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2026-02-23 - 00:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 792 highest latencies:
System rackcslot2.osadl.org (updated Sun Feb 22, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2037027361,8sleep10-21swapper/107:08:161
2044427057,8sleep00-21swapper/007:09:010
20676993333,0cyclictest0-21swapper/010:18:360
2067799287,5cyclictest91rcu_preempt12:25:321
2067799285,3cyclictest0-21swapper/112:14:491
20677992827,0cyclictest24-21ksoftirqd/110:44:531
20677992823,1cyclictest24-21ksoftirqd/111:54:511
20676992810,12cyclictest0-21swapper/009:24:440
2067799270,3cyclictest0-21swapper/110:34:441
2067699277,19cyclictest0-21swapper/011:44:180
2067799264,2cyclictest91rcu_preempt10:09:531
20677992624,1cyclictest24-21ksoftirqd/110:19:461
20677992624,0cyclictest24-21ksoftirqd/112:29:531
20677992619,3cyclictest20674-21cyclictest10:00:121
20677992612,5cyclictest91rcu_preempt08:09:431
20676992617,9cyclictest0-21swapper/011:31:080
2067799256,4cyclictest91rcu_preempt09:19:531
20677992523,1cyclictest0-21swapper/108:19:271
20677992516,4cyclictest24-21ksoftirqd/111:51:551
20677992514,9cyclictest91rcu_preempt11:41:231
2067799250,2cyclictest91rcu_preempt12:34:491
2067799250,1cyclictest91rcu_preempt11:22:191
2067699250,19cyclictest0-21swapper/009:44:250
20677992424,0cyclictest0-21swapper/112:07:161
20677992411,5cyclictest11181-21/usr/sbin/munin10:04:531
20677992411,11cyclictest0-21swapper/111:48:391
2067799240,2cyclictest91rcu_preempt12:10:351
2067799240,2cyclictest0-21swapper/109:53:381
2067799238,4cyclictest91rcu_preempt10:41:011
2067799234,14cyclictest0-21swapper/107:24:511
2067799232,3cyclictest91rcu_preempt08:23:471
20677992323,0cyclictest24-21ksoftirqd/109:19:331
20677992322,1cyclictest24-21ksoftirqd/111:30:311
20677992322,0cyclictest24-21ksoftirqd/109:29:171
2067799232,10cyclictest91rcu_preempt09:47:521
2067799230,2cyclictest91rcu_preempt11:00:401
20676992311,6cyclictest636-21nscd09:50:130
20676992310,6cyclictest0-21swapper/010:25:200
20677992221,0cyclictest24-21ksoftirqd/107:14:511
20677992218,1cyclictest24-21ksoftirqd/110:25:271
20677992217,2cyclictest24-21ksoftirqd/110:49:541
20677992216,4cyclictest24-21ksoftirqd/109:29:511
20677992216,2cyclictest24-21ksoftirqd/109:39:451
20677992215,6cyclictest3771-21apache_accesses09:54:431
2067799221,2cyclictest91rcu_preempt11:34:461
2067799220,1cyclictest91rcu_preempt10:58:481
2067699226,12cyclictest0-21swapper/011:19:450
20676992212,5cyclictest0-21swapper/011:14:510
20676992210,9cyclictest0-21swapper/010:13:490
2067699220,21cyclictest16774-21taskset10:55:020
2067799215,10cyclictest0-21swapper/112:19:551
20677992117,3cyclictest20674-21cyclictest09:11:271
20677992117,2cyclictest24-21ksoftirqd/111:05:541
2067799211,2cyclictest91rcu_preempt07:50:121
20677992110,8cyclictest0-21swapper/111:14:491
20677992110,6cyclictest24-21ksoftirqd/109:34:551
20677992110,6cyclictest0-21swapper/111:14:331
2067699215,7cyclictest0-21swapper/008:24:450
2067699211,8cyclictest0-21swapper/008:57:020
20676992117,3cyclictest636-21nscd10:34:210
20676992113,5cyclictest100150irq/106-eth1-rx09:32:020
20676992110,6cyclictest0-21swapper/011:35:560
20676992110,5cyclictest0-21swapper/012:39:070
20676992110,4cyclictest0-21swapper/011:24:470
20676992110,4cyclictest0-21swapper/008:43:200
2163522010,0sleep10-21swapper/110:18:571
2067799206,2cyclictest91rcu_preempt09:06:071
20677992018,2cyclictest0-21swapper/110:31:021
20677992012,5cyclictest30544-21apache208:33:091
20677992010,5cyclictest0-21swapper/108:39:441
20677992010,5cyclictest0-21swapper/107:34:491
20677992010,3cyclictest0-21swapper/108:24:461
2067799200,1cyclictest91rcu_preempt08:54:531
2067699206,8cyclictest0-21swapper/008:34:510
2067699205,5cyclictest636-21nscd12:03:370
2067699205,10cyclictest0-21swapper/008:49:500
2067699203,8cyclictest0-21swapper/009:09:520
20676992014,3cyclictest0-21swapper/009:19:530
20676992013,5cyclictest30536-21apache209:35:090
20676992013,4cyclictest30536-21apache211:56:140
20676992010,7cyclictest0-21swapper/011:08:100
20676992010,5cyclictest0-21swapper/007:44:470
20676992010,5cyclictest0-21swapper/007:44:470
20676992010,4cyclictest0-21swapper/012:07:550
20676992010,1cyclictest0-21swapper/009:46:480
2067699200,1cyclictest0-21swapper/011:01:380
2067699200,17cyclictest0-21swapper/011:49:540
2067799195,1cyclictest91rcu_preempt07:29:421
20677991912,5cyclictest100250irq/107-eth1-rx07:41:251
20677991912,3cyclictest24-21ksoftirqd/108:34:441
20677991910,4cyclictest24-21ksoftirqd/111:24:521
2067699193,12cyclictest0-21swapper/009:59:520
2067699193,10cyclictest0-21swapper/008:44:530
20676991915,1cyclictest0-21swapper/007:39:520
2067699191,17cyclictest2297-21diskmemload10:23:320
20676991910,5cyclictest0-21swapper/010:39:450
20676991910,5cyclictest0-21swapper/008:09:480
20676991910,2cyclictest0-21swapper/012:29:470
2067799188,5cyclictest231ktimersoftd/108:04:531
20677991811,3cyclictest0-21swapper/108:59:471
20677991810,5cyclictest0-21swapper/112:00:491
2067699184,8cyclictest0-21swapper/012:24:480
2067699183,10cyclictest0-21swapper/007:54:460
2067699181,9cyclictest0-21swapper/007:09:490
20676991816,1cyclictest19589-21df08:29:450
20676991814,4cyclictest100250irq/107-eth1-rx10:07:570
2067699181,16cyclictest0-21swapper/010:44:420
20676991810,6cyclictest0-21swapper/011:10:060
20676991810,4cyclictest0-21swapper/010:34:460
20676991810,4cyclictest0-21swapper/009:14:480
20676991810,4cyclictest0-21swapper/009:04:440
20676991810,3cyclictest0-21swapper/007:29:450
20676991810,2cyclictest0-21swapper/007:14:490
20676991810,1cyclictest0-21swapper/012:20:030
2067699180,13cyclictest0-21swapper/012:14:480
2067799175,8cyclictest0-21swapper/107:19:451
20677991714,1cyclictest24-21ksoftirqd/107:44:501
20677991714,1cyclictest24-21ksoftirqd/107:44:501
2067799171,12cyclictest0-21swapper/108:49:451
20677991710,2cyclictest0-21swapper/108:44:521
2067699175,7cyclictest13605-21/usr/sbin/munin08:14:500
2067699173,10cyclictest0-21swapper/008:04:450
20676991710,5cyclictest0-21swapper/009:54:430
20676991710,2cyclictest0-21swapper/011:45:260
20677991612,3cyclictest6349-21if_err_eth207:54:481
20677991610,4cyclictest24-21ksoftirqd/107:09:521
2067699163,7cyclictest0-21swapper/010:50:140
2067699162,9cyclictest0-21swapper/008:59:460
20676991610,4cyclictest100250irq/107-eth1-rx07:24:510
20676991610,4cyclictest0-21swapper/012:09:420
567221510,0sleep00-21swapper/007:53:480
2067699155,4cyclictest0-21swapper/008:19:450
20676991510,2cyclictest0-21swapper/007:59:440
20676991510,2cyclictest0-21swapper/007:19:540
20677991411,2cyclictest8628-21ntp_states07:59:501
20676991310,1cyclictest0-21swapper/007:34:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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