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2026-01-29 - 04:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the highest latencies:
System rackcslot2.osadl.org (updated Thu Jan 29, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3081821280,0sleep030817-21df_inode21:54:550
277562720,1sleep00-21swapper/021:49:580
1471227253,16sleep10-21swapper/119:06:511
1479827057,8sleep00-21swapper/019:07:440
179722600,1sleep017968-21munin-plugin-st00:34:430
15170994310,32cyclictest20573-21ls20:45:021
15170994310,32cyclictest0-21swapper/123:40:021
15170994210,22cyclictest0-21swapper/100:24:571
15170994010,29cyclictest0-21swapper/122:39:551
15170994010,29cyclictest0-21swapper/120:01:061
15170993912,25cyclictest91rcu_preempt22:32:471
15170993910,28cyclictest13156-21ls21:30:021
15170993910,28cyclictest0-21swapper/120:05:041
15170993810,28cyclictest0-21swapper/120:19:531
15170993810,27cyclictest0-21swapper/120:25:131
15170993810,27cyclictest0-21swapper/100:30:001
15170993810,17cyclictest0-21swapper/122:39:161
15170993714,22cyclictest0-21swapper/123:01:051
15170993710,27cyclictest0-21swapper/121:17:571
15170993710,27cyclictest0-21swapper/121:10:251
15170993710,27cyclictest0-21swapper/100:13:581
15170993710,26cyclictest0-21swapper/123:34:551
15170993710,26cyclictest0-21swapper/123:24:431
15170993710,26cyclictest0-21swapper/121:54:581
15170993710,26cyclictest0-21swapper/119:19:351
15170993710,26cyclictest0-21swapper/100:02:251
15170993710,25cyclictest0-21swapper/100:39:261
15170993710,22cyclictest0-21swapper/121:49:521
15170993612,23cyclictest0-21swapper/122:50:561
15170993612,23cyclictest0-21swapper/122:19:541
15170993612,21cyclictest0-21swapper/119:30:391
15170993610,25cyclictest0-21swapper/123:17:421
15170993610,25cyclictest0-21swapper/123:05:331
15170993610,25cyclictest0-21swapper/121:21:151
15170993610,25cyclictest0-21swapper/120:54:561
15170993610,25cyclictest0-21swapper/100:08:511
15170993610,24cyclictest0-21swapper/100:15:001
15170993518,16cyclictest0-21swapper/122:26:461
15170993511,23cyclictest0-21swapper/120:49:551
15170993510,25cyclictest0-21swapper/123:52:001
15170993510,25cyclictest0-21swapper/119:45:001
15170993510,24cyclictest16229-21ls20:34:581
15170993510,24cyclictest0-21swapper/123:59:171
15170993510,24cyclictest0-21swapper/121:37:191
15170993510,23cyclictest0-21swapper/122:12:451
15170993510,20cyclictest0-21swapper/122:09:371
15170993510,13cyclictest0-21swapper/100:22:191
15170993423,11cyclictest0-21swapper/119:29:381
15170993417,17cyclictest0-21swapper/121:05:001
15170993416,17cyclictest0-21swapper/123:29:361
15170993410,9cyclictest0-21swapper/121:47:311
15170993410,24cyclictest0-21swapper/123:45:221
15170993410,15cyclictest91rcu_preempt22:14:551
15170993410,10cyclictest0-21swapper/121:25:461
15169993410,21cyclictest0-21swapper/023:18:580
15170993312,20cyclictest0-21swapper/122:45:481
15170993210,21cyclictest0-21swapper/123:13:291
15170993210,21cyclictest0-21swapper/121:42:441
15170993210,21cyclictest0-21swapper/120:09:541
15170993113,18cyclictest0-21swapper/122:54:521
15170993110,20cyclictest0-21swapper/119:44:051
15170993110,15cyclictest91rcu_preempt23:33:461
15170993010,17cyclictest0-21swapper/122:00:031
15169993029,0cyclictest81ktimersoftd/023:36:550
15170992910,19cyclictest0-21swapper/119:09:541
15170992910,17cyclictest0-21swapper/119:35:491
1516999290,22cyclictest29887-21ssh23:20:030
1517099282,25cyclictest31390-21ntp_kernel_pll_19:49:591
15170992810,4cyclictest91rcu_preempt20:32:011
1517099270,26cyclictest1942-21perf19:59:431
15170992510,14cyclictest0-21swapper/120:39:581
1517099241,22cyclictest0-21swapper/120:14:541
15169992420,3cyclictest81ktimersoftd/000:04:580
15169992410,6cyclictest0-21swapper/023:07:030
15169992410,6cyclictest0-21swapper/000:26:200
1517099233,20cyclictest0-21swapper/119:19:541
1516999232,20cyclictest28907-21diskmemload21:24:430
15169992321,1cyclictest0-21swapper/019:47:570
15169992312,10cyclictest31621-21kworker/u4:021:27:590
15169992311,7cyclictest100250irq/107-eth1-rx23:41:440
15169992310,8cyclictest0-21swapper/021:17:020
15169992310,7cyclictest0-21swapper/023:31:150
1517099221,20cyclictest0-21swapper/120:59:591
15169992214,3cyclictest0-21swapper/022:24:420
15169992211,8cyclictest25001-21apache221:13:570
15169992210,6cyclictest0-21swapper/023:59:200
15169992210,2cyclictest0-21swapper/022:14:490
1516999214,12cyclictest0-21swapper/019:40:010
1516999213,8cyclictest0-21swapper/021:49:050
15169992117,1cyclictest0-21swapper/023:48:220
15169992112,6cyclictest25001-21apache221:34:550
15169992110,5cyclictest0-21swapper/020:19:540
15169992110,2cyclictest0-21swapper/020:52:420
1182022110,0sleep00-21swapper/021:29:440
1516999206,9cyclictest0-21swapper/019:29:550
15169992020,0cyclictest0-21swapper/023:27:540
1516999201,7cyclictest0-21swapper/020:30:000
15169992014,4cyclictest5170-1kworker/u5:222:04:330
15169992011,6cyclictest0-21swapper/000:03:300
15169992010,5cyclictest0-21swapper/022:54:580
15169992010,5cyclictest0-21swapper/020:10:020
1516999200,16cyclictest0-21swapper/021:41:240
15169991914,2cyclictest9193-21seq00:21:320
15169991912,5cyclictest100150irq/106-eth1-rx22:36:290
15169991911,5cyclictest100150irq/106-eth1-rx22:40:040
15169991910,8cyclictest0-21swapper/023:00:020
1516999183,6cyclictest11707-21/usr/sbin/munin20:24:540
1516999182,4cyclictest0-21swapper/022:09:490
1516999182,10cyclictest0-21swapper/020:44:590
1516999181,7cyclictest0-21swapper/022:46:170
15169991812,2cyclictest100150irq/106-eth1-rx22:06:150
15169991810,5cyclictest0-21swapper/023:09:580
15169991810,5cyclictest0-21swapper/022:27:020
15169991810,5cyclictest0-21swapper/020:55:030
15169991810,4cyclictest0-21swapper/021:06:200
15169991810,2cyclictest0-21swapper/020:15:030
15169991810,1cyclictest0-21swapper/019:34:560
15169991810,1cyclictest0-21swapper/000:35:480
1516999176,5cyclictest0-21swapper/020:34:530
1516999174,9cyclictest0-21swapper/022:49:560
1516999173,9cyclictest4090-21irqstats00:14:560
15169991715,1cyclictest744-21snmpd22:34:220
15169991710,4cyclictest0-21swapper/019:49:540
15169991710,0cyclictest0-21swapper/020:39:590
1516999170,9cyclictest0-21swapper/020:59:580
158121610,0sleep00-21swapper/019:56:140
1516999163,6cyclictest0-21swapper/019:19:530
15169991616,0cyclictest0-21swapper/020:05:140
15169991612,2cyclictest0-21swapper/000:11:010
15169991610,3cyclictest23877-21kworker/0:219:27:210
15169991610,3cyclictest0-21swapper/023:49:430
15169991610,0cyclictest0-21swapper/020:00:030
15169991511,3cyclictest0-21swapper/019:09:550
15169991510,1cyclictest0-21swapper/019:19:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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