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2026-08-22 - 19:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot5.osadl.org (updated Sat Aug 22, 2026 13:06:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5517:14:576482
51,17:14:026481
017:14:026477
0,17:14:026476
0,17:14:026475
0,17:14:026474
0,17:14:026473
0,17:14:026472
0,17:14:026471
0,17:14:026470
0,17:14:026469
0,17:14:026468
0,17:14:026467
0,17:14:026466
0,17:14:026465
0,17:14:026464
0,17:14:026463
0,17:14:026462
0,17:14:026461
0,17:14:026460
0,17:14:026459
0,17:14:026458
0,17:14:026457
0,17:14:026456
0,17:14:026455
0,17:14:026454
0,17:14:026453
0,17:14:026452
0,17:14:026451
0,17:14:026450
0,17:14:026449
0,17:14:026448
0,17:14:026447
0,17:14:026446
0,17:14:026445
0,17:14:026444
0,17:14:026443
0,17:14:026442
0,17:14:026441
0,17:14:026440
0,17:14:026439
0,17:14:026438
0,17:14:026437
0,17:14:026436
0,17:14:026435
0,17:14:026434
0,17:14:026433
0,17:14:026432
0,17:14:026431
0,17:14:026430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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