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2026-01-28 - 08:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jan 28, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1273823993810,1cyclictest0-21swapper/520:59:015
127382399380379,1cyclictest1322800-21kworker/5:321:02:025
127382399380379,1cyclictest1311031-21kworker/5:020:18:025
127382399380379,1cyclictest1311031-21kworker/5:019:19:025
1273823993800,1cyclictest0-21swapper/520:14:025
1273823993800,1cyclictest0-21swapper/520:02:025
127383899374372,1cyclictest0-21swapper/700:19:027
127383899372370,1cyclictest0-21swapper/700:11:017
127383899370369,1cyclictest1475737-21kworker/7:023:00:027
127383899370369,1cyclictest1394580-21kworker/7:221:55:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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