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2025-11-26 - 10:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Nov 26, 2025 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2617350210586,3sleep30-21swapper/319:05:183
27329362950,2sleep442-21ksoftirqd/421:39:474
28269352910,1sleep763-21ksoftirqd/722:53:267
216999900,71rtkit-daemon0-21swapper/419:05:514
29152852890,0sleep10-21swapper/100:03:211
261814928667,3sleep00-21swapper/019:05:230
261906728443,12sleep20-21swapper/219:06:532
27667292830,2sleep549-21ksoftirqd/522:05:185
2619488998117,34cyclictest0-21swapper/100:08:141
2619488998116,34cyclictest0-21swapper/122:58:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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