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2026-03-10 - 22:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 10, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
414043099367364,2cyclictest28597-21kworker/3:011:53:023
414043099366363,2cyclictest28597-21kworker/3:009:47:023
414043099366363,2cyclictest28597-21kworker/3:009:47:023
414043099365363,1cyclictest73873-21kworker/3:211:35:023
414043099365362,2cyclictest28597-21kworker/3:012:09:023
414043099364362,1cyclictest4137286-21kworker/3:208:21:023
414043099364361,2cyclictest28597-21kworker/3:010:27:023
414043099364361,2cyclictest148655-21kworker/3:108:13:023
414043099363362,1cyclictest28597-21kworker/3:011:45:033
414043099362360,1cyclictest28597-21kworker/3:010:37:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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