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2026-05-11 - 10:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon May 11, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122015299364361,1cyclictest1216999-21kworker/3:119:12:023
122013599364363,1cyclictest0-21swapper/100:37:021
122013599363361,1cyclictest0-21swapper/123:21:021
122013599361360,1cyclictest0-21swapper/120:59:021
122013599361360,1cyclictest0-21swapper/120:37:021
122013599361359,2cyclictest1378009-21kworker/1:223:51:021
122013599361359,1cyclictest1290163-21kworker/1:022:05:021
122013599361359,1cyclictest0-21swapper/122:29:021
122016899360359,1cyclictest1504887-21kworker/5:219:12:025
122013599360359,1cyclictest0-21swapper/123:25:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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