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2025-12-03 - 13:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Dec 03, 2025 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8742692126121,2sleep10-21swapper/119:05:251
87276021060,4sleep0111rcuc/019:05:150
216999980,50rtkit-daemon0-21swapper/419:08:484
9761742850,2sleep656-21ksoftirqd/621:29:326
9761742850,2sleep656-21ksoftirqd/621:29:326
875474998516,37cyclictest0-21swapper/500:33:155
875474998516,36cyclictest0-21swapper/523:23:155
11049722850,0sleep40-21swapper/423:10:234
875474998315,38cyclictest0-21swapper/520:43:155
875474998115,35cyclictest0-21swapper/519:18:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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