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2026-07-08 - 14:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jul 08, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1223495993811,379cyclictest0-21swapper/621:13:026
122349599379376,2cyclictest1331378-21kworker/6:121:44:026
122349599379375,2cyclictest1339566-21kworker/6:022:27:026
122349599378376,1cyclictest1242332-21kworker/6:021:26:026
122349599377376,1cyclictest0-21swapper/600:16:026
122349599377375,1cyclictest1242332-21kworker/6:021:21:036
122349599377374,2cyclictest1339566-21kworker/6:022:33:036
122349599377374,2cyclictest1339566-21kworker/6:022:03:026
122349599377374,2cyclictest1242332-21kworker/6:021:32:026
122349599376374,1cyclictest0-21swapper/623:17:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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