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2026-04-05 - 01:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Apr 04, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63742399374373,1cyclictest0-21swapper/511:50:015
63742399373372,1cyclictest640099-21kworker/5:309:00:025
63742399372371,1cyclictest640099-21kworker/5:307:25:015
63742399371370,1cyclictest0-21swapper/512:16:025
63742399371370,1cyclictest0-21swapper/511:20:025
63742399371370,1cyclictest0-21swapper/510:08:015
63742399371369,1cyclictest0-21swapper/509:45:025
63742399370369,1cyclictest770610-21kworker/5:111:01:015
63742399370369,1cyclictest740512-21kworker/5:210:20:025
63742399370369,1cyclictest0-21swapper/512:10:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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