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2026-02-28 - 15:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Feb 28, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
54201599353352,1cyclictest0-21swapper/010:01:020
54201599353352,1cyclictest0-21swapper/009:05:020
54201599352351,1cyclictest597003-21kworker/0:010:21:020
54201599351350,1cyclictest509983-21kworker/0:107:15:020
54201599351350,1cyclictest0-21swapper/011:55:020
54201599350349,1cyclictest0-21swapper/012:15:010
54201599350348,1cyclictest0-21swapper/012:20:020
54201599349348,1cyclictest702301-21kworker/0:111:46:010
54201599349348,1cyclictest702301-21kworker/0:111:36:010
54201599349348,1cyclictest597003-21kworker/0:010:48:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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