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2026-05-23 - 03:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat May 23, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148509099349346,2cyclictest1680432-21kworker/0:019:57:020
148510699344342,1cyclictest0-21swapper/200:36:022
148510699343342,1cyclictest0-21swapper/221:59:022
148510699343342,1cyclictest0-21swapper/221:16:022
148510699342341,1cyclictest0-21swapper/222:30:022
148510699342340,1cyclictest1692574-21kworker/2:023:41:022
148510699341340,1cyclictest0-21swapper/223:10:022
148510699341340,1cyclictest0-21swapper/200:27:012
148510699341339,1cyclictest1728634-21kworker/2:223:31:022
148510699340339,1cyclictest0-21swapper/223:05:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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