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2026-03-27 - 07:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Mar 27, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176269624800,6sleep121-21ksoftirqd/119:05:181
176437199378377,1cyclictest1771181-21kworker/6:121:24:026
176437199377375,1cyclictest0-21swapper/621:19:026
176437199375373,2cyclictest0-21swapper/621:55:026
176437199374372,1cyclictest0-21swapper/623:21:026
176437199373370,2cyclictest0-21swapper/600:36:026
176435099373372,1cyclictest1866398-21kworker/3:022:15:023
176437199372371,1cyclictest0-21swapper/622:22:026
176437199372370,2cyclictest0-21swapper/623:11:026
176435099372370,1cyclictest1866398-21kworker/3:021:38:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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