You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-19 - 04:51
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Jul 19, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114072899373371,1cyclictest0-21swapper/200:10:012
114074299372371,1cyclictest0-21swapper/422:15:014
114072899372370,1cyclictest1333399-21kworker/2:123:13:022
114072899372370,1cyclictest1333399-21kworker/2:123:13:022
114072899372370,1cyclictest0-21swapper/223:00:012
114072899371370,1cyclictest1333399-21kworker/2:122:52:022
114072899371370,1cyclictest0-21swapper/221:39:022
114072899371369,2cyclictest1308787-21kworker/2:022:49:022
114072899371369,1cyclictest1440389-21ssh00:18:012
114072899371369,1cyclictest1264831-21kworker/2:222:33:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional