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2025-11-29 - 11:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Nov 29, 2025 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3702020211090,4sleep20-21swapper/219:05:162
216999950,50rtkit-daemon0-21swapper/019:05:390
37116852930,1sleep30-21swapper/319:19:593
370408228542,36sleep40-21swapper/419:08:084
3704424998415,36cyclictest0-21swapper/322:03:143
370406728241,13sleep70-21swapper/719:07:547
370405228244,13sleep10-21swapper/119:07:411
39738092790,0sleep50-21swapper/523:43:075
38599332780,1sleep7621rcuc/722:11:447
39098532760,1sleep335-21ksoftirqd/322:50:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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