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2026-02-03 - 07:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Feb 03, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3600574993800,1cyclictest0-21swapper/019:37:020
3600574993800,1cyclictest0-21swapper/019:13:020
360058199372368,2cyclictest0-21swapper/123:45:021
360058199368367,1cyclictest3749127-21kworker/1:222:29:021
360058199367366,1cyclictest3640535-21kworker/1:021:48:021
360058199365364,1cyclictest0-21swapper/123:20:021
360058199365363,2cyclictest3827962-21kworker/1:123:54:021
360058199365363,1cyclictest0-21swapper/121:12:021
360058199365363,1cyclictest0-21swapper/121:12:021
360058199365363,1cyclictest0-21swapper/100:24:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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