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2026-02-25 - 21:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Feb 25, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
365266899371370,1cyclictest0-21swapper/211:10:022
365266899371370,1cyclictest0-21swapper/210:55:032
365266899370369,1cyclictest3719676-21kworker/2:012:25:032
365266899370369,1cyclictest3646518-21kworker/2:207:55:012
365266899370369,1cyclictest0-21swapper/211:35:022
365266899370369,1cyclictest0-21swapper/209:01:022
365266899370368,1cyclictest3713652-21kworker/2:108:55:022
365266899369368,1cyclictest3719676-21kworker/2:011:45:022
365266899369368,1cyclictest0-21swapper/209:06:022
365266899369368,1cyclictest0-21swapper/207:50:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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