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2025-11-05 - 04:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Nov 05, 2025 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17324872125103,4sleep60-21swapper/619:05:276
1732276211293,17sleep30-21swapper/319:05:253
1733491999111,55cyclictest1899897-21kworker/7:022:53:117
1733453998916,38cyclictest0-21swapper/219:28:102
1733491998516,38cyclictest0-21swapper/720:48:107
1733453998516,37cyclictest0-21swapper/219:58:112
18708792840,0sleep40-21swapper/422:00:114
1733491998415,35cyclictest0-21swapper/700:13:107
173300928144,12sleep50-21swapper/519:06:155
1733491997714,34cyclictest0-21swapper/719:13:117
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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