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2026-04-01 - 09:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Apr 01, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
349990499381379,1cyclictest3596100-21sh21:28:025
349988399381379,1cyclictest3548817-21kworker/2:120:46:022
349988399381379,1cyclictest3548817-21kworker/2:120:31:022
3499883993810,380cyclictest0-21swapper/219:55:022
3499883993810,380cyclictest0-21swapper/219:35:012
349988399380379,1cyclictest3509721-21kworker/2:019:33:022
349988399380379,1cyclictest3496728-21kworker/2:119:12:022
349988399380378,2cyclictest3521650-21kworker/2:220:17:022
3499883993800,379cyclictest0-21swapper/222:44:022
3499883993800,1cyclictest0-21swapper/223:54:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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