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2026-07-02 - 10:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Jul 02, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
333389499382381,1cyclictest614081-21kworker/0:222:01:020
333389499379378,1cyclictest0-21swapper/021:38:030
333389499379377,2cyclictest614081-21kworker/0:221:16:020
333389499378376,2cyclictest614081-21kworker/0:223:02:020
333389499378376,1cyclictest614081-21kworker/0:221:32:020
333389499377376,1cyclictest614081-21kworker/0:200:33:020
333389499375374,1cyclictest614081-21kworker/0:221:59:030
333389499375374,1cyclictest614081-21kworker/0:221:43:020
333389499375374,1cyclictest0-21swapper/020:27:030
333389499375373,1cyclictest0-21swapper/023:52:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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