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2025-12-31 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Dec 31, 2025 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
339075899386384,1cyclictest3633466-21kworker/0:107:10:020
339077999380379,1cyclictest3587112-21kworker/3:212:36:023
3390779993800,379cyclictest0-21swapper/311:50:023
3390779993800,379cyclictest0-21swapper/311:09:023
3390779993800,379cyclictest0-21swapper/309:42:013
3390779993800,379cyclictest0-21swapper/307:57:013
3390779993800,379cyclictest0-21swapper/307:33:023
3390779993800,1cyclictest0-21swapper/308:41:023
339075899380379,1cyclictest3633466-21kworker/0:108:00:010
339077999379378,1cyclictest3451743-21kworker/3:110:12:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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