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2025-12-09 - 06:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Dec 09, 2025 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304124521060,3sleep549-21ksoftirqd/519:05:135
3043754999318,45cyclictest0-21swapper/400:28:154
3043775999229,34cyclictest0-21swapper/721:23:157
304347928442,13sleep20-21swapper/219:09:062
3043775998315,37cyclictest0-21swapper/719:43:157
3043762998315,38cyclictest0-21swapper/520:48:165
3043775998216,36cyclictest0-21swapper/720:03:167
3043762998216,36cyclictest0-21swapper/520:38:155
3043762998215,38cyclictest0-21swapper/521:33:155
3043762998215,36cyclictest0-21swapper/519:28:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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