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2026-03-26 - 00:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Mar 25, 2026 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130829223490,9sleep442-21ksoftirqd/407:05:264
130918899344342,1cyclictest1595104-21kworker/6:007:15:016
130918899343342,1cyclictest0-21swapper/610:22:026
130918899342341,1cyclictest1373168-21kworker/6:212:09:026
130918899342341,1cyclictest1373168-21kworker/6:211:39:026
130918899342341,1cyclictest1373168-21kworker/6:211:25:026
130918899342341,1cyclictest0-21swapper/611:07:026
130918899342341,1cyclictest0-21swapper/611:00:026
130918899342341,1cyclictest0-21swapper/609:23:026
130918899342341,1cyclictest0-21swapper/608:20:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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