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2026-05-25 - 23:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon May 25, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245709699381380,1cyclictest2644458-21kworker/4:112:27:024
245709699372371,1cyclictest0-21swapper/412:05:024
245709699372371,1cyclictest0-21swapper/412:05:014
245709699372370,1cyclictest0-21swapper/407:20:024
245709699371369,1cyclictest2494014-21kworker/4:212:00:014
245709699370369,1cyclictest2515071-21kworker/4:010:50:024
245709699370369,1cyclictest0-21swapper/410:40:024
245709699370369,1cyclictest0-21swapper/410:40:024
245709699369367,1cyclictest2515071-21kworker/4:011:00:024
245709099369367,1cyclictest97550irq/166-enp0s3110:19:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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