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2026-02-18 - 18:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Feb 18, 2026 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1069265993800,1cyclictest0-21swapper/608:52:026
106926599373372,1cyclictest1302375-21kworker/6:207:28:026
106926599372370,1cyclictest1133229-21kworker/6:212:05:026
106926599371369,1cyclictest1106174-21kworker/6:108:17:026
106926599370368,1cyclictest1133229-21kworker/6:211:40:026
106926599369368,1cyclictest1121200-21kworker/6:008:35:026
106926599369367,2cyclictest1133229-21kworker/6:211:28:026
106926599368367,1cyclictest0-21swapper/608:55:026
106926599367366,1cyclictest1302375-21kworker/6:207:49:026
106926599367366,1cyclictest1302375-21kworker/6:207:49:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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