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2025-11-30 - 12:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Nov 30, 2025 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40324372950,0sleep60-21swapper/619:45:196
1001172930,0sleep60-21swapper/623:55:176
4008059998817,38cyclictest0-21swapper/023:33:140
400768828745,13sleep00-21swapper/019:07:080
4008066998617,38cyclictest0-21swapper/123:43:141
4008066998616,39cyclictest0-21swapper/119:28:141
4008059998614,39cyclictest0-21swapper/020:13:140
4008066998515,39cyclictest0-21swapper/119:38:141
4008066998515,39cyclictest0-21swapper/119:38:141
4008059998516,35cyclictest0-21swapper/020:48:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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