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2026-02-09 - 15:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Feb 09, 2026 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185303299370367,2cyclictest0-21swapper/511:45:025
185303299367366,1cyclictest0-21swapper/507:10:025
185303299365364,1cyclictest0-21swapper/507:25:025
185303299364363,1cyclictest0-21swapper/512:30:025
185303299364363,1cyclictest0-21swapper/512:15:025
185303299364363,1cyclictest0-21swapper/511:00:025
185303299364363,1cyclictest0-21swapper/509:45:015
185303299364363,1cyclictest0-21swapper/509:05:025
185303299364363,1cyclictest0-21swapper/508:50:015
185303299364363,1cyclictest0-21swapper/507:20:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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