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2026-02-02 - 07:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Feb 02, 2026 00:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324742999381378,2cyclictest3413759-21kworker/0:023:52:010
3247429993810,380cyclictest0-21swapper/021:34:020
3247429993810,380cyclictest0-21swapper/020:00:020
3247429993810,1cyclictest0-21swapper/023:25:020
324742999380379,1cyclictest3522658-21kworker/0:200:16:020
324742999380378,1cyclictest3497057-21kworker/0:220:05:020
324742999380378,1cyclictest3413759-21kworker/0:022:47:020
3247429993800,379cyclictest0-21swapper/023:58:010
3247429993800,379cyclictest0-21swapper/023:17:010
3247429993800,379cyclictest0-21swapper/022:07:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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