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2026-05-10 - 20:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun May 10, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110813299356354,1cyclictest1120980-21kworker/3:009:37:023
110813299355353,1cyclictest1120980-21kworker/3:009:51:033
110813299354352,1cyclictest1120980-21kworker/3:010:53:033
110813299353350,2cyclictest1120980-21kworker/3:008:29:013
110813299352351,1cyclictest0-21swapper/310:43:033
110813299352350,1cyclictest1107997-21kworker/3:107:13:023
110813299351349,1cyclictest1120980-21kworker/3:008:21:013
110813299351349,1cyclictest1107997-21kworker/3:107:21:023
110813299351349,1cyclictest0-21swapper/311:15:023
110814699350347,2cyclictest1262372-21kworker/5:012:27:035
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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