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2026-04-27 - 00:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Apr 26, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28855999356355,1cyclictest0-21swapper/510:00:015
28855999355354,1cyclictest0-21swapper/510:10:025
28855999355354,1cyclictest0-21swapper/508:25:025
28855999354353,1cyclictest0-21swapper/509:14:025
28855999354352,1cyclictest0-21swapper/510:09:015
28855999352351,1cyclictest0-21swapper/508:35:025
28855999350349,1cyclictest448850-21kworker/5:011:40:015
28855999350349,1cyclictest0-21swapper/509:48:025
28855999350349,1cyclictest0-21swapper/509:31:025
28855999350348,1cyclictest285402-21kworker/5:107:57:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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