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2026-03-15 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Mar 14, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142701799360359,1cyclictest1394572-21kworker/2:209:05:022
142701799358357,1cyclictest1512082-21kworker/2:109:35:022
142701799358357,1cyclictest0-21swapper/210:15:012
142701799357356,1cyclictest0-21swapper/208:10:012
142701799356355,1cyclictest1512082-21kworker/2:110:14:022
142701799355354,1cyclictest1575262-21kworker/2:211:25:022
142701799354353,1cyclictest1575262-21kworker/2:211:30:022
142701799354353,1cyclictest0-21swapper/212:30:022
142701799354353,1cyclictest0-21swapper/208:28:012
142701799353352,1cyclictest1548185-21kworker/2:011:10:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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