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2026-06-20 - 02:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jun 19, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307623799388387,1cyclictest3253907-21kworker/u16:112:32:027
3076237993820,381cyclictest0-21swapper/709:50:027
307623799381380,1cyclictest3209375-21kworker/7:010:50:027
3076237993810,380cyclictest0-21swapper/711:55:027
3076237993810,380cyclictest0-21swapper/711:55:027
3076237993810,380cyclictest0-21swapper/711:35:027
3076237993810,380cyclictest0-21swapper/708:50:027
307623799380379,1cyclictest3067034-21kworker/7:207:40:027
3076237993800,379cyclictest0-21swapper/711:29:307
3076237993800,379cyclictest0-21swapper/710:40:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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