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2026-09-15 - 04:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Sep 15, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96615099379378,1cyclictest926939-21kworker/7:219:11:017
96611199379377,1cyclictest1201505-21kworker/2:123:35:012
96611199377376,1cyclictest1201505-21kworker/2:100:05:012
96611199377376,1cyclictest0-21swapper/222:55:022
96611199377376,1cyclictest0-21swapper/222:19:022
96611199377375,1cyclictest1233021-21kworker/2:021:19:012
96611199377375,1cyclictest0-21swapper/223:31:022
96611199376375,1cyclictest0-21swapper/223:29:022
96611199375374,1cyclictest0-21swapper/223:07:012
96611199375373,1cyclictest0-21swapper/221:05:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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