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2026-03-23 - 05:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 23, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33955399366365,1cyclictest529064-21kworker/6:200:19:026
33955399365362,2cyclictest0-21swapper/621:32:026
33955399362361,1cyclictest0-21swapper/622:09:026
33955399362359,2cyclictest0-21swapper/622:32:026
33955399362358,3cyclictest0-21swapper/600:32:026
33955399361358,2cyclictest0-21swapper/623:00:026
33955399360359,1cyclictest529064-21kworker/6:223:54:036
33955399360359,1cyclictest0-21swapper/623:39:026
33955399360359,1cyclictest0-21swapper/623:16:036
33955399360358,1cyclictest0-21swapper/623:40:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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