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2026-08-03 - 15:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Aug 03, 2026 00:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239523799355354,1cyclictest2536228-21kworker/7:122:11:027
239523799355354,1cyclictest2536228-21kworker/7:122:11:027
239523799352349,2cyclictest2489507-21kworker/7:021:34:027
239523799349348,1cyclictest0-21swapper/723:09:027
239523799349348,1cyclictest0-21swapper/722:05:027
239523799348347,1cyclictest2549339-21kworker/7:022:38:027
239523799347346,1cyclictest2489507-21kworker/7:022:02:027
239523799343341,1cyclictest2648922-21kworker/7:100:03:027
239523799342341,1cyclictest0-21swapper/700:09:027
239523799342340,1cyclictest0-21swapper/721:49:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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