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2026-01-23 - 17:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jan 23, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
391102123980,5sleep70-21swapper/707:05:137
391360099381380,1cyclictest3947536-21kworker/1:009:36:021
391360099381380,1cyclictest3947536-21kworker/1:009:36:021
391360099380379,1cyclictest3947536-21kworker/1:008:28:021
3913600993800,380cyclictest0-21swapper/108:39:021
391360099379378,1cyclictest3886744-21kworker/1:207:26:021
391360099379378,1cyclictest3886744-21kworker/1:207:23:021
391360099379377,1cyclictest3947536-21kworker/1:010:27:021
391360099379377,1cyclictest3886744-21kworker/1:208:03:021
3913600993790,379cyclictest0-21swapper/111:26:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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