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2026-07-07 - 14:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Jul 07, 2026 00:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
861593993810,380cyclictest0-21swapper/519:53:025
861593993800,379cyclictest0-21swapper/521:07:025
861593993800,379cyclictest0-21swapper/519:14:025
861593993800,1cyclictest0-21swapper/519:18:025
861593993790,379cyclictest0-21swapper/521:02:025
861593993790,378cyclictest0-21swapper/519:56:025
86157099363361,1cyclictest1128308-21kworker/2:100:30:022
86159999361360,1cyclictest0-21swapper/600:30:026
86157099350348,1cyclictest896226-21kworker/2:221:19:022
86159999348347,1cyclictest0-21swapper/621:19:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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