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2026-03-20 - 11:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Mar 20, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345104799381379,1cyclictest3677429-21kworker/4:023:28:024
345104799381379,1cyclictest3518030-21kworker/4:121:15:024
345103499381379,1cyclictest3628372-21kworker/2:200:02:022
345103499381379,1cyclictest3523745-21kworker/2:322:06:022
345103499381379,1cyclictest3523745-21kworker/2:321:43:022
345103499381379,1cyclictest3523745-21kworker/2:321:14:032
345104799380379,1cyclictest3677429-21kworker/4:023:58:024
345104799380379,1cyclictest3518030-21kworker/4:123:03:024
345104799380379,1cyclictest3518030-21kworker/4:122:42:024
345104799380379,1cyclictest3518030-21kworker/4:122:24:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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