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2025-12-04 - 15:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Dec 04, 2025 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14833212135117,2sleep50-21swapper/507:05:235
14830462135116,17sleep30-21swapper/307:05:213
149845021090,1sleep228-21ksoftirqd/207:30:122
1484540999832,38cyclictest0-21swapper/510:23:155
1484524999215,40cyclictest0-21swapper/310:03:163
1484500998715,38cyclictest0-21swapper/007:43:150
1484540998215,36cyclictest0-21swapper/510:48:155
1484500998115,36cyclictest0-21swapper/010:33:150
15586552800,1sleep010-21ksoftirqd/009:05:180
1484540998015,36cyclictest0-21swapper/512:28:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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