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2026-04-22 - 22:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Apr 22, 2026 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304793499371369,1cyclictest0-21swapper/212:31:022
304793499371369,1cyclictest0-21swapper/210:27:022
304793499371369,1cyclictest0-21swapper/207:13:032
304793499370368,1cyclictest0-21swapper/210:55:022
304793499370368,1cyclictest0-21swapper/209:05:022
304793499370368,1cyclictest0-21swapper/208:41:022
304793499369367,1cyclictest0-21swapper/212:11:022
304793499369367,1cyclictest0-21swapper/211:03:022
304793499369367,1cyclictest0-21swapper/210:37:022
304793499369367,1cyclictest0-21swapper/210:31:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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