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2026-01-30 - 06:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jan 30, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
210283699364363,1cyclictest0-21swapper/622:14:016
210283699364362,1cyclictest2388632-21kworker/6:000:39:016
210283699364362,1cyclictest0-21swapper/623:02:026
210283699364362,1cyclictest0-21swapper/622:22:026
210283699364362,1cyclictest0-21swapper/600:02:016
210283699363362,1cyclictest0-21swapper/623:23:016
210283699363362,1cyclictest0-21swapper/622:04:016
210283699363362,1cyclictest0-21swapper/622:04:016
210283699363361,1cyclictest0-21swapper/623:39:016
210283699363361,1cyclictest0-21swapper/623:07:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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