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2026-09-24 - 18:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Sep 24, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20594799371370,1cyclictest357206-21kworker/0:012:20:020
20594799370369,1cyclictest0-21swapper/009:38:020
20594799370369,1cyclictest0-21swapper/009:38:020
20597299369368,1cyclictest202829-21kworker/3:207:15:023
20594799369368,1cyclictest0-21swapper/010:43:020
20597299368367,1cyclictest0-21swapper/308:25:023
20594799368367,1cyclictest0-21swapper/008:38:020
20594799367366,1cyclictest486520-21kworker/0:207:25:020
20597299366365,1cyclictest0-21swapper/308:43:023
20594799366365,1cyclictest486520-21kworker/0:209:17:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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