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2026-03-12 - 17:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Mar 12, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
711605993800,379cyclictest0-21swapper/610:18:026
711605993800,1cyclictest0-21swapper/611:34:026
711605993800,1cyclictest0-21swapper/609:19:026
71157699369367,1cyclictest0-21swapper/211:45:022
71157699367366,1cyclictest0-21swapper/211:56:022
71157699367366,1cyclictest0-21swapper/211:56:012
71157699367366,1cyclictest0-21swapper/208:39:022
71157699367365,1cyclictest0-21swapper/210:35:022
71157699367365,1cyclictest0-21swapper/208:40:022
71157699366365,1cyclictest0-21swapper/209:20:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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