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2026-03-19 - 07:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Mar 19, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300156499382380,1cyclictest0-21swapper/700:01:027
3001510993821,380cyclictest0-21swapper/019:50:010
300156499381379,2cyclictest3102119-21kworker/7:022:03:027
300151099381380,1cyclictest3265124-21kworker/0:019:37:020
300151099380378,1cyclictest3265124-21kworker/0:020:26:020
3001510993800,379cyclictest0-21swapper/020:01:020
300156499379377,1cyclictest0-21swapper/723:51:027
300156499379377,1cyclictest0-21swapper/700:29:017
300156499378376,1cyclictest0-21swapper/722:43:017
300156499377376,1cyclictest0-21swapper/723:06:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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