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2026-03-07 - 16:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Mar 06, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
268984199382380,1cyclictest2943856-21kworker/1:108:01:021
268984199380379,1cyclictest2726779-21kworker/1:010:01:021
268984199380379,1cyclictest0-21swapper/111:41:021
268984199380379,1cyclictest0-21swapper/110:23:011
268984199380378,1cyclictest2943856-21kworker/1:107:58:011
268984199380378,1cyclictest2943856-21kworker/1:107:50:011
268984199380378,1cyclictest2943856-21kworker/1:107:35:021
268984199380378,1cyclictest2850123-21kworker/1:112:05:021
268984199380378,1cyclictest2726779-21kworker/1:010:05:021
268984199380378,1cyclictest2726779-21kworker/1:010:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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