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2025-12-25 - 13:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Dec 25, 2025 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66759299369365,2cyclictest701486-21kworker/7:120:15:027
66758699367366,1cyclictest0-21swapper/621:11:026
66758699366365,1cyclictest0-21swapper/623:53:036
66758699366364,1cyclictest0-21swapper/622:07:026
66758699365364,1cyclictest0-21swapper/621:35:026
66758699365363,1cyclictest0-21swapper/623:25:026
66758699364363,1cyclictest0-21swapper/600:18:036
66758699363362,1cyclictest0-21swapper/623:03:026
66758699363362,1cyclictest0-21swapper/621:22:036
66758699362361,1cyclictest953421-21kworker/6:100:33:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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