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2026-08-10 - 22:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Aug 10, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
831094993820,381cyclictest0-21swapper/111:51:031
831094993820,381cyclictest0-21swapper/110:29:031
831094993820,381cyclictest0-21swapper/109:49:021
831094993820,381cyclictest0-21swapper/109:19:021
83112099381380,1cyclictest964371-21kworker/4:111:09:024
83112099381380,1cyclictest837790-21kworker/4:108:43:024
83112099381380,1cyclictest837790-21kworker/4:108:43:024
83112099381380,1cyclictest1003527-21kworker/4:012:32:034
831094993810,2cyclictest0-21swapper/112:29:021
831094993810,1cyclictest0-21swapper/111:23:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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