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2026-02-16 - 23:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Feb 16, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
326423993810,380cyclictest0-21swapper/308:59:023
32642399380379,1cyclictest453625-21kworker/3:111:47:023
32642399380379,1cyclictest372386-21kworker/3:209:53:023
326423993790,1cyclictest0-21swapper/307:12:023
32644199324321,3cyclictest375394-21kworker/5:008:52:035
32643499317315,2cyclictest291456-21kworker/4:008:15:024
32643499315313,1cyclictest0-21swapper/411:25:024
32643499314313,1cyclictest0-21swapper/410:35:024
32643499314313,1cyclictest0-21swapper/407:25:024
32643499314312,1cyclictest0-21swapper/412:06:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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