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2026-01-01 - 12:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Jan 01, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
351411399380379,1cyclictest3810824-21kworker/2:019:48:022
351411399322320,1cyclictest3818630-21ssh00:16:022
351413799320319,1cyclictest3623263-21kworker/5:021:46:025
351410799318317,1cyclictest0-21swapper/121:46:021
351412299317315,1cyclictest3731616-21kworker/3:223:11:033
351411399314313,1cyclictest3766844-21kworker/2:200:20:022
351411399314312,1cyclictest0-21swapper/223:43:022
351411399314312,1cyclictest0-21swapper/223:32:022
351412299313311,1cyclictest0-21swapper/319:15:033
351411399313312,1cyclictest3810824-21kworker/2:019:10:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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