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2026-07-29 - 11:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jul 29, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
638670993800,379cyclictest0-21swapper/419:35:024
638670993800,379cyclictest0-21swapper/419:35:024
63867899377376,1cyclictest0-21swapper/523:23:025
63867899376374,1cyclictest702653-21kworker/5:023:07:035
63867899375374,1cyclictest0-21swapper/522:45:025
63869299374373,1cyclictest0-21swapper/722:23:037
63867899374372,1cyclictest702653-21kworker/5:023:15:025
63867899373372,1cyclictest0-21swapper/522:53:025
63867899373372,1cyclictest0-21swapper/522:11:035
63867899373371,1cyclictest702653-21kworker/5:023:49:035
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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