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2026-09-21 - 16:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Sep 21, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
333006299342341,1cyclictest3329941-21kworker/1:107:45:021
333006299341339,1cyclictest3433166-21kworker/1:012:05:021
333006299340338,1cyclictest0-21swapper/109:20:021
333006299339338,1cyclictest3433166-21kworker/1:011:50:021
333006299339337,1cyclictest0-21swapper/112:20:011
333006299337336,1cyclictest3372683-21kworker/1:208:24:021
333006299337335,2cyclictest0-21swapper/112:00:021
333006299337335,1cyclictest3433166-21kworker/1:011:00:021
333006299337335,1cyclictest3433166-21kworker/1:010:46:021
333006299337335,1cyclictest0-21swapper/112:26:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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