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2026-09-06 - 15:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Sep 06, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216256723820,4sleep5481rcuc/507:05:185
216412699381380,1cyclictest2306152-21kworker/3:012:09:023
216412699381380,1cyclictest2248929-21kworker/3:310:36:023
216412699381379,1cyclictest2427569-21kworker/3:208:12:023
216412699381379,1cyclictest2427569-21kworker/3:207:47:023
216412699381379,1cyclictest2427569-21kworker/3:207:37:023
216412699381379,1cyclictest2420981-21kworker/3:108:26:023
216412699381379,1cyclictest2306152-21kworker/3:011:43:023
216412699381379,1cyclictest2248929-21kworker/3:310:14:023
216412699381379,1cyclictest2248929-21kworker/3:309:37:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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