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2026-09-05 - 14:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Sep 05, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1566772993830,380cyclictest1750329-21systemd-userwor22:46:024
156677299381379,2cyclictest1709210-21kworker/4:123:44:024
156677299381379,1cyclictest1709210-21kworker/4:100:25:024
156678799380379,1cyclictest1862841-21kworker/6:219:58:026
156678799380379,1cyclictest1862841-21kworker/6:219:23:026
156678799380378,1cyclictest1862841-21kworker/6:219:39:026
156677299380379,1cyclictest1709210-21kworker/4:122:23:024
156677299380379,1cyclictest1709210-21kworker/4:100:13:024
156677299380379,1cyclictest1709210-21kworker/4:100:13:024
156678799379378,1cyclictest1862841-21kworker/6:219:54:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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