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2026-04-25 - 23:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Apr 25, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
412417299367365,1cyclictest0-21swapper/308:00:023
412417299365364,1cyclictest4114997-21kworker/3:009:30:023
412417299365364,1cyclictest0-21swapper/310:23:023
412417299365363,1cyclictest0-21swapper/312:01:023
412417299364363,1cyclictest4114997-21kworker/3:010:33:023
412417299364363,1cyclictest0-21swapper/307:20:033
412417299363362,1cyclictest4114997-21kworker/3:010:51:033
412417299363362,1cyclictest0-21swapper/309:20:023
412417299363362,1cyclictest0-21swapper/307:25:033
412417299363361,1cyclictest0-21swapper/310:10:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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