You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-30 - 04:03
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Dec 30, 2025 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
272305599374372,1cyclictest0-21swapper/021:35:020
272305599366364,1cyclictest0-21swapper/023:43:020
272305599363361,1cyclictest2943782-21kworker/0:219:10:020
272305599363360,2cyclictest2825870-21diskmemload21:33:020
272305599362359,2cyclictest2925746-21kworker/0:000:39:020
272305599361359,1cyclictest2925746-21kworker/0:023:47:020
272305599360359,1cyclictest2925746-21kworker/0:023:55:010
272305599360358,1cyclictest2796462-21kworker/0:122:21:010
272305599360358,1cyclictest2796462-21kworker/0:121:47:010
272305599360358,1cyclictest0-21swapper/023:07:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional