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2026-02-09 - 03:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Feb 08, 2026 12:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1489033993831,1cyclictest0-21swapper/312:31:023
148904899382380,1cyclictest97550irq/166-enp0s3109:40:025
148904899381380,1cyclictest97550irq/166-enp0s3111:44:035
1489033993810,1cyclictest0-21swapper/309:37:023
1489033993810,0cyclictest0-21swapper/308:37:033
148902499381379,1cyclictest1513905-21kworker/2:108:31:022
148902499381379,1cyclictest0-21swapper/211:02:022
1489053993800,1cyclictest0-21swapper/609:22:036
148904899380379,1cyclictest97550irq/166-enp0s3110:01:025
148904899380379,1cyclictest0-21swapper/508:55:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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