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2025-11-22 - 09:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Nov 22, 2025 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11789459913956,69cyclictest0-21swapper/022:38:130
11774712135117,16sleep60-21swapper/619:05:196
1178945999930,38cyclictest0-21swapper/020:43:130
117795929778,17sleep30-21swapper/319:05:243
1178945998615,37cyclictest0-21swapper/023:23:130
117847128642,30sleep20-21swapper/219:06:032
117868228543,13sleep70-21swapper/719:09:057
12185332840,0sleep30-21swapper/320:10:123
1178952998420,38cyclictest0-21swapper/123:43:131
1178989998316,36cyclictest0-21swapper/622:23:126
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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