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2026-03-04 - 22:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Mar 04, 2026 12:46:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
196409499382380,1cyclictest2094601-21kworker/5:112:06:025
196405399382380,1cyclictest2010020-21kworker/0:009:16:020
1964102993811,1cyclictest0-21swapper/611:45:026
196409499381380,1cyclictest2202551-21kworker/5:207:28:025
196409499381380,1cyclictest2094601-21kworker/5:112:17:025
196409499381379,1cyclictest2202551-21kworker/5:210:08:025
196409499381379,1cyclictest2202551-21kworker/5:209:18:025
196409499381379,1cyclictest2094601-21kworker/5:111:16:025
196405399381380,1cyclictest2073199-21kworker/0:211:46:020
196405399381380,1cyclictest2010020-21kworker/0:010:07:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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