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2026-02-17 - 05:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Feb 17, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44581399380378,1cyclictest528096-21kworker/0:023:38:020
44584699379377,1cyclictest0-21swapper/423:38:024
44586699329327,1cyclictest618604-21kworker/7:223:16:027
44586699327326,1cyclictest0-21swapper/700:29:017
44586699326324,1cyclictest0-21swapper/722:55:027
44586699325323,1cyclictest0-21swapper/723:45:027
44586699324321,2cyclictest575913-21kworker/7:022:05:027
44586699323322,1cyclictest0-21swapper/723:07:027
44586699323322,1cyclictest0-21swapper/722:25:027
44586699323321,1cyclictest618604-21kworker/7:222:50:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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