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2026-03-24 - 03:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 24, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70203999344343,1cyclictest975547-21kworker/7:023:59:017
70203499337336,1cyclictest0-21swapper/621:25:026
70203999318317,1cyclictest0-21swapper/722:44:027
70198699317316,1cyclictest753970-21kworker/0:021:25:020
70202699313311,1cyclictest0-21swapper/500:00:015
70202699312311,1cyclictest0-21swapper/522:52:025
70202699312310,1cyclictest939762-21kworker/5:000:13:025
70203999311309,2cyclictest823904-21kworker/7:122:21:027
70203999310308,1cyclictest0-21swapper/721:54:027
70203999310307,2cyclictest672966-21kworker/7:021:42:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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