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2026-01-12 - 14:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Jan 12, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
366443899379378,1cyclictest3692321-21kworker/5:121:59:015
366442399379377,2cyclictest3853102-21kworker/3:022:59:013
366442399378376,1cyclictest3853102-21kworker/3:000:07:013
366442399377375,1cyclictest0-21swapper/300:13:023
366439899377376,1cyclictest0-21swapper/019:23:010
366443899376375,1cyclictest3692321-21kworker/5:122:45:015
366442399375374,1cyclictest3680276-21kworker/3:222:17:023
366442399374373,1cyclictest3853102-21kworker/3:023:15:023
366442399371368,2cyclictest3680276-21kworker/3:220:29:013
366442399371367,1cyclictest3945918-40updatedb00:00:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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