You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-26 - 11:42
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Apr 26, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3668499378377,1cyclictest0-21swapper/000:00:020
3668499377376,1cyclictest0-21swapper/021:31:020
3668499376375,1cyclictest0-21swapper/022:44:020
3668499376375,1cyclictest0-21swapper/000:25:020
3668499376375,1cyclictest0-21swapper/000:25:020
3668499375374,1cyclictest0-21swapper/023:41:020
3668499375374,1cyclictest0-21swapper/023:06:020
3668499375373,1cyclictest94319-21kworker/u16:120:43:020
3670399374372,1cyclictest0-21swapper/221:17:022
3668499374373,1cyclictest0-21swapper/023:52:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional