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2026-08-05 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Aug 05, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323371699377375,1cyclictest0-21swapper/610:19:026
323371699345344,1cyclictest3335637-21kworker/6:112:36:016
323371699344343,1cyclictest0-21swapper/612:10:026
323370999344342,1cyclictest0-21swapper/510:19:015
323371699343342,1cyclictest3249798-21kworker/6:009:20:026
323371699341340,1cyclictest3249798-21kworker/6:010:30:016
323371699339338,1cyclictest3562630-21kworker/6:108:01:026
323371699338337,1cyclictest3335637-21kworker/6:112:17:026
323371699338337,1cyclictest3335637-21kworker/6:112:09:026
323371699338337,1cyclictest0-21swapper/611:01:016
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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