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2026-02-22 - 20:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Feb 22, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
253254899376374,1cyclictest0-21swapper/509:15:025
253254899375374,1cyclictest0-21swapper/509:55:025
253254899375373,1cyclictest0-21swapper/509:00:025
253254899375373,1cyclictest0-21swapper/508:27:035
253254899374373,1cyclictest0-21swapper/510:05:025
253254899374373,1cyclictest0-21swapper/509:05:025
253254899373371,1cyclictest0-21swapper/510:15:025
253254899372371,1cyclictest0-21swapper/512:14:025
253254899372371,1cyclictest0-21swapper/508:45:025
253254899372371,1cyclictest0-21swapper/508:08:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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