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2026-04-09 - 11:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Apr 09, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
219371999382378,2cyclictest2206314-21kworker/5:121:52:025
219371999380378,1cyclictest2206314-21kworker/5:122:10:025
219371999380378,1cyclictest2206314-21kworker/5:100:24:015
2193719993800,379cyclictest0-21swapper/522:20:015
219370799380379,1cyclictest0-21swapper/321:45:023
219371999379378,1cyclictest2206314-21kworker/5:123:17:025
219371999379377,1cyclictest2206314-21kworker/5:121:19:025
2193719993790,378cyclictest0-21swapper/521:29:025
219371999378377,1cyclictest2206314-21kworker/5:122:59:025
219371999378377,1cyclictest2206314-21kworker/5:122:03:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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