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2026-07-10 - 18:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jul 10, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2209147993830,382cyclictest0-21swapper/112:11:021
2209147993830,382cyclictest0-21swapper/108:47:021
2209147993830,382cyclictest0-21swapper/107:43:021
2209147993822,379cyclictest0-21swapper/108:53:021
2209147993820,381cyclictest0-21swapper/110:27:021
2209147993820,381cyclictest0-21swapper/109:52:031
2209147993820,381cyclictest0-21swapper/109:27:021
2209147993820,381cyclictest0-21swapper/109:21:021
220914799381379,1cyclictest0-21swapper/110:42:021
2209147993810,381cyclictest0-21swapper/111:57:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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