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2026-06-16 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Jun 16, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
173034399381379,1cyclictest1800331-21kworker/7:021:09:027
1730343993810,380cyclictest0-21swapper/719:10:027
1730343993810,380cyclictest0-21swapper/719:10:027
1730329993810,380cyclictest0-21swapper/523:33:025
173034399380379,1cyclictest1779158-21kworker/7:120:48:027
173034399380379,1cyclictest1779158-21kworker/7:120:48:027
173034399380379,1cyclictest1749139-21kworker/7:120:09:027
173034399380379,1cyclictest1749139-21kworker/7:119:47:027
1730343993800,1cyclictest0-21swapper/719:42:027
173032999380378,1cyclictest1825879-21kworker/5:022:56:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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