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2025-08-27 - 02:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Aug 26, 2025 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63732824880,7sleep00-21swapper/007:05:240
638790993790,379cyclictest0-21swapper/709:25:027
63875599379378,1cyclictest795222-21kworker/2:112:10:032
63879099378377,1cyclictest601906-21kworker/7:207:14:027
63875599378376,1cyclictest770327-21kworker/2:210:48:022
63879099377376,1cyclictest686291-21kworker/7:009:20:037
63875599377375,1cyclictest782771-21kworker/2:011:15:032
63758523770,5sleep20-21swapper/207:05:262
63879099376375,1cyclictest686291-21kworker/7:010:45:037
63879099376375,1cyclictest601906-21kworker/7:207:53:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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