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2025-05-09 - 05:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri May 09, 2025 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3620247993810,380cyclictest0-21swapper/322:03:033
362024799380379,1cyclictest3840670-21kworker/3:100:37:023
362024799380379,1cyclictest3840670-21kworker/3:100:10:013
362024799380379,1cyclictest3764659-21kworker/3:222:18:013
362024799380379,1cyclictest3626820-21kworker/3:119:27:023
3620247993800,379cyclictest0-21swapper/320:27:023
362024799379378,1cyclictest3626820-21kworker/3:121:11:023
362024799379377,1cyclictest3822780-21kworker/3:122:58:013
362024799379377,1cyclictest3626820-21kworker/3:121:33:023
362024799379376,2cyclictest3840670-21kworker/3:123:38:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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