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2026-03-06 - 14:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Mar 06, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244158999384379,2cyclictest2602066-21systemd-userwor22:28:020
244158999380378,1cyclictest2644613-21kworker/0:023:29:020
2441589993800,1cyclictest2702007-21sh23:47:020
244158999379378,1cyclictest2644613-21kworker/0:000:13:020
244158999379377,1cyclictest2644613-21kworker/0:023:35:020
244158999378377,1cyclictest2644613-21kworker/0:023:10:020
244158999378377,1cyclictest0-21swapper/021:56:020
244158999378376,1cyclictest2429429-21kworker/0:221:25:020
244158999377376,1cyclictest2429429-21kworker/0:221:05:020
244158999377376,1cyclictest0-21swapper/023:30:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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