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2026-06-24 - 04:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jun 24, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
42172299385382,1cyclictest0-21swapper/719:55:027
42169199375373,1cyclictest0-21swapper/322:03:023
42169199369367,2cyclictest0-21swapper/321:38:023
42169199366365,1cyclictest623715-21kworker/3:000:05:023
42169199365364,1cyclictest504369-21kworker/3:121:23:023
42169199364363,1cyclictest0-21swapper/323:30:023
42169199364362,1cyclictest0-21swapper/300:12:013
42169199363361,2cyclictest504369-21kworker/3:122:34:023
42169199363361,1cyclictest97550irq/166-enp0s3121:46:023
42169199362361,1cyclictest0-21swapper/323:45:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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