You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-28 - 15:20
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Mar 28, 2026 12:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
235739599370368,1cyclictest1370548-21kworker/5:209:15:025
235739599368367,1cyclictest1370548-21kworker/5:211:27:025
235739599367366,1cyclictest1370548-21kworker/5:209:33:025
235739599367366,1cyclictest1370548-21kworker/5:209:13:025
235739599366365,1cyclictest1370548-21kworker/5:211:11:025
235739599366365,1cyclictest1370548-21kworker/5:210:15:025
235739599366365,1cyclictest1370548-21kworker/5:209:49:025
235739599366365,1cyclictest1370548-21kworker/5:209:21:025
235739599365364,1cyclictest1370548-21kworker/5:212:15:025
235739599365364,1cyclictest1370548-21kworker/5:208:13:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional