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2026-03-24 - 19:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 24, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95085724090,4sleep60-21swapper/607:05:296
951491993810,380cyclictest0-21swapper/408:35:014
95149199380379,1cyclictest1205273-21kworker/4:009:01:014
95149199380379,1cyclictest1024217-21kworker/4:210:05:024
95149199380378,1cyclictest1054617-21kworker/4:010:34:024
95149199379378,1cyclictest1128405-21kworker/4:212:30:034
95149199379378,1cyclictest1128405-21kworker/4:212:20:024
95149199378377,1cyclictest1128405-21kworker/4:212:05:024
95149199378377,1cyclictest0-21swapper/411:15:014
95149199378376,1cyclictest1024217-21kworker/4:209:22:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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