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2026-09-18 - 08:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Sep 18, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201383699381380,1cyclictest3489589-21kworker/4:119:25:024
201383699381380,1cyclictest2213541-21kworker/4:023:00:024
201383699380379,1cyclictest2231005-21kworker/4:300:29:024
201383699379378,1cyclictest3489589-21kworker/4:120:30:024
201383699378377,1cyclictest3489589-21kworker/4:120:22:024
201383699378376,1cyclictest3489589-21kworker/4:119:11:024
201383699378376,1cyclictest3489589-21kworker/4:119:11:024
201383699376375,1cyclictest3489589-21kworker/4:120:16:024
201383699376375,1cyclictest3489589-21kworker/4:119:16:024
201383699376374,1cyclictest3489589-21kworker/4:119:21:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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