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2026-06-09 - 07:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Jun 09, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3444572993800,1cyclictest0-21swapper/520:16:025
344455799380379,1cyclictest3601616-21kworker/3:022:56:023
344453999380379,1cyclictest3733310-21kworker/1:120:16:021
344455799379378,1cyclictest3652745-21kworker/3:100:25:023
344455799379375,2cyclictest3601616-21kworker/3:022:27:023
344455799378377,1cyclictest3469439-21kworker/3:221:51:023
344455799378375,2cyclictest0-21swapper/322:19:023
344455799377376,1cyclictest0-21swapper/323:41:013
344455799377376,1cyclictest0-21swapper/322:01:023
344455799377376,1cyclictest0-21swapper/321:38:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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