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2026-04-19 - 19:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Apr 19, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195424899381379,1cyclictest0-21swapper/112:06:011
1954248993810,380cyclictest0-21swapper/111:08:011
1954248993810,380cyclictest0-21swapper/109:47:021
1954248993810,380cyclictest0-21swapper/108:48:021
195424899380379,1cyclictest0-21swapper/111:21:021
195424899380379,1cyclictest0-21swapper/107:48:021
1954248993800,379cyclictest0-21swapper/111:28:021
1954248993800,379cyclictest0-21swapper/111:15:021
1954248993800,379cyclictest0-21swapper/110:37:021
1954248993800,1cyclictest0-21swapper/110:52:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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