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2026-04-28 - 13:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Apr 28, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77613199381379,1cyclictest769980-21kworker/3:121:56:013
77615999380379,1cyclictest927007-21kworker/6:022:24:026
77615999379377,1cyclictest0-21swapper/600:11:016
77613199379378,1cyclictest0-21swapper/321:46:023
77613199379378,1cyclictest0-21swapper/321:46:023
77615999378377,1cyclictest0-21swapper/623:12:026
77615999378377,1cyclictest0-21swapper/623:12:026
77613199378376,2cyclictest769980-21kworker/3:122:37:023
77613199378376,1cyclictest0-21swapper/322:47:013
77615999377376,1cyclictest0-21swapper/622:35:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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