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2026-02-24 - 08:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Feb 24, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
302194699381379,1cyclictest3088918-21kworker/6:021:18:026
302194699380379,1cyclictest3088918-21kworker/6:021:53:026
302194699380378,1cyclictest3211627-21kworker/6:323:08:026
3021946993800,380cyclictest0-21swapper/620:12:026
3021946993800,379cyclictest0-21swapper/621:07:026
3021946993800,1cyclictest0-21swapper/620:27:026
3021946993800,1cyclictest0-21swapper/619:54:026
302194699378376,1cyclictest3267457-21kworker/6:119:14:036
302192499305304,1cyclictest3226057-21kworker/3:123:43:023
302192499305304,1cyclictest0-21swapper/323:11:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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