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2026-09-11 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Sep 11, 2026 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
398493599356355,1cyclictest43995-21kworker/1:107:25:021
398493599352351,1cyclictest97550irq/166-enp0s3107:15:011
398493599349347,1cyclictest97550irq/166-enp0s3112:25:021
398493599349347,1cyclictest97550irq/166-enp0s3110:05:021
398493599348347,1cyclictest97550irq/166-enp0s3111:33:021
398493599348347,1cyclictest97550irq/166-enp0s3110:34:011
398493599348347,1cyclictest97550irq/166-enp0s3110:34:011
398493599348346,1cyclictest97550irq/166-enp0s3111:59:021
398493599348346,1cyclictest97550irq/166-enp0s3111:59:021
398493599348346,1cyclictest97550irq/166-enp0s3111:43:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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