You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-14 - 00:34
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed May 13, 2026 12:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
219245799341340,1cyclictest2373462-21kworker/0:210:15:010
219245799341339,1cyclictest2373462-21kworker/0:212:01:010
219248999340339,1cyclictest0-21swapper/410:15:014
219245799340339,1cyclictest2373462-21kworker/0:207:40:020
219245799340339,1cyclictest0-21swapper/008:35:020
219245799340338,1cyclictest2373462-21kworker/0:211:35:020
219248999339338,1cyclictest0-21swapper/407:40:024
219245799339338,1cyclictest0-21swapper/011:05:010
219248999338337,1cyclictest2280520-21kworker/4:211:05:024
219248999338337,1cyclictest2214338-21kworker/4:108:35:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional