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2025-12-21 - 05:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Dec 21, 2025 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321126499381378,1cyclictest0-21swapper/620:25:026
321122999380379,1cyclictest3407487-21kworker/1:219:11:021
321126499379377,1cyclictest3488977-21kworker/6:000:17:026
321126499379377,1cyclictest3445107-21kworker/6:223:19:026
321122999379378,1cyclictest3407487-21kworker/1:220:58:021
321122999379378,1cyclictest3407487-21kworker/1:220:23:021
321126499378376,1cyclictest3334253-21kworker/6:122:43:026
321126499378376,1cyclictest3275217-21kworker/6:021:13:036
321126499378376,1cyclictest3275217-21kworker/6:021:13:026
321126499377376,1cyclictest3334253-21kworker/6:121:57:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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