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2026-04-10 - 07:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Apr 10, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
256271799381380,1cyclictest2839697-21kworker/0:020:14:030
256271799380378,1cyclictest2839697-21kworker/0:019:49:010
256274299374372,1cyclictest2688524-21kworker/3:023:09:033
256275899373372,1cyclictest2770675-21kworker/5:123:45:035
256274299371370,1cyclictest2688524-21kworker/3:023:45:023
256274299371369,1cyclictest2688524-21kworker/3:000:09:023
256275899370369,1cyclictest2529839-21kworker/5:020:01:025
256275899370368,1cyclictest2770675-21kworker/5:100:29:025
256274299370369,1cyclictest2688524-21kworker/3:022:29:023
256274299370368,1cyclictest2688524-21kworker/3:023:15:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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