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2026-05-20 - 02:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue May 19, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16091299336334,1cyclictest0-21swapper/709:50:027
16091299334333,1cyclictest0-21swapper/709:10:027
16091299333332,1cyclictest0-21swapper/712:13:027
16091299333332,1cyclictest0-21swapper/711:39:027
16091299333332,1cyclictest0-21swapper/708:55:027
16091299332331,1cyclictest0-21swapper/712:05:027
16091299332331,1cyclictest0-21swapper/711:33:027
16091299332331,1cyclictest0-21swapper/710:50:017
16091299332331,1cyclictest0-21swapper/710:00:027
16091299332331,1cyclictest0-21swapper/709:59:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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