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2026-08-21 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Aug 21, 2026 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33697699378377,1cyclictest0-21swapper/121:34:021
33697699378377,1cyclictest0-21swapper/121:15:021
33697699373372,1cyclictest0-21swapper/120:30:031
33699699368366,1cyclictest427523-21kworker/3:123:32:153
33697699367365,1cyclictest0-21swapper/121:25:021
33697699365364,1cyclictest0-21swapper/122:53:021
33702599362361,1cyclictest0-21swapper/723:32:157
33697699360359,1cyclictest0-21swapper/121:49:021
33697699358357,1cyclictest0-21swapper/123:37:021
33534723480,5sleep442-21ksoftirqd/419:05:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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