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2026-05-28 - 15:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu May 28, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
353546799368367,1cyclictest809563-21kworker/0:010:50:020
353546799364363,1cyclictest809563-21kworker/0:011:50:030
353546799362361,1cyclictest809563-21kworker/0:011:30:020
353546799362361,1cyclictest0-21swapper/012:15:020
353546799361360,1cyclictest809563-21kworker/0:011:45:020
353546799361360,1cyclictest809563-21kworker/0:011:45:020
353546799361360,1cyclictest809563-21kworker/0:010:05:030
353546799361360,1cyclictest0-21swapper/011:00:020
353546799361360,1cyclictest0-21swapper/010:40:020
353546799361360,1cyclictest0-21swapper/010:15:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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