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2026-03-28 - 01:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Mar 27, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199862099380379,1cyclictest0-21swapper/708:05:027
1998620993800,1cyclictest0-21swapper/711:27:017
1998620993800,1cyclictest0-21swapper/711:27:017
199862099377376,1cyclictest0-21swapper/710:45:027
199862099377376,1cyclictest0-21swapper/709:37:027
199862099375373,1cyclictest0-21swapper/712:37:027
199862099372371,1cyclictest0-21swapper/708:17:017
199862099371369,1cyclictest0-21swapper/707:50:017
199862099370368,1cyclictest0-21swapper/712:09:027
199862099369368,1cyclictest0-21swapper/709:27:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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