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2026-06-04 - 21:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Jun 04, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186316499381380,1cyclictest1974965-21kworker/5:211:53:025
186316499381380,1cyclictest1974965-21kworker/5:210:43:025
186316499381380,1cyclictest1974965-21kworker/5:210:43:025
186316499381379,1cyclictest1974965-21kworker/5:212:38:035
186316499381379,1cyclictest1974965-21kworker/5:211:42:025
186316499381379,1cyclictest1974965-21kworker/5:210:26:015
186316499381379,1cyclictest1945190-21kworker/5:010:02:015
1863164993811,379cyclictest0-21swapper/511:04:025
1863164993810,380cyclictest0-21swapper/512:22:025
1863164993810,380cyclictest0-21swapper/510:23:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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