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2026-05-24 - 16:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun May 24, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2103097993800,379cyclictest0-21swapper/610:33:026
210094423790,18sleep70-21swapper/707:05:147
210309799370369,1cyclictest0-21swapper/611:05:026
210309799369368,1cyclictest0-21swapper/611:55:026
210309799369367,1cyclictest0-21swapper/611:15:026
210309799368367,1cyclictest0-21swapper/612:11:026
210309799368367,1cyclictest0-21swapper/611:00:026
210309799368367,1cyclictest0-21swapper/610:10:036
210309799368367,1cyclictest0-21swapper/610:05:026
210309799368367,1cyclictest0-21swapper/609:40:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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