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2026-04-01 - 23:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Apr 01, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3753649993810,380cyclictest0-21swapper/611:34:026
3753649993810,380cyclictest0-21swapper/610:54:016
3753649993810,380cyclictest0-21swapper/609:52:026
3753649993810,380cyclictest0-21swapper/608:36:026
3753649993810,380cyclictest0-21swapper/607:56:026
3753649993810,1cyclictest0-21swapper/607:49:016
375362999381380,1cyclictest3844725-21kworker/3:111:16:023
375362999381379,1cyclictest3784539-21kworker/3:009:37:023
3753629993810,380cyclictest0-21swapper/310:57:013
3753629993810,380cyclictest0-21swapper/308:56:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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