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2026-08-25 - 09:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Aug 25, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179562799381379,1cyclictest2100663-21kworker/4:221:24:024
179562799381379,1cyclictest1884717-21kworker/4:022:35:024
1795627993810,380cyclictest0-21swapper/422:48:024
1795601993810,380cyclictest0-21swapper/122:45:021
179562799380379,1cyclictest1884717-21kworker/4:023:09:024
179562799380379,1cyclictest1884717-21kworker/4:023:09:024
179562799380379,1cyclictest1884717-21kworker/4:022:55:024
179562799380379,1cyclictest1884717-21kworker/4:021:39:024
179562799380378,1cyclictest1884717-21kworker/4:022:54:024
179562799380378,1cyclictest0-21swapper/400:34:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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