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2025-12-13 - 19:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Dec 13, 2025 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
418410299382380,1cyclictest97550irq/166-enp0s3110:53:035
418410299380378,1cyclictest97550irq/166-enp0s3109:36:025
418410299378377,1cyclictest97550irq/166-enp0s3111:40:025
418410299378377,1cyclictest97550irq/166-enp0s3109:28:025
418410299378377,1cyclictest4141895-21kworker/5:107:40:035
418410299378376,1cyclictest97550irq/166-enp0s3112:08:025
418410299378376,1cyclictest97550irq/166-enp0s3110:00:025
418410299378376,1cyclictest97550irq/166-enp0s3109:45:025
418410299378376,1cyclictest97550irq/166-enp0s3108:40:025
418410299378376,1cyclictest97550irq/166-enp0s3107:26:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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