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2026-07-16 - 01:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jul 15, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
403799699376375,1cyclictest1371-21kworker/3:212:17:023
403799699376375,1cyclictest0-21swapper/312:09:023
403799699372370,1cyclictest1371-21kworker/3:211:45:023
403799699371370,1cyclictest1371-21kworker/3:211:36:023
403799699371370,1cyclictest0-21swapper/312:28:023
403799699371370,1cyclictest0-21swapper/312:02:023
403799699371370,1cyclictest0-21swapper/307:50:013
403799699368367,1cyclictest136707-21kworker/3:107:55:013
403797799368366,1cyclictest0-21swapper/108:59:021
403799699367366,1cyclictest1371-21kworker/3:212:35:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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