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2026-07-22 - 10:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jul 22, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226390699382379,2cyclictest2456915-21kworker/5:023:33:025
226389199382380,1cyclictest2276745-21kworker/3:120:28:023
226389199381379,1cyclictest2327895-21kworker/3:021:09:023
226387999381379,1cyclictest2254483-21kworker/2:020:55:032
226387999381379,1cyclictest2254483-21kworker/2:020:55:022
226390699380379,1cyclictest2456915-21kworker/5:023:27:025
2263906993800,380cyclictest2456915-21kworker/5:000:29:025
2263906993800,379cyclictest0-21swapper/522:10:025
226389199380378,1cyclictest2327895-21kworker/3:020:57:023
226389199380378,1cyclictest2327895-21kworker/3:020:57:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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