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2026-05-23 - 16:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat May 23, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175475799366364,1cyclictest1788670-21kworker/2:209:15:022
175475799357355,1cyclictest0-21swapper/209:01:022
175475799352351,1cyclictest1463083-21kworker/2:007:35:022
175475799352351,1cyclictest0-21swapper/209:05:022
175475799352350,1cyclictest0-21swapper/210:16:022
175475799351350,1cyclictest1788670-21kworker/2:212:20:022
175475799351350,1cyclictest1788670-21kworker/2:212:05:022
175475799351350,1cyclictest1788670-21kworker/2:208:10:012
175475799351350,1cyclictest0-21swapper/212:28:022
175475799351350,1cyclictest0-21swapper/211:35:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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