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2026-03-13 - 21:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Mar 13, 2026 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107793499364363,1cyclictest0-21swapper/207:10:012
107793499363361,1cyclictest0-21swapper/209:48:022
107793499362360,1cyclictest0-21swapper/211:09:032
107793499361360,1cyclictest0-21swapper/208:20:022
107793499361359,1cyclictest0-21swapper/212:10:022
107793499361359,1cyclictest0-21swapper/208:10:022
107793499360358,1cyclictest0-21swapper/208:05:022
107793499359358,1cyclictest0-21swapper/212:15:022
107793499359358,1cyclictest0-21swapper/211:30:032
107793499359358,1cyclictest0-21swapper/208:15:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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