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2026-02-23 - 08:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Feb 23, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264949599380379,1cyclictest2619587-21kworker/1:019:28:021
264949599380378,1cyclictest2619587-21kworker/1:020:21:021
264949599379378,1cyclictest2619587-21kworker/1:021:07:011
264949599379377,1cyclictest2619587-21kworker/1:021:02:021
264949599379377,1cyclictest2619587-21kworker/1:019:22:031
264949599379377,1cyclictest2619587-21kworker/1:019:22:021
264949599378377,1cyclictest2619587-21kworker/1:020:53:021
264949599378377,1cyclictest2619587-21kworker/1:020:33:021
264949599378376,1cyclictest2619587-21kworker/1:019:51:021
264953399325322,2cyclictest2671409-21kworker/6:121:49:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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