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2026-03-31 - 21:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 31, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3386473993810,380cyclictest0-21swapper/112:26:021
3386473993810,380cyclictest0-21swapper/112:13:031
3386473993810,380cyclictest0-21swapper/109:06:021
3386473993800,379cyclictest0-21swapper/107:19:021
3386473993800,1cyclictest0-21swapper/111:41:031
3386473993800,1cyclictest0-21swapper/110:53:021
338646699322321,1cyclictest3396288-21kworker/0:107:28:020
338646699321320,1cyclictest0-21swapper/008:55:020
338646699321320,1cyclictest0-21swapper/008:12:020
338646699320319,1cyclictest3417405-21kworker/0:010:35:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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