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2026-03-12 - 04:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Mar 12, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44736199382380,1cyclictest417479-21kworker/3:220:43:033
447361993811,1cyclictest0-21swapper/320:47:033
44736199380379,1cyclictest417479-21kworker/3:220:25:023
44736199380378,1cyclictest417479-21kworker/3:221:09:023
44736199380378,1cyclictest417479-21kworker/3:221:04:023
44736199380378,1cyclictest417479-21kworker/3:220:00:033
44736199380378,1cyclictest417479-21kworker/3:219:37:033
447361993800,1cyclictest0-21swapper/320:24:023
44736199379378,1cyclictest417479-21kworker/3:220:39:033
44736199379378,1cyclictest417479-21kworker/3:219:48:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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