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2026-02-25 - 07:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Feb 25, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
338572299381380,1cyclictest3548687-21kworker/7:022:33:027
338572299381380,1cyclictest3486721-21kworker/7:021:46:027
338569499381379,1cyclictest0-21swapper/319:57:023
3385685993810,380cyclictest0-21swapper/223:57:022
3385685993810,380cyclictest0-21swapper/221:29:012
3385685993810,380cyclictest0-21swapper/200:02:022
338572299380379,1cyclictest3548687-21kworker/7:023:02:027
338572299380379,1cyclictest3548687-21kworker/7:022:41:027
338572299380379,1cyclictest3531980-21kworker/7:222:16:027
338572299380379,1cyclictest3506784-21kworker/7:122:11:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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