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2026-02-06 - 09:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Feb 05, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13635499367366,1cyclictest0-21swapper/023:17:020
13638799358356,1cyclictest348883-21kworker/4:123:17:014
13635499357355,1cyclictest0-21swapper/023:24:020
13635499356355,1cyclictest348616-21kworker/0:323:50:020
13635499356355,1cyclictest200368-21kworker/0:221:20:020
13635499355353,1cyclictest200368-21kworker/0:222:27:010
13635499354353,1cyclictest348616-21kworker/0:323:41:010
13635499354351,2cyclictest348616-21kworker/0:300:12:010
13635499354351,2cyclictest200368-21kworker/0:221:56:020
13635499353352,1cyclictest437019-21kworker/0:000:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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