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2025-12-29 - 02:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Dec 28, 2025 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218733024000,3sleep00-21swapper/007:05:170
218926999382380,1cyclictest2189125-21kworker/6:007:37:026
218925599381379,1cyclictest2253245-21kworker/4:212:37:024
218925599381379,1cyclictest2253245-21kworker/4:210:42:024
218925599381379,1cyclictest2163192-21kworker/4:007:35:024
218925599380378,1cyclictest2253245-21kworker/4:212:29:024
218925599380378,1cyclictest2253245-21kworker/4:212:23:024
218925599380377,2cyclictest2163192-21kworker/4:008:41:024
2189255993800,1cyclictest0-21swapper/408:45:024
218925599379378,1cyclictest0-21swapper/411:21:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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