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2026-04-18 - 18:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Apr 18, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159704823940,3sleep00-21swapper/007:05:280
159783199367365,1cyclictest0-21swapper/107:19:011
159787399348345,2cyclictest97550irq/166-enp0s3111:55:026
159787399347345,1cyclictest97550irq/166-enp0s3111:13:036
159787399346344,1cyclictest97550irq/166-enp0s3110:15:026
159787399346344,1cyclictest97550irq/166-enp0s3108:21:026
159787399346343,3cyclictest1652822-21kworker/6:008:43:026
159787399345343,1cyclictest97550irq/166-enp0s3110:01:026
159787399345343,1cyclictest97550irq/166-enp0s3110:01:026
159787399345343,1cyclictest97550irq/166-enp0s3109:17:036
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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