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2026-07-06 - 13:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Jul 06, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53021599381380,1cyclictest621266-21kworker/2:122:16:022
53021599381378,2cyclictest579183-21kworker/2:020:56:022
530215993810,380cyclictest0-21swapper/223:53:032
530215993810,380cyclictest0-21swapper/221:16:032
530215993810,380cyclictest0-21swapper/200:25:032
53021599380379,1cyclictest503722-21kworker/2:120:30:032
530215993800,379cyclictest0-21swapper/219:21:032
530215993800,1cyclictest0-21swapper/222:48:032
530215993800,1cyclictest0-21swapper/221:46:022
530215993800,1cyclictest0-21swapper/200:32:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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