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2026-08-13 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Aug 12, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1574899993840,381cyclictest1699003-21systemd-userwor10:35:020
157489999381379,1cyclictest1756229-21kworker/0:012:15:020
157489999380379,1cyclictest1844806-21kworker/0:007:24:020
157489999380379,1cyclictest1756229-21kworker/0:012:10:030
157489999380379,1cyclictest1605809-21kworker/0:109:45:020
157489999380379,1cyclictest1605809-21kworker/0:108:25:020
157489999380378,1cyclictest1844806-21kworker/0:007:35:020
157489999380378,1cyclictest1605809-21kworker/0:110:47:020
157489999380378,1cyclictest1605809-21kworker/0:108:45:020
1574899993800,379cyclictest0-21swapper/009:05:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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