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2026-08-08 - 19:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Aug 08, 2026 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11683599381379,1cyclictest180808-21kworker/4:010:56:034
11683599381379,1cyclictest180808-21kworker/4:009:36:024
116835993810,380cyclictest0-21swapper/410:42:024
11683599380379,1cyclictest180808-21kworker/4:010:36:024
11683599380379,1cyclictest135399-21kworker/4:108:17:034
11683599380378,1cyclictest180808-21kworker/4:009:54:024
11683599380378,1cyclictest180808-21kworker/4:009:32:024
11683599380378,1cyclictest135399-21kworker/4:107:52:034
116835993800,379cyclictest0-21swapper/410:15:024
116835993800,379cyclictest0-21swapper/409:45:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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