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2026-06-29 - 08:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Jun 29, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223999499393392,1cyclictest2519163-21kworker/2:200:12:022
223997899367366,1cyclictest2396110-21kworker/0:223:01:020
223997899367366,1cyclictest2396110-21kworker/0:223:01:020
223997899367366,1cyclictest0-21swapper/023:55:020
223997899366365,1cyclictest0-21swapper/021:40:020
223997899366365,1cyclictest0-21swapper/021:21:020
223997899366364,1cyclictest2396110-21kworker/0:200:13:010
223997899366364,1cyclictest0-21swapper/021:31:020
223997899365364,1cyclictest2310011-21kworker/0:022:08:020
223997899365364,1cyclictest0-21swapper/021:27:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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