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2026-08-23 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Aug 23, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
101651999382380,1cyclictest1077466-21kworker/7:120:57:027
101651999382380,1cyclictest1029332-21kworker/7:120:17:027
101651999382380,1cyclictest1029332-21kworker/7:119:35:027
101649199382380,1cyclictest0-21swapper/320:57:023
101651999381379,1cyclictest1029332-21kworker/7:120:01:027
101651999381378,2cyclictest1077466-21kworker/7:100:33:027
101651999380378,1cyclictest1065063-21kworker/7:020:51:017
101651999380378,1cyclictest1029332-21kworker/7:119:47:027
101651999380378,1cyclictest1029332-21kworker/7:119:47:027
101649199380378,1cyclictest0-21swapper/300:33:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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