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2026-08-28 - 10:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Aug 28, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2859327993840,381cyclictest3153517-21systemd-userwor00:11:023
2859319993810,380cyclictest0-21swapper/200:38:022
285931999380379,1cyclictest3154989-21kworker/2:220:48:032
285931999380379,1cyclictest3154989-21kworker/2:220:35:022
285931999380379,1cyclictest3060262-21kworker/2:000:24:022
2859319993800,379cyclictest0-21swapper/223:20:022
2859319993800,379cyclictest0-21swapper/221:32:022
2859319993800,379cyclictest0-21swapper/219:45:022
2859319993800,1cyclictest0-21swapper/222:29:022
2859319993800,1cyclictest0-21swapper/221:16:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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