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2026-05-28 - 03:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu May 28, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327637899382381,1cyclictest3270166-21kworker/7:220:40:017
327634199382380,1cyclictest3532050-21kworker/2:021:03:022
327633499382379,2cyclictest3541427-21kworker/1:122:03:011
327637899381380,1cyclictest3372432-21kworker/7:222:41:017
327637899381380,1cyclictest3372432-21kworker/7:221:44:017
327637899381380,1cyclictest0-21swapper/723:28:027
327634199381380,1cyclictest3532050-21kworker/2:021:53:012
327634199381379,1cyclictest3532050-21kworker/2:019:51:022
327634199381379,1cyclictest3532050-21kworker/2:019:16:022
3276341993810,381cyclictest0-21swapper/223:02:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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