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2026-04-06 - 02:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Apr 05, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100061424130,23sleep70-21swapper/707:05:197
100203599382380,1cyclictest1075030-21kworker/7:111:17:027
100203599382380,1cyclictest1075030-21kworker/7:110:38:027
100203599382379,2cyclictest1075030-21kworker/7:112:14:027
100203599381379,1cyclictest2773686-21kworker/7:007:37:027
100203599381379,1cyclictest1075030-21kworker/7:109:52:027
100201399381380,1cyclictest1165258-21kworker/4:011:42:024
100201399381380,1cyclictest1044936-21kworker/4:108:49:024
100201399381380,1cyclictest1044936-21kworker/4:108:49:024
100201399381379,1cyclictest1186338-21kworker/4:212:36:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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