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2026-02-21 - 19:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Feb 21, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217049499331330,1cyclictest0-21swapper/112:35:011
217049499329327,1cyclictest2174647-21cstates07:15:021
217049499328326,1cyclictest0-21swapper/107:43:021
217049499327326,1cyclictest0-21swapper/109:49:021
217049499327326,1cyclictest0-21swapper/108:11:021
217049499326325,1cyclictest0-21swapper/111:59:021
217049499326325,1cyclictest0-21swapper/111:21:021
217049499326325,1cyclictest0-21swapper/111:21:011
217049499326325,1cyclictest0-21swapper/110:33:021
217049499326325,1cyclictest0-21swapper/109:13:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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