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2026-01-16 - 16:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jan 16, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126646599381380,1cyclictest1257288-21kworker/6:007:39:026
126646599381380,1cyclictest1257288-21kworker/6:007:39:026
126646599381380,1cyclictest1257288-21kworker/6:007:31:026
1266465993810,380cyclictest0-21swapper/612:19:026
1266465993810,380cyclictest0-21swapper/611:12:026
1266465993810,380cyclictest0-21swapper/610:56:026
1266465993810,380cyclictest0-21swapper/609:17:026
1266465993810,380cyclictest0-21swapper/607:44:016
1266465993810,1cyclictest0-21swapper/609:59:026
126646599380379,1cyclictest1351522-21kworker/6:010:42:016
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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