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2026-03-18 - 01:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 17, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250845999369368,1cyclictest0-21swapper/108:39:021
250845999364363,1cyclictest0-21swapper/111:46:021
250845999364363,1cyclictest0-21swapper/111:25:021
250845999364363,1cyclictest0-21swapper/109:08:021
250845999363362,1cyclictest2659729-21kworker/1:212:20:021
250845999363362,1cyclictest2659729-21kworker/1:211:55:021
250845999363362,1cyclictest0-21swapper/112:38:021
250845999363362,1cyclictest0-21swapper/112:33:021
250845999363362,1cyclictest0-21swapper/111:30:021
250845999363362,1cyclictest0-21swapper/109:46:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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