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2026-02-17 - 17:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Feb 17, 2026 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70095899380379,1cyclictest731852-21kworker/2:208:16:022
70099499364360,2cyclictest746811-21kworker/7:309:01:017
70099499361359,1cyclictest0-21swapper/707:25:027
70099499359358,1cyclictest0-21swapper/707:52:027
70099499359357,1cyclictest797870-21kworker/7:110:01:027
70099499358357,1cyclictest0-21swapper/708:25:017
70099499358356,1cyclictest0-21swapper/708:34:027
70099499357356,1cyclictest858227-21kworker/7:212:05:017
70099499357356,1cyclictest746811-21kworker/7:308:40:027
70099499357356,1cyclictest662958-21kworker/7:008:00:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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