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2026-05-12 - 04:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue May 12, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157916199380379,1cyclictest3041704-21kworker/0:119:54:020
157916199380379,1cyclictest3041704-21kworker/0:119:33:020
1579161993800,379cyclictest0-21swapper/020:08:010
1579161993800,1cyclictest0-21swapper/021:05:020
157916199379378,1cyclictest3041704-21kworker/0:119:29:020
157916199379377,1cyclictest3041704-21kworker/0:120:31:020
157916199378377,1cyclictest3041704-21kworker/0:119:43:020
157916199378377,1cyclictest0-21swapper/020:39:020
157916199378376,1cyclictest0-21swapper/019:24:020
157917199356355,1cyclictest0-21swapper/100:02:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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