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2026-08-12 - 00:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Aug 11, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120883599383380,2cyclictest1245779-21kworker/0:209:49:020
1208835993820,381cyclictest0-21swapper/010:50:020
120883599381380,1cyclictest1245779-21kworker/0:212:38:010
120883599381380,1cyclictest1245779-21kworker/0:212:28:020
120883599381380,1cyclictest1245779-21kworker/0:210:07:010
120883599381379,1cyclictest1245779-21kworker/0:211:13:020
120883599381379,1cyclictest1245779-21kworker/0:209:28:020
120883599380379,1cyclictest1245779-21kworker/0:211:44:020
120883599380379,1cyclictest1245779-21kworker/0:209:51:020
120883599380379,1cyclictest1245779-21kworker/0:209:51:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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