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2026-07-25 - 09:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Jul 25, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
336738999357356,1cyclictest3480254-21kworker/u16:121:47:024
336738999357355,1cyclictest0-21swapper/421:57:014
336738999357355,1cyclictest0-21swapper/421:57:014
336738999353351,1cyclictest2380126-21kworker/4:122:22:274
336738999352351,1cyclictest2380126-21kworker/4:122:54:014
336738999352351,1cyclictest2380126-21kworker/4:100:10:024
336738999352351,1cyclictest0-21swapper/423:44:024
336738999352351,1cyclictest0-21swapper/421:50:024
336738999352350,1cyclictest2380126-21kworker/4:121:16:014
336738999351350,1cyclictest2380126-21kworker/4:123:48:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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