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2026-04-29 - 03:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Apr 29, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114043199378377,1cyclictest1170712-21kworker/3:221:58:023
114043199371369,1cyclictest1439381-21rm00:13:023
114043199370368,1cyclictest0-21swapper/322:49:023
114043199369368,1cyclictest1170712-21kworker/3:222:14:023
114043199367365,1cyclictest1170712-21kworker/3:200:00:023
114043199367365,1cyclictest0-21swapper/321:35:023
114043199367365,1cyclictest0-21swapper/321:16:023
114043199367364,2cyclictest0-21swapper/323:51:023
114043199366365,1cyclictest0-21swapper/323:02:023
114043199366365,1cyclictest0-21swapper/322:55:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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