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2026-01-13 - 16:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Jan 13, 2026 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110092993830,2cyclictest301670-21systemd-userwor12:36:021
110092993830,2cyclictest301670-21systemd-userwor12:36:021
110125993820,382cyclictest226548-21kworker/5:010:59:015
110125993820,381cyclictest74667-21kworker/5:008:59:025
11009299382380,1cyclictest271470-21kworker/1:011:51:011
11012599381379,1cyclictest0-21swapper/508:12:025
110125993810,381cyclictest74667-21kworker/5:008:45:025
11010499381379,1cyclictest150766-21kworker/2:210:49:012
110104993810,380cyclictest0-21swapper/211:19:022
110104993810,1cyclictest0-21swapper/210:36:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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