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2026-09-02 - 13:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Sep 02, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48285199381380,1cyclictest552843-21kworker/6:121:41:016
48282499381379,1cyclictest1456221-21kworker/2:220:13:022
48282499381378,2cyclictest633212-21kworker/2:122:23:022
48282499380378,1cyclictest633212-21kworker/2:123:45:012
482824993800,379cyclictest0-21swapper/200:37:012
48281399380379,1cyclictest714699-21kworker/1:123:43:011
48281399380378,1cyclictest97550irq/166-enp0s3123:55:011
48281399380378,1cyclictest97550irq/166-enp0s3122:17:011
48282499379378,1cyclictest1456221-21kworker/2:220:59:012
48282499379378,1cyclictest0-21swapper/220:29:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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