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2026-05-30 - 18:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat May 30, 2026 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
418874199376374,1cyclictest254045-21kworker/0:010:24:020
418874199376374,1cyclictest254045-21kworker/0:010:24:020
418874199365364,1cyclictest0-21swapper/012:15:020
418874199357355,1cyclictest0-21swapper/008:20:020
418874199356355,1cyclictest0-21swapper/010:25:030
418874199356354,1cyclictest254045-21kworker/0:007:15:020
418874199356354,1cyclictest0-21swapper/009:45:020
418877999355354,1cyclictest0-21swapper/511:25:025
418877999355354,1cyclictest0-21swapper/508:08:025
418874199355354,1cyclictest0-21swapper/010:55:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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