You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-19 - 21:49
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Mar 19, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325375899381379,1cyclictest3350831-21kworker/0:311:22:010
325375899381379,1cyclictest2265902-21kworker/0:107:14:010
3253758993811,380cyclictest0-21swapper/010:43:010
3253758993810,380cyclictest0-21swapper/007:28:010
3253758993800,380cyclictest0-21swapper/008:59:020
3253758993800,1cyclictest0-21swapper/012:12:030
325375899379378,1cyclictest3350831-21kworker/0:312:22:030
325375899379378,1cyclictest3350831-21kworker/0:311:19:010
325375899379378,1cyclictest3296342-21kworker/0:009:46:010
325375899379378,1cyclictest3296342-21kworker/0:009:36:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional