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2025-12-30 - 16:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Dec 30, 2025 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300604199381379,1cyclictest3270578-21kworker/1:210:06:021
300604199381379,1cyclictest3270578-21kworker/1:210:02:021
300604199381379,1cyclictest3073064-21kworker/1:009:29:021
300603399381378,2cyclictest0-21swapper/008:20:020
3006033993811,1cyclictest0-21swapper/008:46:010
3006033993811,1cyclictest0-21swapper/008:46:010
300604199380379,1cyclictest3270578-21kworker/1:207:34:021
3006041993800,380cyclictest0-21swapper/107:13:011
3006041993800,379cyclictest0-21swapper/108:28:021
3006033993800,1cyclictest0-21swapper/010:43:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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