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2026-02-15 - 08:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Feb 15, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
388214499375374,1cyclictest1161878-21kworker/5:219:55:025
388214499371370,1cyclictest97550irq/166-enp0s3121:57:025
388214499371369,1cyclictest97550irq/166-enp0s3121:47:025
388214499371369,1cyclictest97550irq/166-enp0s3100:37:025
388214499370369,1cyclictest97550irq/166-enp0s3122:35:035
388214499370369,1cyclictest97550irq/166-enp0s3121:21:035
388214499370368,2cyclictest1161878-21kworker/5:219:37:025
388214499370368,2cyclictest1161878-21kworker/5:219:37:025
388214499370368,1cyclictest97550irq/166-enp0s3122:53:025
388214499370368,1cyclictest97550irq/166-enp0s3100:17:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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