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2026-08-18 - 03:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Aug 18, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345963099381379,2cyclictest3472495-21kworker/1:019:43:021
345963099380379,1cyclictest237620-21kworker/1:119:26:021
345963099380378,1cyclictest0-21swapper/120:13:021
3459630993800,379cyclictest0-21swapper/100:20:011
3459630993800,1cyclictest0-21swapper/123:40:021
3459630993800,1cyclictest0-21swapper/120:35:021
345963099379378,1cyclictest3499598-21kworker/1:120:54:021
345963099379378,1cyclictest3499598-21kworker/1:120:48:021
345963099379378,1cyclictest3484521-21kworker/1:219:58:011
345963099379378,1cyclictest0-21swapper/120:33:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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