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2026-03-01 - 16:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Mar 01, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85075799378375,2cyclictest0-21swapper/007:37:020
85081199375373,1cyclictest820598-21kworker/7:011:08:027
85075799374372,1cyclictest0-21swapper/008:15:010
85075799373371,1cyclictest555235-21kworker/0:110:35:020
85075799372370,1cyclictest0-21swapper/011:25:020
85075799371369,1cyclictest0-21swapper/011:41:020
85075799370368,1cyclictest0-21swapper/008:25:020
85075799369367,1cyclictest555235-21kworker/0:112:01:020
85075799367365,1cyclictest555235-21kworker/0:110:33:020
85075799367365,1cyclictest555235-21kworker/0:108:59:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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