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2026-03-09 - 18:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 09, 2026 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3782097993841,2cyclictest0-21swapper/311:56:023
3782076993820,380cyclictest0-21swapper/007:21:020
378209799381380,1cyclictest3772952-21kworker/3:208:55:023
378209799381379,1cyclictest3772952-21kworker/3:211:50:023
378209799381379,1cyclictest3772952-21kworker/3:207:20:023
378208299381380,1cyclictest3942325-21kworker/1:212:16:021
378208299381380,1cyclictest3858130-21kworker/1:009:42:021
378208299381379,1cyclictest3806990-21kworker/1:109:01:011
378208299381379,1cyclictest3806990-21kworker/1:108:48:021
378208299381379,1cyclictest3806990-21kworker/1:108:14:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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