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2026-04-12 - 17:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Apr 12, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
356790999379378,1cyclictest3577637-21kworker/5:007:25:025
356790999378377,1cyclictest3577637-21kworker/5:011:35:025
356790999378377,1cyclictest3577637-21kworker/5:010:30:025
356790999378377,1cyclictest3577637-21kworker/5:008:25:025
356790999377376,1cyclictest3577637-21kworker/5:010:10:025
356790999377376,1cyclictest3577637-21kworker/5:009:15:025
356790999377376,1cyclictest3577637-21kworker/5:008:40:025
356790999377376,1cyclictest0-21swapper/510:15:025
356790999376375,1cyclictest3577637-21kworker/5:011:07:015
356790999376375,1cyclictest3577637-21kworker/5:010:39:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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