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2026-05-22 - 15:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri May 22, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
111499499381380,1cyclictest1310066-21kworker/2:123:05:022
111499499381380,1cyclictest0-21swapper/219:40:012
111499499381379,1cyclictest1117935-21kworker/2:221:00:022
1114994993811,379cyclictest0-21swapper/222:59:012
1114994993810,380cyclictest0-21swapper/222:40:022
1114994993810,380cyclictest0-21swapper/222:27:022
1114994993810,380cyclictest0-21swapper/222:07:012
111499499380379,1cyclictest1399535-21kworker/2:019:20:022
111499499380379,1cyclictest1399535-21kworker/2:019:20:012
111499499380379,1cyclictest1117935-21kworker/2:220:50:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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