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2026-08-07 - 19:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Aug 07, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
387121399380379,1cyclictest3908116-21kworker/5:211:25:015
387121399380379,1cyclictest3908116-21kworker/5:210:55:025
387121399380379,1cyclictest3908116-21kworker/5:209:50:025
387121399380378,1cyclictest0-21swapper/511:20:025
387121399380378,1cyclictest0-21swapper/509:25:025
387121399380378,1cyclictest0-21swapper/509:12:025
387121399380378,1cyclictest0-21swapper/507:48:025
3871213993800,1cyclictest0-21swapper/512:06:025
387121399379378,1cyclictest3908116-21kworker/5:212:14:025
387121399379378,1cyclictest3908116-21kworker/5:211:40:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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