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2025-09-16 - 04:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Sep 16, 2025 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4003186993800,379cyclictest0-21swapper/122:30:021
400318699374373,1cyclictest0-21swapper/122:20:021
400317799374371,1cyclictest4013216-21kworker/0:221:27:020
400318699370368,1cyclictest0-21swapper/123:49:011
400318699369368,1cyclictest0-21swapper/121:23:021
400317799368367,1cyclictest0-21swapper/021:55:020
400318699366365,1cyclictest4075647-21kworker/1:121:43:021
400320699362361,1cyclictest0-21swapper/400:05:024
400318699362361,1cyclictest4075647-21kworker/1:122:15:021
400317799362360,1cyclictest0-21swapper/021:15:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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