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2026-07-03 - 10:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jul 03, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3658001993832,380cyclictest0-21swapper/522:24:025
365798599380377,2cyclictest0-21swapper/322:24:023
365800799370369,1cyclictest0-21swapper/622:03:026
365800799368366,1cyclictest0-21swapper/619:55:026
365800799366365,1cyclictest0-21swapper/620:41:026
365796699366364,1cyclictest0-21swapper/120:17:021
365800799363361,1cyclictest3958710-21kworker/6:000:39:026
365800799363361,1cyclictest3796464-21kworker/6:122:47:026
365800799362361,1cyclictest0-21swapper/623:01:026
365800799361360,1cyclictest0-21swapper/623:47:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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