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2026-06-14 - 01:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Jun 13, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
921504993800,379cyclictest0-21swapper/011:02:020
921504993800,379cyclictest0-21swapper/010:32:020
921504993800,379cyclictest0-21swapper/010:04:030
921504993800,1cyclictest0-21swapper/012:27:020
921504993800,1cyclictest0-21swapper/009:24:020
921504993800,1cyclictest0-21swapper/009:06:020
921504993800,1cyclictest0-21swapper/008:22:030
92152299368367,1cyclictest0-21swapper/212:15:022
92152299367366,1cyclictest0-21swapper/210:50:032
92152299367365,1cyclictest961467-21kworker/2:109:25:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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