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2026-08-29 - 10:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Aug 29, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322042499378377,1cyclictest3372569-21kworker/5:023:03:025
322043299359356,1cyclictest3254324-21kworker/6:020:11:026
322043999356354,1cyclictest3401509-21kworker/7:023:01:027
322040099344341,1cyclictest0-21swapper/220:11:022
322043999329328,1cyclictest3447983-21kworker/7:223:32:027
322043999318317,1cyclictest3263341-21kworker/7:021:07:017
322040899317315,1cyclictest0-21swapper/323:01:013
322039399317315,1cyclictest3293404-21diskmemload23:01:021
322043999308306,1cyclictest0-21swapper/723:19:017
322043999302300,1cyclictest0-21swapper/723:55:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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