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2026-03-30 - 05:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 30, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2775558993810,380cyclictest0-21swapper/222:35:022
2775558993810,380cyclictest0-21swapper/220:10:032
2775558993810,380cyclictest0-21swapper/200:30:022
2775558993810,380cyclictest0-21swapper/200:30:022
277555899380379,1cyclictest2746152-21kworker/2:119:20:022
277555899380378,1cyclictest2824535-21kworker/2:020:54:022
277555899380378,1cyclictest2791322-21kworker/2:219:53:022
2775558993800,379cyclictest0-21swapper/220:40:022
2775558993800,379cyclictest0-21swapper/220:01:022
2775558993800,379cyclictest0-21swapper/219:55:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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