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2026-05-21 - 02:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed May 20, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
52858225130,5sleep2271rcuc/207:05:152
53001523950,3sleep763-21ksoftirqd/707:05:297
53059199379376,1cyclictest498954-21kworker/7:110:24:027
53053899365364,1cyclictest0-21swapper/011:28:020
53057999356355,1cyclictest0-21swapper/512:00:025
53057999355354,1cyclictest0-21swapper/510:37:025
53057999354353,1cyclictest0-21swapper/509:01:025
53057999354352,1cyclictest0-21swapper/511:50:025
53057999353352,1cyclictest0-21swapper/508:15:015
53057999353351,1cyclictest0-21swapper/509:29:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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