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2026-01-27 - 20:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Jan 27, 2026 12:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1165798993810,380cyclictest0-21swapper/409:24:024
1165798993810,380cyclictest0-21swapper/407:30:024
116579899380379,1cyclictest1403931-21kworker/4:308:27:024
116579899380379,1cyclictest1314025-21kworker/4:112:28:024
116579899380379,1cyclictest1314025-21kworker/4:112:28:024
116579899380379,1cyclictest1268907-21kworker/4:010:11:034
116579899380379,1cyclictest1247683-21kworker/4:209:52:024
116579899380378,1cyclictest1314025-21kworker/4:112:06:024
1165798993800,379cyclictest0-21swapper/411:06:024
1165798993800,379cyclictest0-21swapper/410:30:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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