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2026-03-03 - 06:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 03, 2026 00:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133155499382380,1cyclictest1572318-21kworker/0:219:44:020
133155499382380,1cyclictest1572318-21kworker/0:219:44:020
1331592993810,380cyclictest1512894-21kworker/5:023:05:025
1331592993810,380cyclictest1380366-21kworker/5:221:45:025
133159299379376,2cyclictest1380366-21kworker/5:221:35:025
133159299377375,1cyclictest0-21swapper/500:32:025
133159299376374,1cyclictest0-21swapper/521:18:025
133159299376373,2cyclictest1302101-21kworker/5:119:19:025
133159299374372,1cyclictest1548784-21kworker/5:223:41:025
133159299373372,1cyclictest1380366-21kworker/5:221:29:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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