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2025-12-24 - 11:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Dec 24, 2025 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25702299382380,1cyclictest4157987-21kworker/4:123:21:024
25702299382380,1cyclictest4157987-21kworker/4:122:43:024
257040993811,379cyclictest0-21swapper/719:36:027
257040993810,380cyclictest0-21swapper/721:07:027
257040993810,380cyclictest0-21swapper/719:48:027
257040993810,380cyclictest0-21swapper/719:17:027
25702299381379,1cyclictest4157987-21kworker/4:121:57:024
25702299381379,1cyclictest4157987-21kworker/4:120:25:024
25702299381379,1cyclictest4157987-21kworker/4:119:55:024
257022993811,379cyclictest0-21swapper/422:12:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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