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2025-12-10 - 07:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Dec 10, 2025 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
340057621720,6sleep335-21ksoftirqd/319:05:193
340173129981,4sleep10-21swapper/119:05:351
3402273999833,35cyclictest0-21swapper/520:03:155
3402279999726,41cyclictest56-21ksoftirqd/620:58:156
340225899908,50cyclictest35-21ksoftirqd/322:23:153
3402258999017,38cyclictest0-21swapper/319:18:153
34623402890,0sleep10-21swapper/120:45:001
340184728846,13sleep50-21swapper/519:07:085
3402279998711,48cyclictest56-21ksoftirqd/621:23:146
3402258998717,36cyclictest0-21swapper/323:18:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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