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2026-03-21 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Mar 21, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
382157999377376,1cyclictest3885572-21kworker/5:122:06:025
382156199368366,2cyclictest4071732-21kworker/3:300:24:023
382156199368366,1cyclictest3915586-21kworker/3:221:45:013
382157999364363,1cyclictest427764-21kworker/5:220:21:025
382156199364362,1cyclictest0-21swapper/322:44:023
382156199362361,1cyclictest0-21swapper/323:48:023
382156199362360,1cyclictest0-21swapper/323:26:023
382156199361360,1cyclictest4137555-21kworker/3:100:36:013
382156199361360,1cyclictest3995361-21kworker/3:022:51:023
382156199361360,1cyclictest3915586-21kworker/3:222:38:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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