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2026-08-20 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Aug 20, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
418275799382380,1cyclictest97550irq/166-enp0s3121:17:021
418275799382380,1cyclictest97550irq/166-enp0s3119:25:011
418275799381379,1cyclictest97550irq/166-enp0s3121:53:011
418275799381379,1cyclictest97550irq/166-enp0s3120:45:011
418275799381379,1cyclictest97550irq/166-enp0s3120:25:011
418275799381379,1cyclictest97550irq/166-enp0s3100:11:021
418275799380379,1cyclictest7907-21kworker/1:021:36:011
418275799380378,1cyclictest97550irq/166-enp0s3120:41:011
418275799380378,1cyclictest97550irq/166-enp0s3119:19:021
418275799379377,1cyclictest97550irq/166-enp0s3120:37:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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