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2026-05-18 - 02:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun May 17, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
362013099370369,1cyclictest0-21swapper/512:23:025
362011699346344,1cyclictest0-21swapper/308:30:023
362011699345343,1cyclictest3720206-21kworker/3:211:15:023
362011699345343,1cyclictest3720206-21kworker/3:210:37:023
362011699345343,1cyclictest0-21swapper/310:32:023
362009799345343,1cyclictest3616967-21kworker/1:112:23:021
362011699344343,1cyclictest0-21swapper/310:15:023
362011699344342,1cyclictest0-21swapper/309:35:033
362011699343342,1cyclictest3720206-21kworker/3:212:20:023
362011699343342,1cyclictest0-21swapper/311:35:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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