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2026-09-17 - 07:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Sep 16, 2026 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
155084099381379,1cyclictest1842091-21kworker/4:209:24:014
155084099381379,1cyclictest1842091-21kworker/4:209:06:024
155084099381379,1cyclictest1842091-21kworker/4:208:57:024
155084099380379,1cyclictest1842091-21kworker/4:208:46:024
155084099380379,1cyclictest1684003-21kworker/4:011:32:024
155084099380379,1cyclictest1638902-21kworker/4:109:48:024
155084099380378,1cyclictest1842091-21kworker/4:208:32:024
155084099379378,1cyclictest1842091-21kworker/4:207:56:024
155084099379377,1cyclictest1842091-21kworker/4:208:51:014
155085599378377,1cyclictest0-21swapper/607:31:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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