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2026-07-30 - 12:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Jul 30, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
98041699389385,3cyclictest1026389-21kworker/0:221:13:020
98047299384382,1cyclictest0-21swapper/722:21:027
98047299383382,1cyclictest0-21swapper/721:41:027
98041699381380,1cyclictest1061455-21kworker/0:323:33:020
98041699381379,1cyclictest0-21swapper/021:17:020
98041699381379,1cyclictest0-21swapper/021:17:020
98047299379378,1cyclictest0-21swapper/719:57:027
98041699379378,1cyclictest1061455-21kworker/0:323:39:020
98041699379378,1cyclictest0-21swapper/022:43:020
98041699379378,1cyclictest0-21swapper/022:43:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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