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2026-02-08 - 02:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Feb 07, 2026 12:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1112758993820,381cyclictest0-21swapper/209:54:022
111278299326325,1cyclictest97550irq/166-enp0s3108:35:025
111278299326324,1cyclictest97550irq/166-enp0s3111:45:015
111278299326324,1cyclictest97550irq/166-enp0s3107:47:025
111278299325324,1cyclictest97550irq/166-enp0s3111:05:025
111278299325324,1cyclictest97550irq/166-enp0s3109:41:025
111278299325324,1cyclictest97550irq/166-enp0s3107:43:025
111278299324323,1cyclictest1119608-21kworker/5:207:23:025
111278299324323,1cyclictest1106592-21kworker/5:108:03:025
111278299324322,1cyclictest97550irq/166-enp0s3110:03:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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