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2026-09-19 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Sep 19, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
237569099381379,1cyclictest2595710-21kworker/3:023:25:023
237570399380378,1cyclictest2472286-21kworker/5:123:23:025
237569099380379,1cyclictest2495662-21kworker/3:022:04:023
2375690993800,379cyclictest0-21swapper/300:35:023
237570399379377,1cyclictest2472286-21kworker/5:122:05:035
237569099379377,1cyclictest2605727-21kworker/3:100:29:033
237569099379377,1cyclictest2605727-21kworker/3:100:29:033
237569099379377,1cyclictest2546364-21kworker/3:322:53:023
237570399378376,1cyclictest0-21swapper/523:47:025
237569099378376,1cyclictest0-21swapper/321:29:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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