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2026-03-02 - 04:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 02, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96168899367365,1cyclictest0-21swapper/100:08:021
96168099344342,1cyclictest0-21swapper/000:19:010
96172199339338,1cyclictest1151847-21kworker/5:023:07:015
96172199337336,1cyclictest989604-21kworker/5:122:45:015
96172199337336,1cyclictest1151847-21kworker/5:022:51:015
96172199337335,1cyclictest1252821-21kworker/5:200:39:025
96172199336334,1cyclictest1151847-21kworker/5:022:55:015
96172199335333,1cyclictest1098544-21kworker/5:022:05:015
96172199334333,1cyclictest989604-21kworker/5:121:11:025
96172199334333,1cyclictest1151847-21kworker/5:023:45:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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