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2026-02-07 - 09:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Feb 07, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
86281799380378,1cyclictest0-21swapper/619:10:036
86281799379378,1cyclictest0-21swapper/622:58:036
86281799378376,1cyclictest0-21swapper/600:34:026
86279599378376,1cyclictest1064684-21kworker/3:023:38:023
86281799377376,1cyclictest0-21swapper/623:09:026
86281799377376,1cyclictest0-21swapper/622:51:026
86281799377376,1cyclictest0-21swapper/621:51:026
86281799377376,1cyclictest0-21swapper/621:26:026
86281799377376,1cyclictest0-21swapper/621:15:026
86281799376375,1cyclictest0-21swapper/619:15:036
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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