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2026-05-10 - 12:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun May 10, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85618499381379,1cyclictest965191-21kworker/4:221:59:024
85618499381379,1cyclictest853043-21kworker/4:121:15:014
85618499381379,1cyclictest1154650-21kworker/4:100:22:024
85618499381379,1cyclictest1006787-21kworker/4:123:27:024
856184993810,380cyclictest0-21swapper/423:31:024
856184993810,380cyclictest0-21swapper/421:40:014
856184993810,380cyclictest0-21swapper/421:35:014
85618499380378,1cyclictest965191-21kworker/4:221:50:024
85618499380378,1cyclictest853043-21kworker/4:121:21:024
85618499380377,2cyclictest853043-21kworker/4:119:43:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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