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2026-01-09 - 11:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jan 09, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
252099424670,3sleep335-21ksoftirqd/319:05:183
252251399357356,1cyclictest2577448-21kworker/7:221:35:027
252251399319317,1cyclictest0-21swapper/722:09:027
252246799317316,1cyclictest0-21swapper/121:35:021
252251399313312,1cyclictest0-21swapper/721:33:027
252251399312310,1cyclictest0-21swapper/721:49:017
252248599312310,1cyclictest0-21swapper/321:35:013
252251399311309,1cyclictest0-21swapper/723:27:017
252251399309307,1cyclictest2522361-21kworker/7:219:15:027
252251399308306,1cyclictest2753612-21kworker/7:023:39:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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