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2026-05-27 - 12:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed May 27, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291934799378376,1cyclictest3892613-21kworker/5:100:12:025
291934799375374,1cyclictest3892613-21kworker/5:121:22:025
291934799373372,1cyclictest0-21swapper/500:39:025
291934799372370,1cyclictest0-21swapper/523:17:025
291934799372370,1cyclictest0-21swapper/521:28:025
291934799371370,1cyclictest3892613-21kworker/5:121:17:025
291934799371370,1cyclictest0-21swapper/500:30:025
291934799370369,1cyclictest0-21swapper/521:36:025
291934799370368,1cyclictest3892613-21kworker/5:122:35:025
291934799369368,1cyclictest3892613-21kworker/5:122:04:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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