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2026-06-17 - 01:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Jun 16, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1992940993810,380cyclictest0-21swapper/207:55:022
1992940993810,380cyclictest0-21swapper/207:50:022
199294099380378,1cyclictest2020521-21kworker/2:211:13:012
1992940993800,379cyclictest0-21swapper/211:00:022
1992940993800,379cyclictest0-21swapper/210:20:022
1992940993800,379cyclictest0-21swapper/208:50:022
1992940993800,379cyclictest0-21swapper/208:10:012
199294099379378,1cyclictest2020521-21kworker/2:208:35:022
199294099379378,1cyclictest0-21swapper/209:19:012
1992940993790,1cyclictest0-21swapper/211:45:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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