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2026-02-16 - 08:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Feb 16, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65477993810,380cyclictest0-21swapper/321:11:013
6550599371370,1cyclictest0-21swapper/723:03:017
6550599369368,1cyclictest0-21swapper/700:07:027
6550599368367,1cyclictest0-21swapper/722:01:017
6550599366365,1cyclictest0-21swapper/723:53:017
6550599365363,1cyclictest0-21swapper/719:45:017
6550599364363,1cyclictest0-21swapper/723:41:027
6550599364363,1cyclictest0-21swapper/700:15:027
6550599363362,1cyclictest0-21swapper/719:25:017
6550599363361,1cyclictest0-21swapper/719:21:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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