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2025-10-17 - 16:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Oct 17, 2025 12:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330381023870,15sleep442-21ksoftirqd/407:05:254
330461799378376,1cyclictest0-21swapper/309:34:013
330461799377375,1cyclictest0-21swapper/307:30:013
330461799376374,1cyclictest0-21swapper/311:40:023
330461799376374,1cyclictest0-21swapper/309:46:013
330461799376374,1cyclictest0-21swapper/308:34:013
330461799376374,1cyclictest0-21swapper/308:26:023
330461799376374,1cyclictest0-21swapper/307:10:013
330461799375373,1cyclictest0-21swapper/311:00:023
330461799375373,1cyclictest0-21swapper/310:14:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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