You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-05 - 11:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Mar 05, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207278899378377,1cyclictest2377976-21kworker/4:221:12:024
207278199377375,1cyclictest0-21swapper/323:54:023
207278199375373,1cyclictest0-21swapper/323:03:023
207279599370369,1cyclictest2364738-21kworker/5:100:25:015
207279599370368,1cyclictest2370816-21kworker/5:219:15:025
207279599369368,1cyclictest0-21swapper/521:55:025
207279599369368,1cyclictest0-21swapper/521:21:025
207279599369366,2cyclictest0-21swapper/519:30:025
207278199369368,1cyclictest2222464-21kworker/3:123:39:023
207278199369368,1cyclictest0-21swapper/300:39:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional