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2026-02-24 - 21:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Feb 24, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327642399381379,1cyclictest3343206-21kworker/3:111:47:023
327642399380379,1cyclictest3286270-21kworker/3:208:01:023
327642399380378,1cyclictest0-21swapper/308:38:023
327640599380379,1cyclictest3267258-21kworker/1:011:41:021
327642399379377,1cyclictest3343206-21kworker/3:111:03:023
327642399379377,1cyclictest0-21swapper/308:11:023
327642399378377,1cyclictest3286270-21kworker/3:208:57:023
327642399378376,1cyclictest0-21swapper/309:19:023
327642399377375,1cyclictest0-21swapper/310:02:023
327642399377375,1cyclictest0-21swapper/309:37:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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