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2026-05-11 - 22:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon May 11, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147172999368366,1cyclictest1729769-21kworker/3:207:13:023
147172999368366,1cyclictest1556776-21kworker/3:009:59:023
147172999368366,1cyclictest0-21swapper/312:19:023
147172999367366,1cyclictest1729769-21kworker/3:207:27:013
147172999367366,1cyclictest1556776-21kworker/3:011:41:013
147172999367365,1cyclictest1556776-21kworker/3:010:13:013
147172999367365,1cyclictest1514661-21kworker/3:108:37:023
147172999367365,1cyclictest0-21swapper/308:05:023
147172999367364,2cyclictest1556776-21kworker/3:011:13:023
147172999365364,1cyclictest1556776-21kworker/3:011:59:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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