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2026-06-10 - 04:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jun 10, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
379347799368366,1cyclictest0-21swapper/122:39:021
379347799367366,1cyclictest0-21swapper/123:39:021
379347799367365,1cyclictest0-21swapper/123:55:031
379347799364363,1cyclictest0-21swapper/122:45:021
379347799364363,1cyclictest0-21swapper/122:45:021
379352199363361,1cyclictest0-21swapper/723:55:027
379347799363362,1cyclictest0-21swapper/120:17:031
379352199361360,1cyclictest0-21swapper/722:45:037
379352199361360,1cyclictest0-21swapper/722:45:027
379347799361360,1cyclictest0-21swapper/122:33:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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