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2026-04-09 - 17:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Apr 09, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2451988993810,380cyclictest0-21swapper/207:24:022
245202599357356,1cyclictest0-21swapper/710:19:027
245199599315313,1cyclictest2494921-21kworker/3:209:55:023
245199599315312,2cyclictest2494921-21kworker/3:208:21:013
245199599314312,1cyclictest2576145-21kworker/3:010:55:013
245199599314312,1cyclictest0-21swapper/309:10:023
245199599313311,1cyclictest0-21swapper/308:25:013
245199599312310,1cyclictest2494921-21kworker/3:209:33:023
245199599312309,2cyclictest2494921-21kworker/3:209:51:023
245199599311310,1cyclictest2576145-21kworker/3:011:17:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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