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2026-08-06 - 18:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Aug 06, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
351284099383381,1cyclictest3618933-21kworker/7:111:27:027
351284099383381,1cyclictest3618933-21kworker/7:111:17:037
351284099382380,1cyclictest3618933-21kworker/7:111:57:027
351284099382380,1cyclictest3552722-21kworker/7:009:37:037
351284099381379,1cyclictest3618933-21kworker/7:111:11:027
351284099381379,1cyclictest3618933-21kworker/7:111:11:027
351284099381379,1cyclictest3618933-21kworker/7:110:49:027
351284099380379,1cyclictest3552722-21kworker/7:009:11:027
351284099380378,1cyclictest3766695-21kworker/7:007:14:037
351284099380378,1cyclictest3552722-21kworker/7:008:23:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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