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2026-03-16 - 07:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 16, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189178323830,4sleep763-21ksoftirqd/719:05:287
189243999381379,1cyclictest3363939-21kworker/0:323:40:020
189243999380379,1cyclictest3363939-21kworker/0:321:16:010
189243999380378,2cyclictest3363939-21kworker/0:321:42:010
189243999380378,1cyclictest3363939-21kworker/0:321:39:020
189243999379378,1cyclictest3363939-21kworker/0:322:51:010
189243999379378,1cyclictest3363939-21kworker/0:321:11:010
189243999379377,1cyclictest3363939-21kworker/0:323:45:020
189243999378377,1cyclictest3363939-21kworker/0:300:01:010
189243999377376,1cyclictest0-21swapper/023:18:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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