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2026-08-14 - 01:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Aug 13, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
192482699383380,3cyclictest2090976-21kworker/1:312:11:011
1924826993810,1cyclictest0-21swapper/111:22:011
1924826993810,1cyclictest0-21swapper/108:11:021
192482699380378,1cyclictest1952724-21kworker/1:111:35:021
192482699380377,2cyclictest1952724-21kworker/1:108:33:021
1924826993800,380cyclictest0-21swapper/111:46:021
1924826993800,380cyclictest0-21swapper/111:41:021
1924826993800,380cyclictest0-21swapper/111:34:021
1924826993800,380cyclictest0-21swapper/111:02:021
1924826993800,380cyclictest0-21swapper/109:51:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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