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2026-05-07 - 04:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu May 07, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
395148499376374,2cyclictest4021510-21kworker/0:000:31:030
395148499376374,1cyclictest4021510-21kworker/0:023:06:020
395148499374372,1cyclictest4021510-21kworker/0:023:39:010
395148499373372,1cyclictest4021510-21kworker/0:021:49:020
395148499371369,1cyclictest0-21swapper/023:32:020
395148499371369,1cyclictest0-21swapper/022:25:010
395148499370368,1cyclictest4021510-21kworker/0:022:02:010
395148499370367,2cyclictest4021510-21kworker/0:021:42:010
395148499369368,1cyclictest4021510-21kworker/0:022:45:010
395148499369367,2cyclictest4021510-21kworker/0:021:13:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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