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2026-04-03 - 15:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Apr 03, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28612099363362,1cyclictest0-21swapper/408:36:024
28612099362359,2cyclictest0-21swapper/410:01:024
28612099361360,1cyclictest0-21swapper/411:55:024
28612099361359,1cyclictest0-21swapper/409:55:024
28612099360359,1cyclictest0-21swapper/412:10:024
28612099360359,1cyclictest0-21swapper/408:55:024
28612099360358,1cyclictest0-21swapper/412:25:024
28612099360358,1cyclictest0-21swapper/408:14:024
28612099359358,1cyclictest0-21swapper/411:18:024
28612099359358,1cyclictest0-21swapper/410:25:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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