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2026-01-26 - 20:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Jan 26, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79545023950,2sleep00-21swapper/007:05:160
797250993810,380cyclictest0-21swapper/512:24:025
797250993810,380cyclictest0-21swapper/512:16:025
797250993810,380cyclictest0-21swapper/511:06:025
797250993810,380cyclictest0-21swapper/510:33:025
797250993810,380cyclictest0-21swapper/510:12:025
797250993810,380cyclictest0-21swapper/507:26:025
797250993810,1cyclictest0-21swapper/508:59:025
797250993810,1cyclictest0-21swapper/507:32:025
797250993800,379cyclictest0-21swapper/510:59:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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