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2025-06-29 - 00:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Jun 28, 2025 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
61073699383381,1cyclictest662701-21kworker/1:108:54:031
61073699382381,1cyclictest662701-21kworker/1:111:59:031
610736993820,381cyclictest0-21swapper/110:57:021
61073699379378,1cyclictest746892-21kworker/1:211:01:031
61073699378377,1cyclictest888364-21kworker/1:007:25:031
61073699377376,1cyclictest0-21swapper/107:38:021
61073699377375,1cyclictest0-21swapper/108:00:031
61073699376375,1cyclictest662701-21kworker/1:112:26:021
61073699376375,1cyclictest0-21swapper/107:18:011
61073699375374,1cyclictest0-21swapper/108:20:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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