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2026-04-27 - 12:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Apr 27, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39597999380379,1cyclictest593695-21kworker/2:323:26:022
39597999380379,1cyclictest444948-21kworker/2:122:37:022
39597999380379,1cyclictest444948-21kworker/2:121:49:022
39597999380378,2cyclictest444948-21kworker/2:121:23:032
39597999380377,2cyclictest444948-21kworker/2:121:51:032
39597999380377,2cyclictest444948-21kworker/2:121:51:022
395979993800,379cyclictest0-21swapper/223:45:032
395979993800,379cyclictest0-21swapper/222:00:022
39597999379377,1cyclictest444948-21kworker/2:121:32:022
39597999378377,1cyclictest675623-21kworker/2:000:38:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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