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2026-04-11 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Apr 11, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321081499377376,1cyclictest0-21swapper/110:55:021
321081499377376,1cyclictest0-21swapper/110:13:021
321081499376375,1cyclictest0-21swapper/111:15:021
321081499376375,1cyclictest0-21swapper/109:45:011
321081499376374,1cyclictest0-21swapper/111:25:011
321081499376374,1cyclictest0-21swapper/109:40:011
321081499375374,1cyclictest0-21swapper/112:10:031
321081499375374,1cyclictest0-21swapper/107:50:011
321081499375374,1cyclictest0-21swapper/107:50:011
321081499374373,1cyclictest0-21swapper/110:01:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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