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2026-03-29 - 11:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Mar 29, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246413799376375,1cyclictest2585019-21kworker/5:223:27:025
246413799370369,1cyclictest2585019-21kworker/5:222:31:025
246413799365364,1cyclictest2585019-21kworker/5:223:57:025
246413799365364,1cyclictest2585019-21kworker/5:223:57:015
246413799364363,1cyclictest0-21swapper/523:06:025
246413799364361,2cyclictest2419640-21kworker/5:121:35:015
246413799363362,1cyclictest2585019-21kworker/5:222:29:025
246413799363361,1cyclictest2419640-21kworker/5:121:27:025
246413799363360,2cyclictest2585019-21kworker/5:221:55:025
246413799362361,1cyclictest2585019-21kworker/5:223:31:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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