You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-11 - 18:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Jul 11, 2026 12:46:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2578005993800,1cyclictest0-21swapper/307:23:013
2578005993800,1cyclictest0-21swapper/307:23:013
257803599379378,1cyclictest0-21swapper/712:35:017
257803599377376,1cyclictest2732233-21kworker/7:011:35:017
257803599377376,1cyclictest2732233-21kworker/7:011:35:017
257803599377375,1cyclictest0-21swapper/712:03:017
257803599375374,1cyclictest0-21swapper/708:19:027
257803599374373,1cyclictest2577845-21kworker/7:108:39:027
257803599373371,1cyclictest2732233-21kworker/7:012:33:017
257803599373371,1cyclictest2577845-21kworker/7:109:33:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional