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2026-04-15 - 23:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Apr 15, 2026 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
429882993810,380cyclictest0-21swapper/112:26:021
429882993810,380cyclictest0-21swapper/107:15:031
42988299380379,1cyclictest733771-21kworker/1:107:20:021
42988299380379,1cyclictest569090-21kworker/1:011:20:021
42988299380379,1cyclictest0-21swapper/111:54:021
429882993800,379cyclictest0-21swapper/110:00:021
429882993800,379cyclictest0-21swapper/107:25:031
429882993800,1cyclictest0-21swapper/109:50:021
42988299379377,1cyclictest0-21swapper/109:57:021
42988299378377,1cyclictest733771-21kworker/1:107:44:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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