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2026-07-01 - 09:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Jul 01, 2026 00:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2973768993920,391cyclictest0-21swapper/620:23:026
297376899391390,1cyclictest3235736-21kworker/6:119:44:026
297376899391389,1cyclictest3019501-21kworker/6:020:29:026
2973768993910,1cyclictest0-21swapper/623:11:016
297376899390389,1cyclictest3019501-21kworker/6:021:09:026
2973768993900,1cyclictest0-21swapper/620:47:026
2973768993900,1cyclictest0-21swapper/600:28:016
297376899389388,1cyclictest3235736-21kworker/6:119:58:026
297376899389388,1cyclictest3235736-21kworker/6:119:58:026
297376899389388,1cyclictest3235736-21kworker/6:119:28:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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