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2026-07-18 - 02:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Jul 17, 2026 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
58406699382379,1cyclictest590913-21kworker/1:008:43:021
58408599381379,1cyclictest608954-21kworker/3:208:11:023
58408599381379,1cyclictest580851-21kworker/3:007:47:013
584085993810,380cyclictest0-21swapper/310:38:023
584085993810,380cyclictest0-21swapper/310:38:023
584085993810,380cyclictest0-21swapper/309:30:023
584085993810,380cyclictest0-21swapper/307:52:023
584085993810,380cyclictest0-21swapper/307:52:023
58408599380379,1cyclictest711228-21kworker/3:212:06:013
58408599380379,1cyclictest608954-21kworker/3:208:41:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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