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2026-02-10 - 15:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Feb 10, 2026 12:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2300579993810,1cyclictest0-21swapper/412:29:024
2300579993800,379cyclictest0-21swapper/411:27:024
2300579993800,1cyclictest0-21swapper/412:38:024
2300579993800,1cyclictest0-21swapper/408:37:024
2300579993800,1cyclictest0-21swapper/407:24:024
230059399358357,1cyclictest0-21swapper/607:10:026
230059399347346,1cyclictest0-21swapper/608:50:026
230059399347346,1cyclictest0-21swapper/608:05:026
230059399346345,1cyclictest0-21swapper/611:55:026
230059399346345,1cyclictest0-21swapper/609:35:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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