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2026-03-18 - 16:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Mar 18, 2026 12:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288084499382380,1cyclictest3032100-21kworker/1:011:45:021
288084499381379,1cyclictest3032100-21kworker/1:012:07:021
288084499380378,1cyclictest3032100-21kworker/1:011:27:021
288084499380378,1cyclictest3032100-21kworker/1:011:27:021
288084499380378,1cyclictest2905576-21kworker/1:209:57:021
288084499380378,1cyclictest2905576-21kworker/1:209:57:021
288084499379378,1cyclictest2905576-21kworker/1:208:01:021
288084499378377,1cyclictest2905576-21kworker/1:209:37:021
288084499378376,1cyclictest3032100-21kworker/1:012:29:021
288084499378376,1cyclictest2905576-21kworker/1:209:21:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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