You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-09-14 - 02:22
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Sep 13, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51386999382380,1cyclictest616965-21kworker/3:210:08:033
51386999381379,1cyclictest686158-21kworker/3:111:56:023
51386999381379,1cyclictest616965-21kworker/3:211:34:023
51386999381379,1cyclictest616965-21kworker/3:211:27:023
51386999381379,1cyclictest616965-21kworker/3:211:21:023
51386999381379,1cyclictest1319300-21kworker/3:107:36:023
513869993810,380cyclictest0-21swapper/312:08:023
513869993810,380cyclictest0-21swapper/309:33:023
513869993810,380cyclictest0-21swapper/308:01:023
513869993810,380cyclictest0-21swapper/307:25:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional