You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-15 - 08:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Nov 15, 2025 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290420929543,13sleep60-21swapper/619:06:536
2904660999331,39cyclictest0-21swapper/621:33:136
2904660998916,39cyclictest0-21swapper/600:18:126
2904639998615,40cyclictest0-21swapper/322:08:123
290426228644,13sleep30-21swapper/319:07:393
31955782850,2sleep010-21ksoftirqd/000:00:120
2904660998516,36cyclictest0-21swapper/621:23:136
2904639998516,37cyclictest0-21swapper/322:58:133
2904660998418,37cyclictest0-21swapper/600:28:136
290442728343,33sleep70-21swapper/719:09:597
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional