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2026-01-29 - 06:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Jan 29, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
163237699381379,1cyclictest0-21swapper/421:22:024
163237699377375,1cyclictest1705344-21diskmemload00:27:024
163237699376374,1cyclictest1921234-21kworker/4:000:32:034
163237699374373,1cyclictest1672282-21kworker/4:222:43:024
163237699374373,1cyclictest0-21swapper/422:58:034
163237699374373,1cyclictest0-21swapper/422:10:034
163237699374373,1cyclictest0-21swapper/420:30:024
163237699374373,1cyclictest0-21swapper/400:06:024
163237699373372,1cyclictest0-21swapper/423:23:034
163237699373372,1cyclictest0-21swapper/421:56:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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