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2026-02-13 - 17:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Feb 13, 2026 12:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341142199381379,1cyclictest3553380-21kworker/3:211:18:023
3411421993810,380cyclictest0-21swapper/312:00:023
3411421993810,380cyclictest0-21swapper/307:20:023
341145199380379,1cyclictest0-21swapper/710:15:027
3411421993800,379cyclictest0-21swapper/311:30:023
341145199379378,1cyclictest0-21swapper/709:15:027
341145199379377,1cyclictest0-21swapper/710:57:027
341142199379378,1cyclictest3484432-21kworker/3:010:08:023
341142199379378,1cyclictest3445331-21kworker/3:209:00:023
341142199379378,1cyclictest0-21swapper/312:20:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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