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2026-02-27 - 01:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Feb 26, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4010322993810,0cyclictest0-21swapper/610:18:026
4010322993810,0cyclictest0-21swapper/610:18:026
401032299376375,1cyclictest0-21swapper/612:05:016
401032299375374,1cyclictest0-21swapper/611:20:026
401032299375373,1cyclictest0-21swapper/611:15:026
401032299374373,1cyclictest0-21swapper/611:57:016
401032299374373,1cyclictest0-21swapper/608:25:026
401032299374372,1cyclictest4116412-21kworker/6:010:50:026
401032299373372,1cyclictest4116412-21kworker/6:010:55:026
401032299373372,1cyclictest4059170-21kworker/6:309:30:016
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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