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2026-03-31 - 03:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 31, 2026 00:46:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312098299377375,1cyclictest3139798-21kworker/7:020:17:027
312096199356355,1cyclictest3419916-21kworker/4:123:13:014
312093899352351,1cyclictest3218855-21kworker/1:023:03:021
312093899351350,1cyclictest0-21swapper/121:10:021
312093899351350,1cyclictest0-21swapper/120:07:021
312093899351350,1cyclictest0-21swapper/120:07:021
312093899351348,2cyclictest3166875-21kworker/1:120:59:011
312093899349348,1cyclictest0-21swapper/100:15:021
312093899349348,1cyclictest0-21swapper/100:07:021
312093899349346,2cyclictest3218855-21kworker/1:022:30:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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