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2026-02-26 - 11:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Feb 26, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
376673299382380,1cyclictest4034237-21kworker/0:200:13:020
376678599380377,2cyclictest3899720-21ssh22:00:027
376678599380377,1cyclictest3945152-21kworker/7:300:15:027
376673299380379,1cyclictest4034237-21kworker/0:200:26:020
376673299380379,1cyclictest3797644-21kworker/0:023:36:020
376673299380379,1cyclictest3797644-21kworker/0:022:52:020
376673299380379,1cyclictest3797644-21kworker/0:022:41:020
376673299380379,1cyclictest3797644-21kworker/0:020:13:020
376673299380379,1cyclictest0-21swapper/023:05:030
376673299380378,1cyclictest3797644-21kworker/0:023:43:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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