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2026-07-05 - 12:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sun Jul 05, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17134424790,2sleep60-21swapper/619:05:126
173945993831,381cyclictest0-21swapper/321:51:023
173945993831,381cyclictest0-21swapper/319:17:023
173945993831,381cyclictest0-21swapper/300:21:023
173945993831,2cyclictest0-21swapper/322:43:023
173945993831,1cyclictest0-21swapper/320:35:023
173945993830,382cyclictest0-21swapper/321:41:023
17394599382380,1cyclictest0-21swapper/321:03:023
173945993821,381cyclictest0-21swapper/321:33:023
173945993821,380cyclictest0-21swapper/322:45:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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