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2025-12-05 - 04:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Fri Dec 05, 2025 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159017221050,7sleep40-21swapper/419:05:124
15929049910133,35cyclictest0-21swapper/623:33:156
1592891999412,49cyclictest1698899-21ssh21:33:154
18751792920,0sleep3341rcuc/323:51:243
18751792920,0sleep3341rcuc/323:51:243
18124432910,1sleep010-21ksoftirqd/023:02:110
1592899998918,41cyclictest0-21swapper/520:48:155
1592911998817,38cyclictest0-21swapper/700:18:157
1592911998516,36cyclictest0-21swapper/721:43:147
1592899998516,38cyclictest0-21swapper/521:58:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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