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2026-03-11 - 08:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Wed Mar 11, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5898223970,6sleep50-21swapper/519:05:165
6103699375373,1cyclictest206003-21kworker/4:223:41:024
6100499361357,1cyclictest79889-21kworker/0:122:13:020
6100499361357,1cyclictest79889-21kworker/0:122:13:020
6100499360357,1cyclictest79889-21kworker/0:122:58:020
6100499357355,1cyclictest79889-21kworker/0:122:21:020
6100499356354,1cyclictest79889-21kworker/0:121:53:020
6100499356354,1cyclictest79889-21kworker/0:121:19:020
6100499356354,1cyclictest79889-21kworker/0:121:12:020
6100499355354,1cyclictest280292-21kworker/0:023:37:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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