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2026-03-03 - 17:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 03, 2026 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159462599337336,1cyclictest1745577-21kworker/7:212:01:027
159462599337336,1cyclictest0-21swapper/712:31:027
159459399337336,1cyclictest0-21swapper/312:01:013
159462599336335,1cyclictest1594463-21kworker/7:107:25:027
159459399336335,1cyclictest1727784-21kworker/3:012:31:013
159459399336334,1cyclictest0-21swapper/310:15:023
159459399336334,1cyclictest0-21swapper/307:25:023
159462599335334,1cyclictest1665708-21kworker/7:210:15:027
159462599334332,1cyclictest0-21swapper/707:11:027
159459399334332,1cyclictest0-21swapper/310:35:013
159462599333332,1cyclictest1718766-21kworker/7:110:35:027
159462599333332,1cyclictest0-21swapper/710:00:027
159462599333331,1cyclictest1718766-21kworker/7:110:44:017
159462599333331,1cyclictest1665708-21kworker/7:210:23:027
159462599333331,1cyclictest1594463-21kworker/7:107:20:027
159462599333331,1cyclictest0-21swapper/709:35:027
159462599333331,1cyclictest0-21swapper/708:31:027
159459399333331,1cyclictest1870637-21kworker/3:207:11:023
159459399333331,1cyclictest0-21swapper/310:44:023
159462599332330,1cyclictest1745577-21kworker/7:211:45:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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