You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-10-29 - 01:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Tue Oct 28, 2025 12:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32775592135117,16sleep00-21swapper/007:05:440
32766622110104,3sleep20-21swapper/207:05:222
327817229543,13sleep70-21swapper/707:07:447
3278557999015,40cyclictest0-21swapper/511:33:105
3278549998816,42cyclictest42-21ksoftirqd/408:08:104
3278572998616,36cyclictest0-21swapper/707:38:107
3278564998617,37cyclictest0-21swapper/609:53:106
327684828644,34sleep30-21swapper/307:05:233
3278564998517,35cyclictest0-21swapper/610:38:106
3278557998516,37cyclictest0-21swapper/509:43:105
3278564998417,36cyclictest0-21swapper/612:28:106
3278572998316,36cyclictest0-21swapper/710:28:107
3278564998316,35cyclictest0-21swapper/607:48:106
3278564998217,34cyclictest0-21swapper/612:18:106
3278564998217,34cyclictest0-21swapper/612:18:106
3278557998015,36cyclictest0-21swapper/510:03:105
3278557997915,36cyclictest0-21swapper/511:53:105
3278557997715,33cyclictest0-21swapper/511:43:095
32952952750,0sleep00-21swapper/007:35:000
32835132740,0sleep00-21swapper/007:15:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional