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2025-08-29 - 14:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Fri Aug 29, 2025 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149748523870,24sleep20-21swapper/219:05:132
150019199371370,1cyclictest1553989-21kworker/0:221:19:030
150019199370369,1cyclictest0-21swapper/023:03:020
150019199370368,1cyclictest0-21swapper/019:33:030
150019199368367,1cyclictest0-21swapper/022:04:020
150022299367366,1cyclictest1777552-21kworker/4:223:59:034
150019199365363,1cyclictest0-21swapper/022:21:030
150019199364363,1cyclictest1693007-21kworker/0:122:42:020
150019199360359,1cyclictest0-21swapper/021:08:020
150019199357356,1cyclictest1765175-21kworker/0:219:43:020
150019199357356,1cyclictest1553989-21kworker/0:222:33:020
150019199356355,1cyclictest1765175-21kworker/0:219:49:030
150022299355354,1cyclictest0-21swapper/421:19:024
150019199355354,1cyclictest0-21swapper/019:21:030
150019199354353,1cyclictest0-21swapper/023:07:020
150019199354353,1cyclictest0-21swapper/022:17:030
150019199354352,1cyclictest0-21swapper/022:37:030
150019199354351,2cyclictest0-21swapper/021:24:030
150019199354351,2cyclictest0-21swapper/021:24:030
150022299353352,1cyclictest1693075-21kworker/4:123:03:034
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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