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2026-02-08 - 08:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sun Feb 08, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123892999382379,2cyclictest1466151-21kworker/2:019:21:022
123895899381379,1cyclictest1517731-21kworker/6:019:40:026
1238958993810,380cyclictest0-21swapper/623:57:026
1238958993810,380cyclictest0-21swapper/622:43:026
1238958993810,380cyclictest0-21swapper/622:43:026
123892999381379,1cyclictest1251766-21kworker/2:120:01:022
123892999381378,2cyclictest1251766-21kworker/2:121:26:012
123892999381378,2cyclictest1251766-21kworker/2:119:59:022
1238929993810,380cyclictest0-21swapper/222:02:022
123895899380379,1cyclictest1352246-21kworker/6:122:32:026
123895899380379,1cyclictest1251767-21kworker/6:219:30:026
1238958993800,379cyclictest0-21swapper/600:26:026
1238958993800,1cyclictest0-21swapper/622:00:016
1238958993800,1cyclictest0-21swapper/619:10:016
123892999380379,1cyclictest1251766-21kworker/2:122:25:022
123892999380378,1cyclictest1427210-21kworker/2:222:52:022
123892999380378,1cyclictest1251766-21kworker/2:120:19:012
1238958993790,379cyclictest0-21swapper/622:27:026
123892999379377,2cyclictest1251766-21kworker/2:120:26:022
1238929993790,379cyclictest0-21swapper/222:40:022
1238929993790,379cyclictest0-21swapper/222:40:012
123895899378376,1cyclictest0-21swapper/619:19:016
123892999378376,1cyclictest1447561-21kworker/2:023:08:012
123892999378376,1cyclictest1251766-21kworker/2:121:35:022
123892999378376,1cyclictest1251766-21kworker/2:119:42:012
123895899377376,1cyclictest0-21swapper/620:48:026
123895899377376,1cyclictest0-21swapper/619:46:026
123895899377376,1cyclictest0-21swapper/619:23:026
123895899377375,1cyclictest0-21swapper/619:51:016
123895899376375,1cyclictest0-21swapper/620:39:016
123895899376375,1cyclictest0-21swapper/620:04:026
123895199376374,1cyclictest97550irq/166-enp0s3100:01:015
123892999376375,1cyclictest1467389-21kworker/2:223:24:022
123892999376375,1cyclictest1251766-21kworker/2:122:08:022
123752223760,12sleep0101ksoftirqd/019:05:200
123895899375374,1cyclictest0-21swapper/620:32:016
123892999375374,1cyclictest1467389-21kworker/2:223:40:012
123892999375374,1cyclictest1466151-21kworker/2:019:26:022
123892999375374,1cyclictest1466151-21kworker/2:019:16:022
123892999375374,1cyclictest1251766-21kworker/2:121:07:022
123892999374373,1cyclictest1466151-21kworker/2:019:10:022
123892999374372,2cyclictest1467389-21kworker/2:223:57:012
123892999374372,1cyclictest1467389-21kworker/2:200:26:012
123895899373372,1cyclictest0-21swapper/620:13:026
123892999373371,1cyclictest0-21swapper/221:24:012
123895199372370,1cyclictest97550irq/166-enp0s3123:29:025
123895199372369,2cyclictest97550irq/166-enp0s3121:13:025
123895199372369,2cyclictest97550irq/166-enp0s3121:13:025
123892999372371,1cyclictest1251766-21kworker/2:121:54:012
123892999372371,1cyclictest0-21swapper/221:40:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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