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2026-03-02 - 03:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 02, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96168899367365,1cyclictest0-21swapper/100:08:021
96168099344342,1cyclictest0-21swapper/000:19:010
96172199339338,1cyclictest1151847-21kworker/5:023:07:015
96172199337336,1cyclictest989604-21kworker/5:122:45:015
96172199337336,1cyclictest1151847-21kworker/5:022:51:015
96172199337335,1cyclictest1252821-21kworker/5:200:39:025
96172199336334,1cyclictest1151847-21kworker/5:022:55:015
96172199335333,1cyclictest1098544-21kworker/5:022:05:015
96172199334333,1cyclictest989604-21kworker/5:121:11:025
96172199334333,1cyclictest1151847-21kworker/5:023:45:025
96172199334332,1cyclictest1252821-21kworker/5:200:29:015
96172199333332,1cyclictest989604-21kworker/5:122:27:015
96172199333331,1cyclictest989604-21kworker/5:122:35:015
96172199333331,1cyclictest989604-21kworker/5:122:23:025
96172199332331,1cyclictest989604-21kworker/5:121:53:025
96172199332331,1cyclictest1151847-21kworker/5:023:03:015
96172199332330,2cyclictest989604-21kworker/5:121:21:025
96172199332330,1cyclictest989604-21kworker/5:121:33:015
96172199331330,1cyclictest1151847-21kworker/5:023:25:015
96172199331330,1cyclictest1151847-21kworker/5:000:05:015
96172199331329,1cyclictest1264173-21kworker/5:219:53:025
96171399331328,2cyclictest1233056-21kworker/4:200:19:024
96172199330329,1cyclictest989604-21kworker/5:121:05:015
96172199330329,1cyclictest989604-21kworker/5:121:05:015
96172199330329,1cyclictest1151847-21kworker/5:023:23:025
96172199328327,1cyclictest989604-21kworker/5:121:37:015
96172199328327,1cyclictest989604-21kworker/5:119:55:025
96172199328327,1cyclictest1252821-21kworker/5:200:13:015
96172199328326,1cyclictest989604-21kworker/5:121:57:015
96172199328326,1cyclictest989604-21kworker/5:120:51:015
96172199327326,1cyclictest1151847-21kworker/5:023:51:025
96172199327326,1cyclictest1151847-21kworker/5:023:35:025
96172199327325,1cyclictest1264173-21kworker/5:219:15:025
96172199327325,1cyclictest1151847-21kworker/5:023:43:025
96172199326325,1cyclictest1151847-21kworker/5:023:57:025
96172199326324,1cyclictest1151847-21kworker/5:023:17:025
96172199324323,1cyclictest1264173-21kworker/5:219:25:025
96172199324322,1cyclictest989604-21kworker/5:122:15:025
96172199324322,1cyclictest1252821-21kworker/5:200:33:015
96172199323321,1cyclictest989604-21kworker/5:121:47:025
96172199322321,1cyclictest989604-21kworker/5:121:43:015
96172199322319,2cyclictest989604-21kworker/5:121:26:025
96172199322319,2cyclictest989604-21kworker/5:121:19:025
96172199321320,1cyclictest989604-21kworker/5:122:10:025
96172199321320,1cyclictest989604-21kworker/5:120:43:025
96172199321320,1cyclictest989604-21kworker/5:120:37:025
96172199321320,1cyclictest1264173-21kworker/5:219:23:025
96172199321320,1cyclictest1252821-21kworker/5:200:18:015
96172199321320,1cyclictest1151847-21kworker/5:000:00:015
96172199320319,1cyclictest989604-21kworker/5:122:31:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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