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2026-02-20 - 05:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Fri Feb 20, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154807399381380,1cyclictest1735775-21kworker/6:122:58:026
154807399381379,1cyclictest1735775-21kworker/6:122:52:026
154807399380379,1cyclictest1811816-21kworker/6:200:35:026
154807399380379,1cyclictest1735775-21kworker/6:123:21:026
154807399380379,1cyclictest1655299-21kworker/6:022:29:026
154807399380379,1cyclictest0-21swapper/622:38:016
154807399380378,1cyclictest1735775-21kworker/6:123:15:026
1548073993800,379cyclictest0-21swapper/623:53:026
154807399379378,1cyclictest1811816-21kworker/6:200:10:026
154807399379378,1cyclictest1735775-21kworker/6:123:08:016
154807399379378,1cyclictest1655299-21kworker/6:022:40:026
154807399379378,1cyclictest1655299-21kworker/6:022:06:026
154807399379378,1cyclictest1655299-21kworker/6:021:57:026
154807399379378,1cyclictest0-21swapper/623:48:026
154807399379378,1cyclictest0-21swapper/621:20:026
154807399379378,1cyclictest0-21swapper/620:45:026
154807399378377,1cyclictest1811816-21kworker/6:200:25:026
154807399378377,1cyclictest1735775-21kworker/6:123:00:026
154807399378377,1cyclictest1655299-21kworker/6:021:54:026
154807399378377,1cyclictest1655299-21kworker/6:021:54:026
154807399378377,1cyclictest0-21swapper/621:17:026
154807399378376,1cyclictest1837148-21kworker/6:100:06:026
154807399378376,1cyclictest1811816-21kworker/6:200:16:026
154804599378376,1cyclictest1800485-21sh23:35:022
154807399377376,1cyclictest1811816-21kworker/6:200:20:026
154807399377376,1cyclictest1554638-21kworker/6:119:25:026
154807399377376,1cyclictest1516059-21kworker/6:221:40:026
154807399377376,1cyclictest1516059-21kworker/6:221:27:026
154807399377376,1cyclictest0-21swapper/623:32:016
154807399377376,1cyclictest0-21swapper/623:12:026
154807399376375,1cyclictest1554638-21kworker/6:120:50:026
154807399376375,1cyclictest1516059-21kworker/6:221:12:026
154807399376375,1cyclictest0-21swapper/621:46:026
154807399376375,1cyclictest0-21swapper/621:05:016
154807399376375,1cyclictest0-21swapper/621:00:026
154807399376375,1cyclictest0-21swapper/620:20:016
154807399376374,1cyclictest0-21swapper/619:30:016
154807399374373,1cyclictest1516059-21kworker/6:219:17:026
154807399374372,1cyclictest0-21swapper/620:57:026
154807399373372,1cyclictest1554638-21kworker/6:119:23:026
154804599373371,1cyclictest1737692-21ssh22:44:022
154807399372371,1cyclictest1554638-21kworker/6:120:44:026
154807399372371,1cyclictest1554638-21kworker/6:119:47:026
154807399372371,1cyclictest1516059-21kworker/6:219:14:026
154807399372370,1cyclictest1554638-21kworker/6:120:28:026
154807399372370,1cyclictest0-21swapper/619:41:026
154807399371370,1cyclictest1554638-21kworker/6:120:06:026
154807399371370,1cyclictest0-21swapper/620:37:026
154807399371370,1cyclictest0-21swapper/619:56:026
154804599369367,1cyclictest1879556-21ssh00:39:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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