You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-15 - 11:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sun Feb 15, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
388214499375374,1cyclictest1161878-21kworker/5:219:55:025
388214499371370,1cyclictest97550irq/166-enp0s3121:57:025
388214499371369,1cyclictest97550irq/166-enp0s3121:47:025
388214499371369,1cyclictest97550irq/166-enp0s3100:37:025
388214499370369,1cyclictest97550irq/166-enp0s3122:35:035
388214499370369,1cyclictest97550irq/166-enp0s3121:21:035
388214499370368,2cyclictest1161878-21kworker/5:219:37:025
388214499370368,2cyclictest1161878-21kworker/5:219:37:025
388214499370368,1cyclictest97550irq/166-enp0s3122:53:025
388214499370368,1cyclictest97550irq/166-enp0s3100:17:025
388214499369368,1cyclictest3946127-21kworker/5:123:03:025
388214499369367,1cyclictest97550irq/166-enp0s3123:53:025
388214499369367,1cyclictest97550irq/166-enp0s3119:15:025
388215999368366,1cyclictest4118501-21kworker/7:223:29:027
388214499368367,1cyclictest97550irq/166-enp0s3123:37:025
388214499368367,1cyclictest97550irq/166-enp0s3121:35:025
388214499368366,1cyclictest97550irq/166-enp0s3123:47:025
388214499368366,1cyclictest97550irq/166-enp0s3122:11:035
388214499368366,1cyclictest97550irq/166-enp0s3122:05:025
388214499368366,1cyclictest97550irq/166-enp0s3100:09:025
388214499367365,2cyclictest1161878-21kworker/5:220:15:025
388214499367365,1cyclictest97550irq/166-enp0s3123:23:025
388214499367365,1cyclictest97550irq/166-enp0s3123:15:025
388214499367365,1cyclictest97550irq/166-enp0s3123:07:025
388214499367365,1cyclictest97550irq/166-enp0s3122:03:025
388214499367365,1cyclictest97550irq/166-enp0s3121:19:035
388214499367365,1cyclictest97550irq/166-enp0s3100:27:025
388214499366365,1cyclictest3946127-21kworker/5:120:57:025
388214499366364,1cyclictest97550irq/166-enp0s3122:55:025
388214499366364,1cyclictest97550irq/166-enp0s3121:41:025
388214499366364,1cyclictest97550irq/166-enp0s3121:11:025
388214499366364,1cyclictest97550irq/166-enp0s3120:21:025
388214499366364,1cyclictest97550irq/166-enp0s3100:33:025
388214499365364,1cyclictest97550irq/166-enp0s3122:15:025
388214499365364,1cyclictest97550irq/166-enp0s3121:27:025
388214499365364,1cyclictest3946127-21kworker/5:123:44:025
388214499365363,1cyclictest97550irq/166-enp0s3123:11:025
388214499365363,1cyclictest97550irq/166-enp0s3121:07:025
388214499365363,1cyclictest97550irq/166-enp0s3120:43:025
388214499364362,1cyclictest97550irq/166-enp0s3119:41:025
388214499364362,1cyclictest97550irq/166-enp0s3100:00:025
388214499364362,1cyclictest3946127-21kworker/5:122:49:025
388214499363362,1cyclictest97550irq/166-enp0s3119:53:025
388214499363362,1cyclictest3946127-21kworker/5:122:21:025
388214499363361,1cyclictest97550irq/166-enp0s3120:45:025
388214499363361,1cyclictest97550irq/166-enp0s3100:21:025
388214499362361,1cyclictest4136939-21kworker/5:223:56:025
388214499362361,1cyclictest4136939-21kworker/5:223:56:025
388214499362360,1cyclictest97550irq/166-enp0s3122:40:025
388214499362360,1cyclictest97550irq/166-enp0s3122:29:035
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional