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2026-02-21 - 06:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sat Feb 21, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190882399380379,1cyclictest2067557-21kworker/6:023:06:026
190882399380378,1cyclictest2067557-21kworker/6:023:50:026
1908823993800,379cyclictest0-21swapper/622:15:026
190882399379378,1cyclictest2067557-21kworker/6:023:48:026
190882399379378,1cyclictest2067557-21kworker/6:022:40:036
190882399379377,2cyclictest2067557-21kworker/6:023:34:026
190882399379377,1cyclictest0-21swapper/622:00:026
190882399378377,1cyclictest0-21swapper/621:41:026
190882399378376,1cyclictest1957760-21kworker/6:121:39:026
190882399378376,1cyclictest0-21swapper/621:29:026
190882399378376,1cyclictest0-21swapper/600:33:026
190882399377376,1cyclictest0-21swapper/623:36:026
190882399377376,1cyclictest0-21swapper/623:12:036
190882399377376,1cyclictest0-21swapper/600:09:036
190882399377375,1cyclictest2067557-21kworker/6:022:49:026
190882399377375,1cyclictest2067557-21kworker/6:022:49:026
190882399377375,1cyclictest1957760-21kworker/6:121:32:026
190882399377375,1cyclictest1957760-21kworker/6:121:17:026
190882399376375,1cyclictest1957760-21kworker/6:122:25:026
190882399376374,1cyclictest0-21swapper/622:22:026
190882399376374,1cyclictest0-21swapper/620:01:036
190882399376374,1cyclictest0-21swapper/600:18:026
190882399375374,1cyclictest1957760-21kworker/6:122:13:026
190882399375374,1cyclictest0-21swapper/623:29:026
190882399375374,1cyclictest0-21swapper/623:02:026
190882399375373,1cyclictest0-21swapper/600:22:026
190880999375374,1cyclictest2152421-21kworker/4:000:04:024
190882399374373,1cyclictest1957760-21kworker/6:120:41:026
190882399373372,1cyclictest2194636-21kworker/6:100:12:026
190882399373372,1cyclictest2067557-21kworker/6:023:44:036
190882399373372,1cyclictest1957760-21kworker/6:121:52:026
190882399373372,1cyclictest0-21swapper/621:20:036
190882399373372,1cyclictest0-21swapper/621:20:026
190882399373372,1cyclictest0-21swapper/619:35:026
190882399372371,1cyclictest0-21swapper/620:50:026
190882399372371,1cyclictest0-21swapper/620:15:026
190882399372371,1cyclictest0-21swapper/619:25:036
190882399372371,1cyclictest0-21swapper/600:28:026
190882399371370,1cyclictest2174562-21kworker/6:220:20:026
190882399370369,1cyclictest1957760-21kworker/6:121:03:036
190882399370369,1cyclictest0-21swapper/620:26:026
190882399370369,1cyclictest0-21swapper/619:59:036
190882399369368,1cyclictest2174562-21kworker/6:219:33:036
190882399369368,1cyclictest0-21swapper/621:06:026
190882399369368,1cyclictest0-21swapper/620:46:026
190882399369368,1cyclictest0-21swapper/619:11:026
190882399368367,1cyclictest0-21swapper/620:59:026
190882399368367,1cyclictest0-21swapper/620:11:026
190882399368367,1cyclictest0-21swapper/619:46:026
190882399367366,1cyclictest0-21swapper/619:22:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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