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2025-05-02 - 12:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Fri May 02, 2025 00:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120333199388384,1cyclictest1228026-21systemd-userwor19:49:023
1203331993860,385cyclictest0-21swapper/320:34:023
1203331993840,383cyclictest0-21swapper/322:51:023
1203331993830,382cyclictest0-21swapper/322:19:023
1203331993830,382cyclictest0-21swapper/320:45:023
1203331993830,382cyclictest0-21swapper/319:52:023
1203331993830,382cyclictest0-21swapper/319:18:023
1203331993830,382cyclictest0-21swapper/300:17:033
120333199382381,1cyclictest0-21swapper/323:10:033
120333199382381,1cyclictest0-21swapper/323:10:033
120333199382380,1cyclictest0-21swapper/323:18:033
1203331993820,381cyclictest0-21swapper/323:24:033
1203331993820,381cyclictest0-21swapper/322:56:033
1203331993820,381cyclictest0-21swapper/319:36:023
1203331993820,381cyclictest0-21swapper/319:33:013
1203331993820,2cyclictest0-21swapper/320:18:023
1203331993820,1cyclictest0-21swapper/321:29:023
1203331993820,1cyclictest0-21swapper/300:11:033
120333199381380,1cyclictest0-21swapper/321:05:023
120333199381380,1cyclictest0-21swapper/321:04:013
1203331993810,380cyclictest0-21swapper/323:45:023
1203331993810,380cyclictest0-21swapper/320:12:023
120333199380378,1cyclictest0-21swapper/320:24:023
1203331993800,0cyclictest0-21swapper/322:01:023
120333199379378,1cyclictest1191186-21kworker/3:219:43:023
120333199378377,1cyclictest1191186-21kworker/3:221:58:013
120333199378377,1cyclictest0-21swapper/320:57:023
120333199378377,1cyclictest0-21swapper/320:25:023
120333199378377,1cyclictest0-21swapper/320:25:013
120333199377376,1cyclictest0-21swapper/300:05:033
120333199377375,1cyclictest1191186-21kworker/3:222:09:023
120333199376374,2cyclictest1471444-21kworker/3:200:33:033
120333199376374,1cyclictest1377579-21kworker/3:023:28:023
120333199376374,1cyclictest0-21swapper/300:24:013
120333199375374,1cyclictest1191186-21kworker/3:221:49:023
120333199375374,1cyclictest0-21swapper/300:26:023
120333199374373,1cyclictest0-21swapper/323:34:033
120333199373372,1cyclictest1471444-21kworker/3:200:04:023
120333199373372,1cyclictest1377579-21kworker/3:023:38:013
120333199373372,1cyclictest1377579-21kworker/3:022:46:003
120333199373372,1cyclictest1191186-21kworker/3:222:38:013
120333199373372,1cyclictest1191186-21kworker/3:221:36:013
120333199373372,1cyclictest0-21swapper/322:41:023
120333199372371,1cyclictest0-21swapper/321:53:023
120333199372371,1cyclictest0-21swapper/321:53:023
120333199372371,1cyclictest0-21swapper/320:35:023
120333199372370,1cyclictest1191186-21kworker/3:220:03:023
120333199371370,1cyclictest0-21swapper/300:37:033
120333199371370,1cyclictest0-21swapper/300:37:033
120333199371369,1cyclictest0-21swapper/321:34:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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