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2026-02-19 - 12:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Thu Feb 19, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117738399382380,1cyclictest1328251-21kworker/0:122:39:020
117739199381379,1cyclictest2653604-21kworker/1:221:49:011
1177391993810,380cyclictest0-21swapper/123:29:011
117738399381380,1cyclictest1328251-21kworker/0:123:40:010
1177433993800,379cyclictest0-21swapper/721:13:017
117739199380379,1cyclictest2653604-21kworker/1:221:36:011
117739199380379,1cyclictest1473997-21kworker/1:200:36:021
117739199380379,1cyclictest1420419-21kworker/1:100:03:021
117739199380379,1cyclictest1313191-21kworker/1:023:16:021
117739199380379,1cyclictest1313191-21kworker/1:023:16:021
117739199380378,2cyclictest2653604-21kworker/1:221:10:021
117739199380378,1cyclictest1420419-21kworker/1:100:14:011
117738399380379,1cyclictest1328251-21kworker/0:123:34:020
117738399380379,1cyclictest1328251-21kworker/0:123:09:020
117739199379378,1cyclictest2653604-21kworker/1:221:26:021
117739199379378,1cyclictest1313191-21kworker/1:022:33:021
117739199379378,1cyclictest1313191-21kworker/1:022:16:021
117739199379378,1cyclictest0-21swapper/121:21:021
117739199379377,1cyclictest0-21swapper/122:11:021
117738399379378,1cyclictest1328251-21kworker/0:122:53:020
117738399379378,1cyclictest1328251-21kworker/0:100:16:020
117738399379378,1cyclictest0-21swapper/022:40:010
117738399379377,1cyclictest1328251-21kworker/0:100:12:010
117739199378377,1cyclictest1420419-21kworker/1:100:09:011
117739199378377,1cyclictest1313191-21kworker/1:022:20:011
117739199378377,1cyclictest0-21swapper/122:38:011
117739199378376,1cyclictest2653604-21kworker/1:221:42:011
117738399378377,1cyclictest1187234-21kworker/0:121:43:010
117743399377376,1cyclictest0-21swapper/722:09:017
117743399377375,1cyclictest0-21swapper/723:49:017
117739199377376,1cyclictest2653604-21kworker/1:220:15:011
117739199377376,1cyclictest0-21swapper/122:57:011
117739199377376,1cyclictest0-21swapper/119:25:021
117739199377375,1cyclictest2653604-21kworker/1:219:57:021
117739199377375,1cyclictest0-21swapper/119:43:011
117738399377376,1cyclictest1328251-21kworker/0:123:15:010
117738399377376,1cyclictest1328251-21kworker/0:123:15:010
117738399377376,1cyclictest0-21swapper/023:23:020
117738399377376,1cyclictest0-21swapper/022:34:010
117738399377376,1cyclictest0-21swapper/021:19:010
117738399377375,1cyclictest1302104-21kworker/0:022:00:010
117738399377375,1cyclictest0-21swapper/023:51:020
117739199376375,1cyclictest0-21swapper/120:55:021
117739199376375,1cyclictest0-21swapper/120:08:021
117739199376375,1cyclictest0-21swapper/119:11:011
117739199376374,1cyclictest2653604-21kworker/1:220:53:021
117739199376374,1cyclictest0-21swapper/100:34:021
117738399376375,1cyclictest1187234-21kworker/0:121:47:020
117738399376375,1cyclictest0-21swapper/023:47:020
117743399375374,1cyclictest1327512-21kworker/7:123:11:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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