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2026-03-01 - 20:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sun Mar 01, 2026 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85075799378375,2cyclictest0-21swapper/007:37:020
85081199375373,1cyclictest820598-21kworker/7:011:08:027
85075799374372,1cyclictest0-21swapper/008:15:010
85075799373371,1cyclictest555235-21kworker/0:110:35:020
85075799372370,1cyclictest0-21swapper/011:25:020
85075799371369,1cyclictest0-21swapper/011:41:020
85075799370368,1cyclictest0-21swapper/008:25:020
85075799369367,1cyclictest555235-21kworker/0:112:01:020
85075799367365,1cyclictest555235-21kworker/0:110:33:020
85075799367365,1cyclictest555235-21kworker/0:108:59:020
85075799367365,1cyclictest0-21swapper/010:43:020
85081199366365,1cyclictest0-21swapper/709:55:017
85081199366365,1cyclictest0-21swapper/709:45:027
85075799366365,1cyclictest555235-21kworker/0:109:50:020
85075799366365,1cyclictest555235-21kworker/0:109:50:020
85075799366364,1cyclictest0-21swapper/007:27:020
85075799366363,2cyclictest555235-21kworker/0:111:46:020
85075799365364,1cyclictest0-21swapper/008:23:020
85075799365363,1cyclictest555235-21kworker/0:109:47:020
85075799365363,1cyclictest555235-21kworker/0:108:49:020
85075799365363,1cyclictest0-21swapper/011:37:020
85076399364363,1cyclictest0-21swapper/111:18:021
85075799364363,1cyclictest555235-21kworker/0:107:42:020
85075799364363,1cyclictest0-21swapper/007:51:020
85075799364362,1cyclictest555235-21kworker/0:109:42:020
85075799364362,1cyclictest555235-21kworker/0:109:08:020
85075799364361,1cyclictest555235-21kworker/0:111:22:020
85075799364361,1cyclictest555235-21kworker/0:111:22:010
85081199363361,1cyclictest0-21swapper/711:57:027
85081199363361,1cyclictest0-21swapper/708:21:027
85075799363362,1cyclictest555235-21kworker/0:112:07:020
85075799363362,1cyclictest555235-21kworker/0:110:21:020
85075799363361,1cyclictest555235-21kworker/0:111:34:020
85081199362360,1cyclictest0-21swapper/709:13:017
85075799361360,1cyclictest555235-21kworker/0:110:07:020
85081199360358,1cyclictest0-21swapper/709:37:027
85081199359358,1cyclictest0-21swapper/710:57:027
85081199359358,1cyclictest0-21swapper/708:37:027
85075799359358,1cyclictest0-21swapper/010:00:020
85081199357356,1cyclictest0-21swapper/707:37:027
85075799357356,1cyclictest555235-21kworker/0:111:00:020
85081199356355,1cyclictest0-21swapper/712:11:027
85075799356354,1cyclictest555235-21kworker/0:111:14:010
85075799356354,1cyclictest0-21swapper/012:12:020
85081199355354,1cyclictest0-21swapper/710:41:027
85081199354352,1cyclictest820598-21kworker/7:011:41:017
85075799354352,1cyclictest555235-21kworker/0:107:48:020
85081199353351,1cyclictest820598-21kworker/7:011:33:027
85075799353351,1cyclictest555235-21kworker/0:109:02:020
85075799353351,1cyclictest0-21swapper/009:14:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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