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2026-02-28 - 07:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sat Feb 28, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28640399380379,1cyclictest280209-21kworker/4:223:50:024
28640399380378,2cyclictest280209-21kworker/4:221:38:024
28640399380378,2cyclictest280209-21kworker/4:221:38:024
28640399380378,2cyclictest280209-21kworker/4:221:24:014
28640399379377,1cyclictest280209-21kworker/4:200:07:024
28640399378377,1cyclictest280209-21kworker/4:223:33:024
28640399378377,1cyclictest280209-21kworker/4:221:54:024
28640399378377,1cyclictest280209-21kworker/4:221:25:024
28640399378376,1cyclictest280209-21kworker/4:222:45:024
28640399378376,1cyclictest280209-21kworker/4:222:36:024
28640399378376,1cyclictest280209-21kworker/4:221:12:024
28640399377376,1cyclictest280209-21kworker/4:222:18:024
28640399377376,1cyclictest280209-21kworker/4:200:14:024
28640399377375,1cyclictest280209-21kworker/4:223:06:024
28640399377375,1cyclictest280209-21kworker/4:221:45:024
28640399376375,1cyclictest280209-21kworker/4:223:26:024
28640399376375,1cyclictest280209-21kworker/4:222:05:024
28640399376374,1cyclictest280209-21kworker/4:222:26:024
28640399375374,1cyclictest280209-21kworker/4:222:41:024
28640399375374,1cyclictest280209-21kworker/4:221:16:024
28640399375374,1cyclictest280209-21kworker/4:200:25:024
28640399375374,1cyclictest0-21swapper/422:50:014
28640399374373,1cyclictest280209-21kworker/4:222:10:024
28640399374373,1cyclictest280209-21kworker/4:221:55:024
28640399373372,1cyclictest280209-21kworker/4:223:45:024
28640399373372,1cyclictest280209-21kworker/4:223:00:024
28640399373372,1cyclictest280209-21kworker/4:223:00:014
28640399372371,1cyclictest280209-21kworker/4:223:37:014
28640399372371,1cyclictest280209-21kworker/4:220:28:024
28640399372371,1cyclictest280209-21kworker/4:220:10:014
28640399372371,1cyclictest280209-21kworker/4:219:45:024
28640399371370,1cyclictest280209-21kworker/4:223:42:024
28640399371370,1cyclictest280209-21kworker/4:220:40:024
28640399370369,1cyclictest280209-21kworker/4:220:20:024
28640399370369,1cyclictest280209-21kworker/4:220:15:024
28640399370369,1cyclictest280209-21kworker/4:220:15:024
28640399370369,1cyclictest280209-21kworker/4:219:25:024
28640399368367,1cyclictest280209-21kworker/4:221:03:024
28640399368367,1cyclictest280209-21kworker/4:220:32:024
28640399367366,1cyclictest280209-21kworker/4:220:51:024
28640399367366,1cyclictest280209-21kworker/4:220:49:024
28640399367366,1cyclictest280209-21kworker/4:219:57:024
28640399367366,1cyclictest280209-21kworker/4:219:43:024
28640399367366,1cyclictest280209-21kworker/4:219:23:024
28640399367366,1cyclictest280209-21kworker/4:219:17:024
28640399367366,1cyclictest280209-21kworker/4:219:13:014
28641699366364,1cyclictest0-21swapper/620:19:026
28641699366364,1cyclictest0-21swapper/620:19:026
28640399366364,1cyclictest280209-21kworker/4:220:38:014
28638099362360,1cyclictest474648-21kworker/u16:222:55:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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