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2026-07-09 - 15:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Thu Jul 09, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184109299363362,1cyclictest0-21swapper/512:35:025
184109299363362,1cyclictest0-21swapper/509:42:025
184109299363361,1cyclictest0-21swapper/511:35:025
184109299361360,1cyclictest1914124-21kworker/5:111:20:025
184109299361360,1cyclictest0-21swapper/511:01:015
184109299360359,1cyclictest1914124-21kworker/5:109:53:015
184109299360359,1cyclictest0-21swapper/512:00:025
184109299360359,1cyclictest0-21swapper/511:18:025
184109299360359,1cyclictest0-21swapper/507:21:025
184109299360358,1cyclictest1805568-21kworker/5:207:15:025
184109299360358,1cyclictest1805568-21kworker/5:207:15:025
184109299359358,1cyclictest0-21swapper/512:15:025
184109299358357,1cyclictest0-21swapper/509:34:025
184109299358357,1cyclictest0-21swapper/508:30:015
184109299358357,1cyclictest0-21swapper/508:15:025
184109299358357,1cyclictest0-21swapper/508:01:015
184109299358355,2cyclictest1914124-21kworker/5:110:03:025
184109299357356,1cyclictest1914124-21kworker/5:110:26:015
184109299357356,1cyclictest0-21swapper/512:21:025
184109299357356,1cyclictest0-21swapper/511:05:025
184109299357356,1cyclictest0-21swapper/510:50:015
184109299357356,1cyclictest0-21swapper/510:49:015
184109299357356,1cyclictest0-21swapper/508:05:015
184109299357356,1cyclictest0-21swapper/507:10:025
184109299357355,1cyclictest0-21swapper/509:01:025
184109299356355,1cyclictest1914124-21kworker/5:110:19:025
184109299356355,1cyclictest1914124-21kworker/5:110:19:015
184109299355354,1cyclictest0-21swapper/512:11:025
184109299355354,1cyclictest0-21swapper/511:42:025
184109299355354,1cyclictest0-21swapper/511:12:025
184109299355354,1cyclictest0-21swapper/509:26:015
184109299355354,1cyclictest0-21swapper/509:07:015
184109299355354,1cyclictest0-21swapper/507:36:025
184109299355353,1cyclictest0-21swapper/508:37:015
184109299355353,1cyclictest0-21swapper/507:33:025
184109299354353,1cyclictest0-21swapper/511:51:025
184109299354353,1cyclictest0-21swapper/510:55:015
184109299354353,1cyclictest0-21swapper/510:44:015
184109299354353,1cyclictest0-21swapper/507:28:025
184109299354352,1cyclictest0-21swapper/510:34:025
184109299354352,1cyclictest0-21swapper/509:21:015
184106099354352,2cyclictest1911105-21kworker/1:009:42:011
184109299353352,1cyclictest1914124-21kworker/5:110:06:015
184109299353352,1cyclictest0-21swapper/510:37:025
184109299353352,1cyclictest0-21swapper/509:57:025
184109299353352,1cyclictest0-21swapper/507:51:015
184106099353352,1cyclictest2010377-21kworker/1:212:35:021
184109299352351,1cyclictest0-21swapper/511:48:025
184109299352351,1cyclictest0-21swapper/511:48:025
184109299352351,1cyclictest0-21swapper/510:23:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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