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2026-02-01 - 06:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sun Feb 01, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285663099371370,1cyclictest0-21swapper/523:56:025
285663099371369,2cyclictest2923613-21kworker/5:022:59:025
285663099369367,1cyclictest2850446-21kworker/5:219:10:035
285663099368367,1cyclictest2923613-21kworker/5:021:53:025
285663099367366,1cyclictest2923613-21kworker/5:021:22:025
285663099367366,1cyclictest0-21swapper/500:24:025
285663099367364,2cyclictest2923613-21kworker/5:000:01:025
285663099366365,1cyclictest97550irq/166-enp0s3123:40:025
285663099366365,1cyclictest0-21swapper/523:52:025
285663099366365,1cyclictest0-21swapper/500:39:025
285663099366363,2cyclictest2850446-21kworker/5:220:00:025
285663099365364,1cyclictest2923613-21kworker/5:023:49:025
285663099365364,1cyclictest2923613-21kworker/5:023:49:025
285663099365364,1cyclictest2923613-21kworker/5:023:06:035
285663099365363,1cyclictest2923613-21kworker/5:022:38:025
285663099364363,1cyclictest2923613-21kworker/5:022:25:025
285663099364363,1cyclictest0-21swapper/523:04:035
285663099363362,1cyclictest2923613-21kworker/5:023:14:025
285663099363362,1cyclictest2923613-21kworker/5:000:15:035
285663099363362,1cyclictest0-21swapper/521:30:035
285663099363362,1cyclictest0-21swapper/500:31:025
285663099363362,1cyclictest0-21swapper/500:10:035
285663099363362,1cyclictest0-21swapper/500:06:035
285663099363361,1cyclictest2923613-21kworker/5:022:32:035
285663099363361,1cyclictest2923613-21kworker/5:021:47:025
285663099362361,1cyclictest2850446-21kworker/5:219:15:035
285663099362361,1cyclictest0-21swapper/522:14:025
285663099362361,1cyclictest0-21swapper/521:56:025
285663099362361,1cyclictest0-21swapper/521:10:025
285663099362360,2cyclictest2923613-21kworker/5:022:40:025
285663099361360,1cyclictest2923613-21kworker/5:023:39:025
285663099361360,1cyclictest2923613-21kworker/5:022:54:025
285663099361360,1cyclictest2923613-21kworker/5:021:44:025
285663099361360,1cyclictest0-21swapper/522:20:025
285663099361360,1cyclictest0-21swapper/521:38:025
285663099360359,1cyclictest2923613-21kworker/5:021:16:025
285663099360359,1cyclictest2850446-21kworker/5:220:25:025
285663099360359,1cyclictest0-21swapper/523:32:035
285663099360359,1cyclictest0-21swapper/522:07:025
285663099360359,1cyclictest0-21swapper/522:04:035
285663099359358,1cyclictest0-21swapper/522:15:035
285663099359358,1cyclictest0-21swapper/522:15:025
285663099359358,1cyclictest0-21swapper/519:59:025
285663099358356,1cyclictest2850446-21kworker/5:220:52:025
285663099357356,1cyclictest2923613-21kworker/5:021:00:025
285663099357354,3cyclictest0-21swapper/520:21:025
285663099356355,1cyclictest2850446-21kworker/5:219:28:025
285663099356355,1cyclictest2850446-21kworker/5:219:28:025
285663099356354,1cyclictest2850446-21kworker/5:220:46:035
285663099356354,1cyclictest0-21swapper/520:17:035
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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