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2026-02-11 - 09:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Wed Feb 11, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2416250993810,1cyclictest0-21swapper/523:01:015
2416250993800,379cyclictest0-21swapper/523:42:025
2416250993800,379cyclictest0-21swapper/523:38:015
2416250993800,379cyclictest0-21swapper/520:45:025
2416250993800,379cyclictest0-21swapper/520:45:015
2416250993800,379cyclictest0-21swapper/519:15:025
2416250993800,379cyclictest0-21swapper/500:31:025
2416250993800,1cyclictest0-21swapper/522:52:025
2416250993800,1cyclictest0-21swapper/521:45:015
2416218993800,380cyclictest0-21swapper/122:20:021
241625099379378,1cyclictest2471202-21kworker/5:120:53:025
2416250993790,1cyclictest0-21swapper/521:19:025
2416250993790,1cyclictest0-21swapper/521:12:015
2416250993790,0cyclictest0-21swapper/521:43:015
241626699378376,1cyclictest2582475-21kworker/7:123:48:027
241625099378376,1cyclictest0-21swapper/520:19:025
241625099378376,1cyclictest0-21swapper/520:06:015
241625099378376,1cyclictest0-21swapper/519:43:015
241625099378376,1cyclictest0-21swapper/519:22:025
241625099378375,3cyclictest3212859-21kworker/5:019:49:025
241621899378377,1cyclictest0-21swapper/121:35:021
241621899378376,1cyclictest0-21swapper/100:20:011
241625099377376,1cyclictest2480222-21kworker/5:020:59:025
241625099377376,1cyclictest0-21swapper/521:01:015
241623399377375,1cyclictest0-21swapper/323:27:023
241623399377375,1cyclictest0-21swapper/323:27:023
241621899377375,1cyclictest0-21swapper/123:49:011
241621899377375,1cyclictest0-21swapper/123:08:021
241621899377375,1cyclictest0-21swapper/121:32:021
241621899377375,1cyclictest0-21swapper/100:03:021
241625099376375,1cyclictest2471202-21kworker/5:120:41:015
241625099376375,1cyclictest0-21swapper/520:26:025
241621899376375,1cyclictest2696236-21kworker/1:200:05:021
241621899376374,2cyclictest0-21swapper/122:50:011
241625099375374,1cyclictest0-21swapper/519:11:015
241621899375374,1cyclictest2654087-21kworker/1:123:41:021
241621899375374,1cyclictest0-21swapper/122:19:021
241621899375374,1cyclictest0-21swapper/121:21:021
241621899374373,1cyclictest2696236-21kworker/1:200:35:021
241621899374373,1cyclictest2407076-21kworker/1:219:33:021
241621899374373,1cyclictest0-21swapper/119:45:021
241621899374372,1cyclictest2654087-21kworker/1:123:50:011
241621899373372,1cyclictest2696236-21kworker/1:200:16:011
241621899373371,2cyclictest2510186-21kworker/1:122:39:021
241621899373371,1cyclictest0-21swapper/121:15:021
241621899373370,2cyclictest2510186-21kworker/1:121:41:021
241621899372371,1cyclictest2510186-21kworker/1:122:28:011
241621899372370,1cyclictest0-21swapper/121:54:021
241621899371370,1cyclictest2510186-21kworker/1:122:45:011
241621899370369,1cyclictest2510186-21kworker/1:123:13:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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