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2026-03-02 - 17:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Mon Mar 02, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1217893993830,382cyclictest0-21swapper/608:48:026
1217893993820,381cyclictest0-21swapper/612:05:026
1217893993820,381cyclictest0-21swapper/611:13:026
1217893993820,381cyclictest0-21swapper/609:24:026
1217893993820,1cyclictest0-21swapper/608:04:026
1217893993810,380cyclictest0-21swapper/608:56:026
1217893993810,2cyclictest0-21swapper/612:12:026
1217893993810,2cyclictest0-21swapper/609:37:036
121789399380379,1cyclictest0-21swapper/610:50:026
121785399380379,1cyclictest1251797-21kworker/1:208:05:021
121789399379378,1cyclictest1205704-21kworker/6:008:32:036
121789399379377,1cyclictest1299924-21kworker/6:210:33:026
121785399379377,1cyclictest1251797-21kworker/1:208:20:021
121789399378377,1cyclictest1384194-21kworker/6:012:00:026
121789399378377,1cyclictest1299924-21kworker/6:211:40:036
121789399378377,1cyclictest1205704-21kworker/6:009:00:026
121789399378377,1cyclictest1205704-21kworker/6:007:38:026
121789399378376,1cyclictest1299924-21kworker/6:209:40:036
121789399377376,1cyclictest1299924-21kworker/6:209:58:036
121789399377376,1cyclictest1299924-21kworker/6:209:58:026
121789399377376,1cyclictest1205704-21kworker/6:009:10:026
121789399377376,1cyclictest0-21swapper/610:14:026
121789399377375,1cyclictest1299924-21kworker/6:211:08:026
121789399377375,1cyclictest1205704-21kworker/6:007:44:036
121785399377376,1cyclictest1251797-21kworker/1:210:21:031
121789399376375,1cyclictest1205704-21kworker/6:009:28:026
121789399376375,1cyclictest0-21swapper/611:04:026
121789399376374,1cyclictest1384194-21kworker/6:012:24:026
121789399376374,1cyclictest1299924-21kworker/6:211:24:026
121789399376374,1cyclictest1205704-21kworker/6:007:14:026
121789399376373,2cyclictest0-21swapper/610:02:026
121785399376375,1cyclictest1363123-21kworker/1:111:28:031
121785399376375,1cyclictest1363123-21kworker/1:111:28:031
121785399376375,1cyclictest1251797-21kworker/1:208:46:031
121785399376375,1cyclictest1251797-21kworker/1:208:28:021
121785399376375,1cyclictest1251797-21kworker/1:208:28:021
121789399375374,1cyclictest1384194-21kworker/6:012:34:026
121789399375374,1cyclictest1299924-21kworker/6:210:48:036
121789399375374,1cyclictest1205704-21kworker/6:008:52:026
121789399375374,1cyclictest1205704-21kworker/6:007:52:036
121789399375374,1cyclictest0-21swapper/611:36:036
121789399375374,1cyclictest0-21swapper/611:32:036
121789399375374,1cyclictest0-21swapper/609:46:036
121789399375374,1cyclictest0-21swapper/609:16:026
121789399375373,1cyclictest1205704-21kworker/6:007:58:036
121785399375374,1cyclictest1511057-21kworker/1:007:47:031
121785399375374,1cyclictest1511057-21kworker/1:007:37:021
121785399375374,1cyclictest1251797-21kworker/1:209:21:021
121785399375374,1cyclictest1251797-21kworker/1:208:12:021
121789399374373,1cyclictest0-21swapper/611:54:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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