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2026-02-23 - 02:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun Feb 22, 2026 12:48:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912950,286ptp4l0-21swapper/107:07:491
248379916021,82cyclictest0-21swapper/2210:50:2315
247529915544,110cyclictest0-21swapper/207:27:3012
24868991490,88cyclictest0-21swapper/2911:21:1522
24832991486,127cyclictest16732-21taskset07:25:2614
247809914722,91cyclictest0-21swapper/910:56:3531
247529914546,98cyclictest0-21swapper/207:40:2012
247769914417,115cyclictest0-21swapper/811:49:3230
247429914343,62cyclictest0-21swapper/010:23:060
24868991410,85cyclictest0-21swapper/2910:41:5722
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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