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2026-02-02 - 01:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun Feb 01, 2026 12:48:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912380,230ptp4l0-21swapper/107:06:021
45562214206,6sleep240-21swapper/2407:08:0317
60099919337,98cyclictest151rcu_preempt12:20:009
6033991837,130cyclictest0-21swapper/2109:26:2214
6033991797,127cyclictest0-21swapper/2109:50:0114
60279917433,108cyclictest0-21swapper/2009:10:2313
60389917358,114cyclictest0-21swapper/2212:15:0115
60469917014,146cyclictest0-21swapper/2411:48:0817
60519916931,137cyclictest0-21swapper/2509:51:1818
60519916931,132cyclictest0-21swapper/2511:14:5618
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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