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2026-05-10 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun May 10, 2026 00:49:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912590,251ptp4l0-21swapper/119:08:091
170782252242,8sleep240-21swapper/2419:05:1417
330891230222,6phc2sys0-21swapper/219:08:2512
2153899227131,4cyclictest151rcu_preempt00:09:4727
21523991605,99cyclictest0-21swapper/322:43:2323
21523991605,153cyclictest0-21swapper/321:48:3923
21523991605,153cyclictest0-21swapper/321:48:3923
21523991595,116cyclictest0-21swapper/322:26:3523
21523991595,116cyclictest0-21swapper/322:04:5423
21523991595,116cyclictest0-21swapper/322:04:5423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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