You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-24 - 23:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Jan 24, 2026 12:48:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2323999353154,2cyclictest151rcu_preempt11:34:144
2323999353154,2cyclictest151rcu_preempt11:34:144
3273913070,299ptp4l0-21swapper/107:08:401
330891200191,6phc2sys0-21swapper/207:05:1812
2320999196196,0cyclictest151rcu_preempt10:06:1530
201902180172,6sleep80-21swapper/807:05:1930
232099917228,109cyclictest0-21swapper/812:30:0030
232559917028,97cyclictest0-21swapper/1511:58:347
218982159150,6sleep270-21swapper/2707:09:2320
232099915562,92cyclictest64-21ksoftirqd/811:11:4130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional