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2026-05-09 - 15:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat May 09, 2026 12:49:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2641799319121,1cyclictest151rcu_preempt12:15:1116
263459920912,1cyclictest151rcu_preempt09:39:5930
264239918510,174cyclictest0-21swapper/2412:25:1317
264239918310,122cyclictest0-21swapper/2412:31:0617
264239917710,111cyclictest0-21swapper/2409:29:1717
26423991659,127cyclictest0-21swapper/2407:55:1717
26376991626,155cyclictest0-21swapper/1310:53:145
26376991626,155cyclictest0-21swapper/1310:53:145
26376991625,141cyclictest0-21swapper/1310:02:285
26376991625,119cyclictest0-21swapper/1311:18:225
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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