You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-06-29 - 00:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Jun 28, 2025 12:49:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482912340,226ptp4l0-21swapper/107:09:241
37729917924,131cyclictest0-21swapper/2009:14:2013
3843991788,83cyclictest0-21swapper/2911:29:4022
38219917532,86cyclictest0-21swapper/2610:32:5919
38219917532,86cyclictest0-21swapper/2610:32:5819
37119916855,70cyclictest0-21swapper/911:55:0031
38219916726,114cyclictest0-21swapper/2609:01:5819
38369916619,108cyclictest151rcu_preempt11:22:3021
37729916624,100cyclictest0-21swapper/2010:50:1913
37729916525,84cyclictest0-21swapper/2012:05:3913
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional