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2026-03-20 - 14:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Fri Mar 20, 2026 00:49:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913190,311ptp4l0-21swapper/119:05:471
219779928790,1cyclictest1901rcuc/2922:46:3322
219779928790,1cyclictest1901rcuc/2922:46:3322
218669928082,1cyclictest151rcu_preempt22:56:0730
218579922225,1cyclictest151rcu_preempt22:00:1129
218579922225,1cyclictest151rcu_preempt22:00:1129
204922219212,6sleep250-21swapper/2519:07:3818
218409921227,99cyclictest0-21swapper/422:45:2326
218409921227,99cyclictest0-21swapper/422:45:2226
219469920714,135cyclictest0-21swapper/2121:48:4014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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