You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-19 - 17:15
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Nov 19, 2025 12:49:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1730899302105,30cyclictest151rcu_preempt11:55:2415
1730899301105,34cyclictest151rcu_preempt12:13:3415
1730899301104,1cyclictest151rcu_preempt09:16:4115
1730899301104,1cyclictest151rcu_preempt09:16:4115
2482912600,252ptp4l0-21swapper/107:09:351
329891186177,6phc2sys0-21swapper/207:05:2812
172819918225,125cyclictest0-21swapper/1710:52:479
172119918259,57cyclictest151rcu_preempt10:21:0428
172819917924,111cyclictest0-21swapper/1710:00:259
172819917924,111cyclictest0-21swapper/1710:00:259
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional