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2026-06-28 - 07:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun Jun 28, 2026 00:49:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912730,265ptp4l0-21swapper/119:08:041
294299917860,117cyclictest0-21swapper/2723:46:3520
292939916738,120cyclictest0-21swapper/023:25:030
330891166157,6phc2sys0-21swapper/219:05:2012
292939916637,94cyclictest0-21swapper/021:55:000
293089916523,93cyclictest0-21swapper/323:14:5223
292939916434,74cyclictest0-21swapper/022:15:500
292939916133,79cyclictest0-21swapper/022:21:580
292939916131,77cyclictest0-21swapper/023:05:000
292939915929,98cyclictest0-21swapper/000:35:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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