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2026-02-03 - 02:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Mon Feb 02, 2026 12:48:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913270,319ptp4l0-21swapper/107:09:281
189639921554,20cyclictest179-21ksoftirqd/2712:12:5320
18963991545,96cyclictest0-21swapper/2712:15:5120
18912991470,87cyclictest0-21swapper/1509:11:297
18932991440,86cyclictest0-21swapper/2008:15:1713
18932991440,86cyclictest0-21swapper/2008:15:1713
188769914347,58cyclictest0-21swapper/807:29:5530
188769914347,58cyclictest0-21swapper/807:29:5530
18932991411,80cyclictest0-21swapper/2007:35:0213
18932991411,80cyclictest0-21swapper/2007:35:0213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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