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2025-12-15 - 16:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Mon Dec 15, 2025 12:47:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287662294286,6sleep280-21swapper/2807:05:1121
330891190181,7phc2sys0-21swapper/207:05:1612
13629918524,71cyclictest151rcu_preempt09:05:1628
13629918524,71cyclictest151rcu_preempt09:05:1628
14089913723,66cyclictest0-21swapper/1207:30:224
1528991347,125cyclictest0-21swapper/2908:20:1722
1528991347,125cyclictest0-21swapper/2908:20:1722
14169913227,70cyclictest0-21swapper/1408:05:036
14169913223,64cyclictest0-21swapper/1410:13:486
14169913146,53cyclictest0-21swapper/1412:06:006
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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