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2026-05-16 - 16:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat May 16, 2026 12:49:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912790,271ptp4l0-21swapper/107:05:121
330891240232,6phc2sys0-21swapper/207:06:1212
1054699201142,1cyclictest151rcu_preempt10:40:2430
10611991713,121cyclictest0-21swapper/1710:48:599
106809916624,19cyclictest0-21swapper/2712:03:2720
106809916324,137cyclictest0-21swapper/2708:15:1420
105609916016,111cyclictest0-21swapper/1012:07:422
106809914919,126cyclictest151rcu_preempt12:30:1120
10680991477,121cyclictest151rcu_preempt10:07:2920
10680991477,121cyclictest151rcu_preempt10:07:2820
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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