You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-10 - 07:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Tue Feb 10, 2026 00:48:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
208049929799,1cyclictest151rcu_preempt22:39:5822
3273912810,274ptp4l0-21swapper/119:08:521
20801991819,113cyclictest0-21swapper/2800:21:4621
20801991809,108cyclictest0-21swapper/2822:10:3021
20801991734,125cyclictest0-21swapper/2821:15:1621
207739917313,140cyclictest0-21swapper/2121:15:2414
207739917313,109cyclictest0-21swapper/2120:25:0614
207739917313,109cyclictest0-21swapper/2120:25:0514
207739917213,121cyclictest0-21swapper/2119:35:2914
207739917213,121cyclictest0-21swapper/2119:35:2814
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional