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2026-05-28 - 21:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu May 28, 2026 12:49:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913130,306ptp4l0-21swapper/107:05:521
178689924043,3cyclictest151rcu_preempt09:47:4625
330891219211,6phc2sys0-21swapper/207:08:5912
177509918043,88cyclictest0-21swapper/610:40:1628
177509916630,93cyclictest0-21swapper/609:55:2228
1781499163118,0cyclictest0-21swapper/2110:02:5014
177899915734,18cyclictest0-21swapper/1409:05:516
177509915719,113cyclictest0-21swapper/610:55:1528
177899915429,92cyclictest0-21swapper/1409:40:186
177929915322,119cyclictest0-21swapper/1507:15:127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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