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2026-02-18 - 22:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Feb 18, 2026 12:49:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912750,261ptp4l0-21swapper/107:05:151
330891198190,6phc2sys0-21swapper/207:07:3912
88529917714,135cyclictest0-21swapper/1811:30:1510
88769916511,113cyclictest0-21swapper/2211:56:1515
8815991640,116cyclictest0-21swapper/1009:17:192
88769915511,107cyclictest0-21swapper/2212:20:1915
88529915117,28cyclictest0-21swapper/1811:05:2610
87889914910,135cyclictest151rcu_preempt09:40:4323
88769914711,84cyclictest0-21swapper/2210:07:4515
8907991450,84cyclictest0-21swapper/3011:36:0524
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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