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2026-08-04 - 20:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Tue Aug 04, 2026 12:48:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2319399357158,2cyclictest151rcu_preempt11:52:500
2319399357158,2cyclictest151rcu_preempt11:52:500
2333499355157,1cyclictest151rcu_preempt10:45:1417
2334199299102,3cyclictest151rcu_preempt11:37:1818
3273912270,217ptp4l0-21swapper/107:05:211
219032166159,6sleep120-21swapper/1207:08:014
232719916420,123cyclictest0-21swapper/1311:01:185
232719916320,92cyclictest0-21swapper/1312:17:115
232719916320,103cyclictest0-21swapper/1312:38:025
232719916319,108cyclictest0-21swapper/1312:32:095
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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