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2026-07-07 - 12:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Tue Jul 07, 2026 00:49:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912840,275ptp4l0-21swapper/119:06:351
270282266259,6sleep290-21swapper/2919:06:0022
330891256244,9phc2sys0-21swapper/219:05:0812
286539920226,3cyclictest151rcu_preempt23:10:5111
286749918813,121cyclictest0-21swapper/2221:14:5515
286749918813,121cyclictest0-21swapper/2221:14:5515
285259917316,153cyclictest0-21swapper/322:01:0623
287289917224,136cyclictest0-21swapper/2923:13:2922
285259917216,111cyclictest0-21swapper/323:32:2923
285259917216,111cyclictest0-21swapper/323:32:2823
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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