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2026-03-02 - 05:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Mon Mar 02, 2026 00:49:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26885991993,179cyclictest151rcu_preempt21:45:0028
26885991993,179cyclictest151rcu_preempt21:44:5928
330891182174,6phc2sys0-21swapper/219:05:2312
3273911790,170ptp4l0-21swapper/119:07:161
269269917611,136cyclictest0-21swapper/1521:55:507
269269917611,136cyclictest0-21swapper/1521:55:507
269269917511,128cyclictest0-21swapper/1523:10:087
269269916411,110cyclictest0-21swapper/1522:33:167
269269916411,110cyclictest0-21swapper/1522:33:157
139821610,1sleep00-21swapper/019:15:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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