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2026-02-06 - 04:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu Feb 05, 2026 00:48:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913050,297ptp4l0-21swapper/119:09:251
330891179171,6phc2sys0-21swapper/219:06:4012
297399916333,94cyclictest0-21swapper/1200:11:394
298109916011,72cyclictest276811smart_sda19:30:2317
297399915828,90cyclictest0-21swapper/1221:47:164
297399915828,90cyclictest0-21swapper/1221:47:154
296729915845,95cyclictest0-21swapper/323:00:0123
297399914823,82cyclictest0-21swapper/1223:10:224
29838991468,128cyclictest151rcu_preempt19:20:1725
29835991440,85cyclictest0-21swapper/3020:55:1024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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