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2026-06-25 - 06:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu Jun 25, 2026 00:49:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
135309926466,2cyclictest151rcu_preempt21:11:117
3273912220,208ptp4l0-21swapper/119:05:171
3273912220,208ptp4l0-21swapper/119:05:171
135649922223,196cyclictest151rcu_preempt19:25:1813
135649922223,196cyclictest151rcu_preempt19:25:1813
134709917425,148cyclictest0-21swapper/421:54:0526
134709916925,84cyclictest0-21swapper/400:30:3626
134709916925,84cyclictest0-21swapper/400:30:3626
330891165157,6phc2sys0-21swapper/219:07:2112
330891165157,6phc2sys0-21swapper/219:07:2112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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