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2026-02-15 - 21:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun Feb 15, 2026 12:48:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891190182,6phc2sys0-21swapper/207:06:1312
4494991870,162cyclictest0-21swapper/309:10:5123
4494991801,140cyclictest0-21swapper/310:16:5123
4494991751,131cyclictest0-21swapper/312:00:1923
46189916611,99cyclictest0-21swapper/2809:34:3721
4626991624,157cyclictest0-21swapper/2912:10:2322
4494991613,128cyclictest0-21swapper/310:45:1423
4626991604,124cyclictest0-21swapper/2910:03:1122
46189915511,107cyclictest0-21swapper/2809:45:1621
4494991530,55cyclictest0-21swapper/312:26:3023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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