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2026-08-09 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun Aug 09, 2026 00:49:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
403599302105,1cyclictest151rcu_preempt00:04:403
4077991700,35cyclictest0-21swapper/1621:41:518
4077991700,35cyclictest0-21swapper/1621:41:518
40779916822,118cyclictest0-21swapper/1600:09:348
41439916628,94cyclictest0-21swapper/2621:29:2419
41439916628,94cyclictest0-21swapper/2621:29:2319
41439916528,87cyclictest0-21swapper/2622:45:1719
3273911640,156ptp4l0-21swapper/119:07:331
41439916316,123cyclictest151rcu_preempt22:35:2519
40449916032,95cyclictest0-21swapper/1223:05:164
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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