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2026-03-25 - 20:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Mar 25, 2026 12:49:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912780,270ptp4l0-21swapper/107:05:471
158569926970,198cyclictest151rcu_preempt12:30:0213
15914991860,185cyclictest0-21swapper/3109:55:5625
159089915932,71cyclictest0-21swapper/3011:30:4824
159089915819,103cyclictest0-21swapper/3008:35:1324
157809915530,67cyclictest0-21swapper/309:52:1623
15914991496,86cyclictest0-21swapper/3111:57:1525
15914991496,86cyclictest0-21swapper/3111:57:1425
330891147138,7phc2sys0-21swapper/207:05:0212
159089914632,83cyclictest0-21swapper/3007:38:5324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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