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2026-05-12 - 16:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Tue May 12, 2026 12:49:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3038399296107,1cyclictest151rcu_preempt12:29:2417
3273912390,231ptp4l0-21swapper/107:09:581
303159922830,1cyclictest151rcu_preempt10:55:222
303159922830,1cyclictest151rcu_preempt10:55:222
303979917038,127cyclictest0-21swapper/2611:27:0519
3035199170168,1cyclictest151rcu_preempt09:50:1210
303979916533,131cyclictest0-21swapper/2609:30:0319
303979916126,43cyclictest0-21swapper/2612:25:2119
303979915826,110cyclictest0-21swapper/2608:35:0019
303519915733,71cyclictest0-21swapper/1812:08:2310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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