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2026-01-21 - 22:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Jan 21, 2026 12:48:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913260,318ptp4l0-21swapper/107:08:371
183042152145,6sleep80-21swapper/807:09:4130
19696991391,87cyclictest0-21swapper/2911:27:5222
195469913853,55cyclictest0-21swapper/809:15:4830
195469913853,55cyclictest0-21swapper/809:15:4830
170712138129,7sleep90-21swapper/907:05:2531
19553991360,88cyclictest0-21swapper/907:30:1531
196809913528,69cyclictest0-21swapper/2712:21:5020
196149913513,83cyclictest0-21swapper/1810:39:0310
19571991356,128cyclictest0-21swapper/1210:22:544
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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