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2026-01-29 - 01:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Jan 28, 2026 12:48:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273914240,415ptp4l0-21swapper/107:05:131
3273914240,415ptp4l0-21swapper/107:05:131
1306399308110,1cyclictest151rcu_preempt09:30:4221
330891260252,6phc2sys0-21swapper/207:06:5912
330891260252,6phc2sys0-21swapper/207:06:5912
130439924440,197cyclictest0-21swapper/2512:25:2218
130439924440,197cyclictest0-21swapper/2512:25:2218
130009916324,115cyclictest0-21swapper/1709:22:269
129329915522,80cyclictest0-21swapper/211:20:5012
129929915433,108cyclictest0-21swapper/1511:57:567
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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