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2026-07-10 - 12:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Fri Jul 10, 2026 00:49:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912890,282ptp4l0-21swapper/119:09:141
330891213204,6phc2sys0-21swapper/219:05:1612
301339921358,56cyclictest151rcu_preempt21:17:5510
301339921358,56cyclictest151rcu_preempt21:17:5410
302349914826,25cyclictest0-21swapper/3021:13:3224
302349914826,25cyclictest0-21swapper/3021:13:3124
302349914725,120cyclictest0-21swapper/3000:20:5824
302349914525,119cyclictest0-21swapper/3022:44:2224
302349914426,90cyclictest0-21swapper/3021:59:2824
302349914426,90cyclictest0-21swapper/3021:59:2824
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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