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2026-03-18 - 18:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Mar 18, 2026 12:49:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913010,293ptp4l0-21swapper/107:09:121
191059925257,3cyclictest151rcu_preempt09:37:1717
330891222214,6phc2sys0-21swapper/207:09:5812
19095991651,143cyclictest0-21swapper/2311:05:5616
191279916028,131cyclictest0-21swapper/2911:09:1522
191279915928,93cyclictest0-21swapper/2911:50:5722
191279915928,93cyclictest0-21swapper/2911:50:5722
191279915928,130cyclictest0-21swapper/2909:46:2422
191279915827,109cyclictest0-21swapper/2912:16:2222
191279915827,109cyclictest0-21swapper/2912:16:2222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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