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2026-02-07 - 05:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Feb 07, 2026 00:48:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
687399340135,9cyclictest88-21ksoftirqd/1221:26:564
3273912910,283ptp4l0-21swapper/119:06:101
3273912910,283ptp4l0-21swapper/119:06:101
68739925124,157cyclictest0-21swapper/1220:15:004
330891192183,6phc2sys0-21swapper/219:05:2312
330891192183,6phc2sys0-21swapper/219:05:2312
69479917832,144cyclictest0-21swapper/2300:04:5616
68739917824,114cyclictest0-21swapper/1221:39:434
69479917430,99cyclictest0-21swapper/2321:37:1916
69479917430,102cyclictest0-21swapper/2322:00:2516
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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