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2026-01-14 - 20:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Jan 14, 2026 12:48:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48729929015,266cyclictest0-21swapper/109:20:201
3273912670,259ptp4l0-21swapper/107:09:021
330891224216,6phc2sys0-21swapper/207:08:3512
5070991731,140cyclictest151rcu_preempt10:45:4821
5070991731,140cyclictest151rcu_preempt10:45:4821
4979991717,135cyclictest0-21swapper/1611:00:138
4979991717,135cyclictest0-21swapper/1611:00:138
4979991697,121cyclictest0-21swapper/1609:32:198
4973991532,18cyclictest0-21swapper/1511:10:507
4973991532,18cyclictest0-21swapper/1511:10:507
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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