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2025-12-16 - 15:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Tue Dec 16, 2025 12:48:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31025991880,174cyclictest151rcu_preempt10:26:129
31025991880,174cyclictest151rcu_preempt10:26:129
310119917322,102cyclictest0-21swapper/1408:15:166
31025991480,103cyclictest151rcu_preempt10:06:259
310119914519,101cyclictest0-21swapper/1410:40:206
310119914519,101cyclictest0-21swapper/1410:40:196
309509914430,68cyclictest0-21swapper/510:45:1427
309509914430,68cyclictest0-21swapper/510:45:1327
31025991410,83cyclictest0-21swapper/1707:50:119
310009914115,91cyclictest12799-21taskset11:36:555
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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