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2025-12-06 - 23:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Dec 06, 2025 12:49:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482912310,223ptp4l0-21swapper/107:07:011
2482912310,223ptp4l0-21swapper/107:07:011
30893991530,105cyclictest10341-21missed_timers09:45:1916
308939914433,108cyclictest28918-21switchtime07:30:2416
30880991436,116cyclictest151rcu_preempt11:26:0714
30880991436,116cyclictest151rcu_preempt11:26:0614
308029914253,55cyclictest0-21swapper/912:10:1631
308029914253,55cyclictest0-21swapper/912:10:1531
308939914053,65cyclictest0-21swapper/2309:52:5016
308029914053,58cyclictest0-21swapper/910:15:3431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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