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2026-02-11 - 08:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Feb 11, 2026 00:48:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912970,289ptp4l0-21swapper/119:08:051
90369918846,115cyclictest0-21swapper/022:03:550
90369918846,115cyclictest0-21swapper/022:03:550
90559917812,144cyclictest151rcu_preempt21:21:5026
90559917358,77cyclictest151rcu_preempt22:50:3326
90559917358,77cyclictest151rcu_preempt22:50:3326
9110991722,140cyclictest0-21swapper/1823:49:4610
90369917129,106cyclictest0-21swapper/023:37:570
90369917026,143cyclictest0-21swapper/021:40:160
90369917022,145cyclictest0-21swapper/021:14:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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