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2026-06-10 - 00:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Tue Jun 09, 2026 12:49:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891290283,6phc2sys0-21swapper/207:06:4812
3273912740,265ptp4l0-21swapper/107:05:251
120339925155,1cyclictest151rcu_preempt10:44:5010
120339925155,1cyclictest151rcu_preempt10:44:5010
121149917167,103cyclictest185-21ksoftirqd/2809:35:1821
11964991609,148cyclictest151rcu_preempt09:52:3830
119649916020,79cyclictest151rcu_preempt09:59:0430
119649915411,142cyclictest151rcu_preempt09:44:3830
119649915411,142cyclictest151rcu_preempt09:44:3730
11959991470,88cyclictest0-21swapper/710:04:0429
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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