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2026-08-16 - 02:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Aug 15, 2026 12:49:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1646299316118,1cyclictest151rcu_preempt11:40:3214
330891273265,6phc2sys0-21swapper/207:06:3412
3273912480,240ptp4l0-21swapper/107:07:531
163669920622,3cyclictest151rcu_preempt11:38:220
164379917230,141cyclictest0-21swapper/1609:40:008
164379917229,142cyclictest0-21swapper/1612:22:388
164379917127,143cyclictest0-21swapper/1610:51:368
164379917127,143cyclictest0-21swapper/1610:51:368
164379916826,107cyclictest0-21swapper/1609:51:298
164379916726,96cyclictest0-21swapper/1611:20:138
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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