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2025-12-30 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Mon Dec 29, 2025 12:48:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891250243,6phc2sys0-21swapper/207:08:0612
255829919330,92cyclictest0-21swapper/2111:54:0014
2547399161123,23cyclictest141rcuc/012:39:250
255829915211,119cyclictest151rcu_preempt07:23:3214
255419914845,89cyclictest0-21swapper/1112:25:223
255829914555,23cyclictest0-21swapper/2109:13:0814
255829914555,23cyclictest0-21swapper/2109:13:0814
256169914235,61cyclictest0-21swapper/2812:00:5421
25616991410,117cyclictest0-21swapper/2809:11:5921
25616991410,117cyclictest0-21swapper/2809:11:5921
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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