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2025-12-25 - 17:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu Dec 25, 2025 12:47:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190672304296,6sleep270-21swapper/2707:08:5520
330891221213,6phc2sys0-21swapper/207:06:4612
203689921332,109cyclictest0-21swapper/508:25:1227
204759918224,106cyclictest0-21swapper/2207:19:0715
177352170162,6sleep50-21swapper/507:05:2027
205109916730,120cyclictest0-21swapper/3008:45:2224
20475991470,85cyclictest0-21swapper/2209:35:2815
20448991440,85cyclictest0-21swapper/1608:40:378
204759914332,103cyclictest0-21swapper/2211:48:5715
204759914332,103cyclictest0-21swapper/2211:48:5615
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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