You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-12 - 11:26
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu Mar 12, 2026 00:49:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913150,307ptp4l0-21swapper/119:09:591
124659929294,1cyclictest151rcu_preempt00:39:1813
124959926266,3cyclictest151rcu_preempt00:23:5220
123699922225,3cyclictest151rcu_preempt23:36:430
1239499209117,56cyclictest0-21swapper/422:03:1526
110842185178,6sleep00-21swapper/019:08:240
124469917523,152cyclictest0-21swapper/1600:19:568
124469917523,152cyclictest0-21swapper/1600:03:108
124469917523,124cyclictest0-21swapper/1622:58:108
124469917423,109cyclictest0-21swapper/1623:25:178
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional