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2026-02-19 - 22:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu Feb 19, 2026 12:49:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
519999340142,18cyclictest151rcu_preempt12:10:0618
3273913270,312ptp4l0-21swapper/107:05:171
51259932324,122cyclictest151rcu_preempt11:03:116
51259932324,122cyclictest151rcu_preempt11:03:116
51079927779,1cyclictest151rcu_preempt11:30:134
330891184175,6phc2sys0-21swapper/207:05:1312
50259917523,151cyclictest0-21swapper/011:17:260
50259917424,95cyclictest0-21swapper/011:43:530
50259917024,27cyclictest0-21swapper/007:10:170
50259917023,146cyclictest0-21swapper/009:52:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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