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2026-07-31 - 18:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Fri Jul 31, 2026 12:49:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913050,293ptp4l0-21swapper/107:05:221
24235991974,1cyclictest151rcu_preempt10:01:3114
241359919323,131cyclictest0-21swapper/310:50:2323
242559918839,39cyclictest151rcu_preempt08:22:1219
242559918839,39cyclictest151rcu_preempt08:22:1219
2417899174173,1cyclictest151rcu_preempt12:28:545
241739917453,68cyclictest151rcu_preempt09:16:504
241629917025,57cyclictest151rcu_preempt11:40:2231
2412499167165,1cyclictest151rcu_preempt10:59:271
241359916646,75cyclictest0-21swapper/312:05:1323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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