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2026-01-30 - 01:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Thu Jan 29, 2026 12:48:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
259812197188,7sleep150-21swapper/1507:05:207
3273911950,181ptp4l0-21swapper/107:10:001
286429918453,130cyclictest0-21swapper/2009:45:1713
286039917515,102cyclictest0-21swapper/1110:15:143
286619917129,104cyclictest0-21swapper/2311:30:1616
286379917014,121cyclictest0-21swapper/1911:20:1911
286429916129,98cyclictest0-21swapper/2011:54:1213
28627991565,150cyclictest0-21swapper/1711:02:219
28627991565,146cyclictest0-21swapper/1711:45:079
28627991545,91cyclictest0-21swapper/1710:49:319
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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