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2026-02-11 - 20:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Feb 11, 2026 12:48:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891286278,6phc2sys0-21swapper/207:05:5312
136839925456,1cyclictest151rcu_preempt12:06:501
3273912160,197ptp4l0-21swapper/107:05:131
136889917629,103cyclictest0-21swapper/210:46:4112
13818991721,169cyclictest151rcu_preempt07:38:2619
13688991680,30cyclictest0-21swapper/212:00:2612
137589916567,33cyclictest151rcu_preempt12:25:125
13835991635,149cyclictest0-21swapper/3009:50:1824
13835991614,120cyclictest0-21swapper/3011:42:4224
136789915915,114cyclictest0-21swapper/008:43:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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