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2026-05-01 - 11:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Fri May 01, 2026 00:49:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891387378,6phc2sys0-21swapper/219:05:1312
3273912530,245ptp4l0-21swapper/119:09:121
126269922119,199cyclictest151rcu_preempt23:44:098
127519920145,1cyclictest151rcu_preempt00:32:4125
12551991876,165cyclictest0-21swapper/421:12:0926
12600991814,128cyclictest0-21swapper/1320:50:215
12600991804,146cyclictest0-21swapper/1321:50:245
12600991804,138cyclictest0-21swapper/1322:22:315
12551991741,168cyclictest0-21swapper/423:51:5726
12551991741,168cyclictest0-21swapper/423:51:5726
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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