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2026-01-26 - 01:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sun Jan 25, 2026 12:47:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913000,292ptp4l0-21swapper/107:08:041
3273913000,292ptp4l0-21swapper/107:08:041
151279924548,2cyclictest151rcu_preempt12:20:1826
152199916344,71cyclictest0-21swapper/2511:48:3218
151759916342,119cyclictest0-21swapper/1411:25:236
330891158150,6phc2sys0-21swapper/207:06:4912
330891158150,6phc2sys0-21swapper/207:06:4912
151989915333,14cyclictest0-21swapper/2009:42:0713
151759915332,120cyclictest0-21swapper/1411:32:516
15205991521,143cyclictest0-21swapper/2211:10:0115
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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