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2026-07-25 - 17:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Jul 25, 2026 12:49:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
506599325137,1cyclictest151rcu_preempt11:38:2612
3273913000,292ptp4l0-21swapper/107:05:441
50789926970,198cyclictest151rcu_preempt10:28:2727
51149918030,29cyclictest0-21swapper/1410:05:056
51589917133,137cyclictest0-21swapper/2408:20:2817
51589917133,137cyclictest0-21swapper/2408:20:2817
51149916730,81cyclictest0-21swapper/1411:22:036
51589916631,106cyclictest0-21swapper/2409:30:2117
51149916430,81cyclictest0-21swapper/1411:06:026
51709915738,114cyclictest0-21swapper/2711:05:1120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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