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2026-03-23 - 05:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Mon Mar 23, 2026 00:49:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181019927073,1cyclictest151rcu_preempt23:49:024
330891239230,6phc2sys0-21swapper/219:05:1912
3273912270,219ptp4l0-21swapper/119:07:421
18132991776,156cyclictest0-21swapper/2023:50:1413
181289917527,140cyclictest0-21swapper/1923:25:1811
18165991709,148cyclictest151rcu_preempt21:46:3319
18165991709,148cyclictest151rcu_preempt21:46:3319
181289916627,92cyclictest0-21swapper/1921:35:1511
181239916531,122cyclictest0-21swapper/1823:52:0010
181429916415,113cyclictest151rcu_preempt19:15:1515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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