You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-28 - 06:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Fri Aug 28, 2026 00:49:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2349799342145,1cyclictest151rcu_preempt21:30:2018
234389927678,1cyclictest151rcu_preempt21:31:364
235189916517,147cyclictest0-21swapper/3021:55:3824
235189916517,127cyclictest0-21swapper/3021:37:2824
235189916217,137cyclictest0-21swapper/3022:17:0124
235189915714,117cyclictest0-21swapper/3000:24:4424
235189915714,117cyclictest0-21swapper/3000:24:4424
235189915617,99cyclictest0-21swapper/3022:20:1424
235139915312,139cyclictest0-21swapper/2923:00:2122
235139915312,125cyclictest0-21swapper/2921:27:5022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional