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2026-02-01 - 07:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Sun Feb 01, 2026 00:48:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912910,283ptp4l0-21swapper/119:06:451
45679916517,132cyclictest0-21swapper/2122:23:0314
45679916517,132cyclictest0-21swapper/2122:23:0314
45679916417,108cyclictest0-21swapper/2122:09:0914
45679916417,108cyclictest0-21swapper/2122:09:0914
45679916417,107cyclictest0-21swapper/2100:15:1714
45679916217,99cyclictest0-21swapper/2123:05:1614
45719915821,92cyclictest0-21swapper/2220:30:1815
45679915417,96cyclictest0-21swapper/2121:18:3914
45159915373,20cyclictest16870-21kernelversion21:45:1830
45159915373,20cyclictest16870-21kernelversion21:45:1830
45719915219,99cyclictest0-21swapper/2221:38:0515
45679915117,102cyclictest0-21swapper/2122:25:1114
45679915117,102cyclictest0-21swapper/2122:25:1114
4465991511,102cyclictest0-21swapper/021:10:200
45679914917,96cyclictest0-21swapper/2119:59:1214
4515991460,85cyclictest0-21swapper/821:55:2330
4515991460,85cyclictest0-21swapper/821:55:2230
45719914418,95cyclictest0-21swapper/2200:36:0915
45719914219,90cyclictest0-21swapper/2200:30:1015
45719914117,70cyclictest0-21swapper/2223:23:4315
45319914129,69cyclictest0-21swapper/1222:30:264
45319914129,69cyclictest0-21swapper/1222:30:264
45679914017,80cyclictest0-21swapper/2121:25:5214
45319914046,65cyclictest0-21swapper/1220:20:264
45319914046,58cyclictest0-21swapper/1223:15:374
45319913928,68cyclictest0-21swapper/1222:01:544
45319913928,68cyclictest0-21swapper/1222:01:534
4531991390,84cyclictest0-21swapper/1221:02:484
45219913962,43cyclictest15718-21latency_hist21:25:0131
45219913962,43cyclictest15718-21latency_hist21:25:0031
4531991380,85cyclictest0-21swapper/1223:41:004
45319913736,62cyclictest0-21swapper/1221:30:194
4515991370,76cyclictest0-21swapper/820:30:1530
45719913621,60cyclictest0-21swapper/2221:42:5915
45719913621,60cyclictest0-21swapper/2221:42:5915
45319913653,67cyclictest0-21swapper/1221:17:474
45319913652,54cyclictest0-21swapper/1223:48:484
45319913648,53cyclictest0-21swapper/1221:46:554
45319913648,53cyclictest0-21swapper/1221:46:544
45319913628,73cyclictest0-21swapper/1220:15:204
45719913530,72cyclictest0-21swapper/2200:13:4315
45319913531,75cyclictest0-21swapper/1200:11:404
45319913529,71cyclictest0-21swapper/1223:50:224
45319913529,67cyclictest0-21swapper/1200:29:384
4507991350,83cyclictest0-21swapper/723:08:4629
45319913438,56cyclictest0-21swapper/1223:02:324
45319913438,56cyclictest0-21swapper/1223:02:314
45319913430,74cyclictest0-21swapper/1223:27:374
45319913430,74cyclictest0-21swapper/1222:16:014
45319913430,74cyclictest0-21swapper/1222:16:014
45319913426,63cyclictest0-21swapper/1223:30:194
45319913426,63cyclictest0-21swapper/1221:06:184
4475991340,89cyclictest0-21swapper/222:09:0412
4475991340,89cyclictest0-21swapper/222:09:0412
45319913331,70cyclictest0-21swapper/1221:21:164
45319913331,70cyclictest0-21swapper/1221:21:154
45319913330,71cyclictest0-21swapper/1222:07:054
45319913330,71cyclictest0-21swapper/1222:07:054
45319913329,68cyclictest0-21swapper/1222:14:094
45319913329,68cyclictest0-21swapper/1222:14:084
45319913328,67cyclictest0-21swapper/1221:54:554
45319913328,67cyclictest0-21swapper/1221:54:554
45319913327,61cyclictest0-21swapper/1222:40:524
45319913327,61cyclictest0-21swapper/1222:40:524
45219913347,57cyclictest0-21swapper/920:30:0531
45219913343,57cyclictest0-21swapper/922:11:3131
45219913343,57cyclictest0-21swapper/922:11:3131
45719913249,54cyclictest0-21swapper/2220:38:1815
45319913250,70cyclictest0-21swapper/1200:16:144
45319913243,62cyclictest0-21swapper/1219:24:484
45319913241,56cyclictest0-21swapper/1221:11:374
45319913229,72cyclictest0-21swapper/1200:22:574
45319913229,65cyclictest0-21swapper/1220:59:044
45319913228,70cyclictest0-21swapper/1221:58:394
45319913228,70cyclictest0-21swapper/1221:58:394
45319913228,65cyclictest0-21swapper/1200:38:274
4521991320,76cyclictest0-21swapper/919:10:1631
45159913246,57cyclictest0-21swapper/823:04:2330
45159913246,57cyclictest0-21swapper/823:04:2330
4599991310,81cyclictest0-21swapper/2923:00:2322
4599991310,81cyclictest0-21swapper/2923:00:2322
45879913124,76cyclictest3905-21taskset23:50:0019
45719913127,70cyclictest0-21swapper/2222:05:5815
45719913127,70cyclictest0-21swapper/2222:05:5815
45719913127,64cyclictest0-21swapper/2223:15:5815
45319913135,67cyclictest0-21swapper/1223:10:004
45319913133,75cyclictest0-21swapper/1223:10:024
45319913126,70cyclictest0-21swapper/1222:59:354
45319913126,70cyclictest0-21swapper/1222:59:344
45219913153,57cyclictest0-21swapper/922:46:5531
45219913153,57cyclictest0-21swapper/922:46:5431
45719913048,53cyclictest0-21swapper/2200:15:1915
45719913042,57cyclictest0-21swapper/2219:33:0815
45679913017,74cyclictest0-21swapper/2122:12:4014
45679913017,74cyclictest0-21swapper/2122:12:4014
45319913029,64cyclictest0-21swapper/1200:00:154
45319913025,67cyclictest0-21swapper/1220:01:054
45319913024,62cyclictest0-21swapper/1223:20:584
4531991300,79cyclictest0-21swapper/1220:35:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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