You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-16 - 20:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Fri Jan 16, 2026 12:48:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
193722224217,6sleep60-21swapper/607:06:0628
210059918726,149cyclictest0-21swapper/2311:17:4416
210059918726,149cyclictest0-21swapper/2311:17:4416
181852185177,6sleep250-21swapper/2507:05:2018
3273911830,174ptp4l0-21swapper/107:07:101
210059917922,120cyclictest0-21swapper/2308:10:1216
210059915926,110cyclictest0-21swapper/2311:34:1916
210059915926,110cyclictest0-21swapper/2311:34:1916
21005991590,116cyclictest0-21swapper/2312:23:3116
20970991470,85cyclictest0-21swapper/1809:21:1010
21005991420,85cyclictest0-21swapper/2309:15:3716
21005991410,85cyclictest0-21swapper/2310:55:1316
21005991410,85cyclictest0-21swapper/2310:55:1216
209359914114,32cyclictest0-21swapper/1312:24:575
21005991400,83cyclictest0-21swapper/2309:20:1216
21005991400,82cyclictest0-21swapper/2312:02:0716
209359914014,125cyclictest0-21swapper/1307:20:215
195872140133,6sleep100-21swapper/1007:09:212
21005991390,83cyclictest0-21swapper/2308:35:1216
209429913941,56cyclictest0-21swapper/1410:40:136
209429913941,56cyclictest0-21swapper/1410:40:126
209359913914,124cyclictest0-21swapper/1309:39:165
21005991380,82cyclictest0-21swapper/2310:30:1216
21005991380,82cyclictest0-21swapper/2310:30:1116
21005991380,82cyclictest0-21swapper/2308:58:5016
209359913814,96cyclictest9617-21diskmemload12:34:015
210059913628,70cyclictest0-21swapper/2309:05:1516
21005991360,81cyclictest0-21swapper/2311:50:2316
209359913614,87cyclictest0-21swapper/1310:11:535
209359913612,106cyclictest0-21swapper/1312:19:365
210419913542,74cyclictest0-21swapper/2811:34:1421
210419913542,74cyclictest0-21swapper/2811:34:1321
210059913429,64cyclictest0-21swapper/2311:01:4416
210059913429,64cyclictest0-21swapper/2311:01:4416
21005991340,27cyclictest0-21swapper/2311:55:1016
210059913327,69cyclictest0-21swapper/2311:43:5716
209359913314,73cyclictest0-21swapper/1310:40:115
209359913314,73cyclictest0-21swapper/1310:40:115
21005991320,77cyclictest0-21swapper/2311:10:1816
21005991320,77cyclictest0-21swapper/2311:10:1716
210419913120,29cyclictest0-21swapper/2812:10:3421
21005991315,75cyclictest0-21swapper/2310:28:0516
21005991315,75cyclictest0-21swapper/2310:28:0416
210059913127,66cyclictest0-21swapper/2308:34:0716
21005991310,78cyclictest0-21swapper/2310:10:5816
209709913152,60cyclictest0-21swapper/1809:11:0110
20963991310,84cyclictest0-21swapper/1710:25:189
20963991310,84cyclictest0-21swapper/1710:25:189
210419913078,45cyclictest0-21swapper/2811:00:3821
210419913078,45cyclictest0-21swapper/2811:00:3721
210059913027,60cyclictest0-21swapper/2309:45:1816
21005991300,78cyclictest0-21swapper/2310:47:4416
21005991300,78cyclictest0-21swapper/2310:47:4316
209429913028,61cyclictest0-21swapper/1411:21:226
209429912926,62cyclictest0-21swapper/1411:44:206
210419912845,55cyclictest0-21swapper/2812:20:2121
210419912844,56cyclictest0-21swapper/2810:45:1821
210419912844,56cyclictest0-21swapper/2810:45:1721
210419912840,59cyclictest0-21swapper/2809:15:2121
21005991285,75cyclictest0-21swapper/2309:43:0916
210059912831,63cyclictest0-21swapper/2310:17:5516
210059912831,63cyclictest0-21swapper/2310:17:5516
210059912828,62cyclictest0-21swapper/2309:53:5316
209709912848,51cyclictest0-21swapper/1810:26:2310
209709912848,51cyclictest0-21swapper/1810:26:2310
209709912836,72cyclictest0-21swapper/1812:03:3810
209709912828,66cyclictest0-21swapper/1812:12:4410
209709912825,61cyclictest0-21swapper/1810:54:4310
209709912825,61cyclictest0-21swapper/1810:54:4210
20963991281,74cyclictest0-21swapper/1710:47:369
20963991281,74cyclictest0-21swapper/1710:47:359
20942991283,74cyclictest0-21swapper/1409:24:206
209429912826,60cyclictest0-21swapper/1411:36:526
209709912714,63cyclictest0-21swapper/1807:54:0510
20942991273,75cyclictest0-21swapper/1409:16:506
209359912714,70cyclictest0-21swapper/1310:17:455
209359912714,70cyclictest0-21swapper/1310:17:445
210059912644,48cyclictest0-21swapper/2309:11:0716
210059912628,67cyclictest0-21swapper/2310:40:2216
210059912628,67cyclictest0-21swapper/2310:40:2116
21005991260,79cyclictest0-21swapper/2312:18:0716
209709912628,64cyclictest0-21swapper/1812:06:5110
209709912627,64cyclictest0-21swapper/1809:30:4810
209709912626,67cyclictest0-21swapper/1807:25:0210
209709912626,66cyclictest0-21swapper/1809:44:1010
209709912624,63cyclictest0-21swapper/1811:43:5310
209709912622,63cyclictest0-21swapper/1808:46:4410
20963991266,103cyclictest0-21swapper/1707:16:089
20942991263,71cyclictest0-21swapper/1410:00:396
20895991264,70cyclictest0-21swapper/810:10:3230
210419912549,59cyclictest0-21swapper/2810:56:1721
210419912549,59cyclictest0-21swapper/2810:56:1621
210419912543,57cyclictest0-21swapper/2811:13:2321
210419912543,57cyclictest0-21swapper/2811:13:2221
210419912528,63cyclictest0-21swapper/2809:21:0821
210059912555,65cyclictest0-21swapper/2307:37:0416
210059912528,61cyclictest0-21swapper/2311:47:2316
210059912525,69cyclictest0-21swapper/2307:55:1516
210059912524,62cyclictest0-21swapper/2309:59:4416
210059912514,74cyclictest0-21swapper/2309:02:2616
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional