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2026-02-18 - 20:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Wed Feb 18, 2026 12:49:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912750,261ptp4l0-21swapper/107:05:151
330891198190,6phc2sys0-21swapper/207:07:3912
88529917714,135cyclictest0-21swapper/1811:30:1510
88769916511,113cyclictest0-21swapper/2211:56:1515
8815991640,116cyclictest0-21swapper/1009:17:192
88769915511,107cyclictest0-21swapper/2212:20:1915
88529915117,28cyclictest0-21swapper/1811:05:2610
87889914910,135cyclictest151rcu_preempt09:40:4323
88769914711,84cyclictest0-21swapper/2210:07:4515
8907991450,84cyclictest0-21swapper/3011:36:0524
8852991440,88cyclictest0-21swapper/1810:33:4310
89079914230,60cyclictest0-21swapper/3012:00:3924
8788991420,83cyclictest0-21swapper/309:55:4123
87889914032,105cyclictest151rcu_preempt11:27:0523
88529913917,121cyclictest0-21swapper/1807:45:0110
88529913917,121cyclictest0-21swapper/1807:45:0010
8904991380,83cyclictest0-21swapper/2909:13:2122
88039913866,71cyclictest0-21swapper/707:30:2429
88039913866,71cyclictest0-21swapper/707:30:2429
8815991370,85cyclictest0-21swapper/1010:39:052
87769913740,95cyclictest0-21swapper/010:54:410
88769913611,73cyclictest0-21swapper/2210:15:4715
88529913617,110cyclictest0-21swapper/1810:25:2010
88369913629,103cyclictest0-21swapper/1508:40:017
8803991360,86cyclictest0-21swapper/707:35:2629
8803991360,86cyclictest0-21swapper/707:35:2629
89079913550,56cyclictest0-21swapper/3012:29:0124
89079913451,55cyclictest0-21swapper/3009:20:1924
89079913444,57cyclictest0-21swapper/3009:47:0324
89079913443,58cyclictest0-21swapper/3009:12:1824
89079913429,73cyclictest0-21swapper/3009:19:4724
8803991340,78cyclictest0-21swapper/710:56:4129
89079913336,62cyclictest0-21swapper/3011:54:1524
89079913328,70cyclictest0-21swapper/3012:10:5024
89079913326,67cyclictest0-21swapper/3012:21:3124
89079913326,66cyclictest0-21swapper/3011:32:2024
88769913311,96cyclictest0-21swapper/2208:35:1915
88529913317,21cyclictest0-21swapper/1809:30:5010
88159913317,90cyclictest0-21swapper/1009:12:302
87939913317,102cyclictest151rcu_preempt12:22:3426
89079913256,71cyclictest0-21swapper/3011:28:0424
89079913228,69cyclictest0-21swapper/3010:13:1424
89079913227,68cyclictest0-21swapper/3007:55:2224
89079913227,68cyclictest0-21swapper/3007:55:2224
89079913226,65cyclictest0-21swapper/3012:39:0924
89079913129,72cyclictest0-21swapper/3009:27:4824
89079913127,70cyclictest0-21swapper/3010:00:2424
87769913136,4cyclictest0-21swapper/011:29:450
89079913029,69cyclictest0-21swapper/3010:22:5224
89079913028,66cyclictest0-21swapper/3010:59:4424
89049913024,105cyclictest0-21swapper/2910:50:1322
88369913029,86cyclictest0-21swapper/1512:01:297
8788991300,76cyclictest0-21swapper/308:55:1723
8776991301,84cyclictest0-21swapper/010:30:110
89079912929,74cyclictest0-21swapper/3009:58:4724
89079912928,67cyclictest0-21swapper/3009:54:3224
89079912928,64cyclictest0-21swapper/3011:45:4324
89079912926,65cyclictest0-21swapper/3010:30:5324
89079912925,63cyclictest0-21swapper/3011:20:0324
89049912944,56cyclictest0-21swapper/2910:27:3922
89079912831,76cyclictest0-21swapper/3009:38:3024
89079912828,73cyclictest0-21swapper/3007:50:0224
89079912828,73cyclictest0-21swapper/3007:50:0124
89079912828,68cyclictest0-21swapper/3010:49:0324
89049912842,59cyclictest0-21swapper/2912:29:3122
88369912829,98cyclictest0-21swapper/1507:35:217
88369912829,98cyclictest0-21swapper/1507:35:207
87769912840,54cyclictest0-21swapper/011:44:590
87769912833,56cyclictest0-21swapper/009:45:200
87769912830,97cyclictest0-21swapper/009:30:210
89079912743,73cyclictest0-21swapper/3011:15:1424
89079912732,66cyclictest0-21swapper/3010:36:1424
89049912746,55cyclictest0-21swapper/2909:20:1822
89049912745,56cyclictest0-21swapper/2907:59:3722
89049912745,56cyclictest0-21swapper/2907:59:3722
89049912742,57cyclictest0-21swapper/2910:08:2422
89049912742,53cyclictest0-21swapper/2908:14:0422
89049912742,53cyclictest0-21swapper/2908:14:0422
89049912725,65cyclictest0-21swapper/2911:37:0822
88769912712,63cyclictest0-21swapper/2211:30:3015
88369912722,103cyclictest0-21swapper/1509:15:167
89079912660,66cyclictest0-21swapper/3010:52:1524
89079912632,77cyclictest0-21swapper/3012:08:1024
89079912627,64cyclictest0-21swapper/3011:40:5324
89079912626,67cyclictest0-21swapper/3007:30:1624
89079912626,67cyclictest0-21swapper/3007:30:1524
89049912641,55cyclictest0-21swapper/2909:05:5322
88369912623,66cyclictest0-21swapper/1509:35:027
87889912633,60cyclictest0-21swapper/310:38:5823
87769912629,89cyclictest0-21swapper/012:05:210
87769912629,77cyclictest0-21swapper/009:17:520
89079912531,80cyclictest0-21swapper/3009:44:5424
89079912529,68cyclictest0-21swapper/3010:43:4224
89079912529,67cyclictest0-21swapper/3010:19:0824
89079912528,71cyclictest0-21swapper/3007:10:2924
89079912528,71cyclictest0-21swapper/3007:10:2924
89079912528,69cyclictest0-21swapper/3007:40:2424
89079912528,69cyclictest0-21swapper/3007:40:2424
89079912528,64cyclictest0-21swapper/3008:52:3224
89079912527,65cyclictest0-21swapper/3008:25:1724
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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