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2026-02-26 - 20:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Thu Feb 26, 2026 12:48:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891244236,6phc2sys0-21swapper/207:09:1812
330891244236,6phc2sys0-21swapper/207:09:1812
35199914833,26cyclictest0-21swapper/008:55:240
20992147140,5sleep10-21swapper/107:07:231
20992147140,5sleep10-21swapper/107:07:231
35329914519,94cyclictest151rcu_preempt12:05:2023
35329914519,94cyclictest151rcu_preempt12:05:2023
3549991440,85cyclictest0-21swapper/707:10:0129
35299914418,71cyclictest0-21swapper/212:35:0112
3519991430,82cyclictest0-21swapper/010:43:160
3553991420,88cyclictest0-21swapper/808:49:3630
3541991421,84cyclictest0-21swapper/507:25:5227
35329914219,100cyclictest151rcu_preempt11:31:0723
35329914219,100cyclictest151rcu_preempt11:31:0723
3553991417,108cyclictest151rcu_preempt09:17:2330
35539913639,75cyclictest151rcu_preempt10:02:1730
35539913612,115cyclictest151rcu_preempt10:48:2230
35499913651,38cyclictest0-21swapper/709:50:4329
3541991350,81cyclictest0-21swapper/512:20:5327
3541991350,81cyclictest0-21swapper/512:20:5227
35619913455,45cyclictest0-21swapper/1008:22:352
36939913316,15cyclictest0-21swapper/3012:28:4624
3541991330,76cyclictest0-21swapper/510:51:3627
36749913229,67cyclictest0-21swapper/2711:38:2820
36749913229,67cyclictest0-21swapper/2711:38:2720
36749913227,69cyclictest0-21swapper/2709:18:2620
36999913132,68cyclictest0-21swapper/3109:55:5525
36939913133,92cyclictest0-21swapper/3011:01:0524
36749913127,71cyclictest0-21swapper/2712:03:0320
36749913127,71cyclictest0-21swapper/2712:03:0320
36749913125,63cyclictest0-21swapper/2709:55:1920
36749913028,67cyclictest0-21swapper/2712:05:1220
36749913028,67cyclictest0-21swapper/2712:05:1220
36749913027,68cyclictest0-21swapper/2710:49:3520
35499913011,117cyclictest151rcu_preempt09:35:1329
35199913064,24cyclictest0-21swapper/010:57:400
36749912930,70cyclictest0-21swapper/2710:29:2920
36749912929,67cyclictest0-21swapper/2710:19:2220
36749912928,66cyclictest0-21swapper/2711:04:1620
36749912928,66cyclictest0-21swapper/2710:56:1520
36749912926,66cyclictest0-21swapper/2711:54:1220
36749912926,66cyclictest0-21swapper/2711:54:1220
3541991290,80cyclictest0-21swapper/509:44:4827
36939912830,85cyclictest0-21swapper/3011:10:1224
36939912830,85cyclictest0-21swapper/3011:10:1224
36749912832,74cyclictest0-21swapper/2712:13:4520
36749912832,74cyclictest0-21swapper/2712:13:4520
36749912825,67cyclictest0-21swapper/2709:54:4720
3544991280,78cyclictest0-21swapper/609:36:1628
36749912728,63cyclictest0-21swapper/2711:47:0120
36749912728,63cyclictest0-21swapper/2711:47:0120
36749912727,65cyclictest0-21swapper/2708:54:5620
3538991271,82cyclictest0-21swapper/411:17:3626
36939912628,72cyclictest0-21swapper/3009:33:5924
36749912628,63cyclictest0-21swapper/2708:46:4420
36749912627,64cyclictest0-21swapper/2710:24:4320
36749912625,67cyclictest0-21swapper/2712:15:2220
36749912625,67cyclictest0-21swapper/2712:15:2120
36749912625,66cyclictest0-21swapper/2707:36:2420
36749912531,74cyclictest0-21swapper/2707:10:1220
36749912528,74cyclictest0-21swapper/2708:29:1720
36749912528,59cyclictest0-21swapper/2708:41:3420
36749912527,65cyclictest0-21swapper/2710:40:1320
36749912527,62cyclictest0-21swapper/2710:50:2220
36749912526,69cyclictest0-21swapper/2707:40:0720
3541991259,73cyclictest0-21swapper/510:38:1527
35199912549,57cyclictest0-21swapper/010:20:200
36999912427,66cyclictest0-21swapper/3108:21:3725
36749912428,63cyclictest0-21swapper/2711:32:3720
36749912428,63cyclictest0-21swapper/2711:32:3620
36749912427,63cyclictest0-21swapper/2709:26:2720
35199912429,63cyclictest0-21swapper/011:55:110
35199912429,63cyclictest0-21swapper/011:55:110
35199912420,60cyclictest13682-21ssh09:22:420
36999912343,49cyclictest0-21swapper/3112:22:2125
36999912343,49cyclictest0-21swapper/3112:22:2125
36999912333,61cyclictest0-21swapper/3109:50:0225
36799912324,57cyclictest0-21swapper/2812:30:1421
36749912353,69cyclictest0-21swapper/2709:31:1620
36749912329,71cyclictest0-21swapper/2710:01:4420
36749912328,59cyclictest0-21swapper/2708:30:2120
36749912325,64cyclictest0-21swapper/2711:59:5120
36749912325,64cyclictest0-21swapper/2711:59:5120
36749912323,60cyclictest0-21swapper/2712:25:3020
35199912347,53cyclictest0-21swapper/011:52:480
35199912347,53cyclictest0-21swapper/011:52:470
35199912342,53cyclictest0-21swapper/009:58:570
35199912334,58cyclictest0-21swapper/010:01:420
36749912231,74cyclictest0-21swapper/2708:05:3520
36749912228,71cyclictest0-21swapper/2709:37:4120
36749912226,63cyclictest0-21swapper/2711:05:2020
36749912225,64cyclictest0-21swapper/2712:22:5020
36749912225,64cyclictest0-21swapper/2712:22:5020
36749912224,59cyclictest0-21swapper/2709:09:5320
3553991227,111cyclictest151rcu_preempt11:05:5130
35499912233,50cyclictest0-21swapper/711:13:1529
35499912233,50cyclictest0-21swapper/711:13:1529
35199912247,54cyclictest0-21swapper/012:06:230
35199912247,54cyclictest0-21swapper/012:06:230
35199912227,64cyclictest0-21swapper/011:10:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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