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2026-02-11 - 08:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Wed Feb 11, 2026 00:48:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912970,289ptp4l0-21swapper/119:08:051
90369918846,115cyclictest0-21swapper/022:03:550
90369918846,115cyclictest0-21swapper/022:03:550
90559917812,144cyclictest151rcu_preempt21:21:5026
90559917358,77cyclictest151rcu_preempt22:50:3326
90559917358,77cyclictest151rcu_preempt22:50:3326
9110991722,140cyclictest0-21swapper/1823:49:4610
90369917129,106cyclictest0-21swapper/023:37:570
90369917026,143cyclictest0-21swapper/021:40:160
90369917022,145cyclictest0-21swapper/021:14:320
90369916927,120cyclictest0-21swapper/000:06:050
90369916619,145cyclictest0-21swapper/023:21:420
90609915598,35cyclictest0-21swapper/522:35:4027
90609915598,35cyclictest0-21swapper/522:35:4027
90559915519,90cyclictest151rcu_preempt21:15:2726
91309915235,79cyclictest0-21swapper/2323:13:3016
91309915235,79cyclictest0-21swapper/2323:13:3016
90369915028,78cyclictest0-21swapper/023:06:120
90369915028,78cyclictest0-21swapper/023:06:110
91309914935,63cyclictest0-21swapper/2321:06:1716
91309914830,116cyclictest0-21swapper/2300:05:2116
91309914528,105cyclictest0-21swapper/2321:30:2016
90369914519,98cyclictest0-21swapper/023:25:170
77442145138,6sleep150-21swapper/1519:09:267
91479914430,87cyclictest0-21swapper/2722:55:2420
91479914430,87cyclictest0-21swapper/2722:55:2420
91309914427,116cyclictest0-21swapper/2322:00:1716
91309914427,116cyclictest0-21swapper/2322:00:1716
91309914323,43cyclictest0-21swapper/2323:30:2116
90539914314,96cyclictest0-21swapper/322:09:2923
90539914314,96cyclictest0-21swapper/322:09:2923
9144991420,85cyclictest0-21swapper/2621:43:2919
9124991420,83cyclictest0-21swapper/2123:55:4114
91309914124,75cyclictest0-21swapper/2322:14:2716
91309914124,75cyclictest0-21swapper/2322:14:2716
9107991400,83cyclictest0-21swapper/1722:36:319
9107991400,83cyclictest0-21swapper/1722:36:319
9053991400,83cyclictest0-21swapper/320:40:1923
90369914027,69cyclictest0-21swapper/020:15:010
9124991390,85cyclictest0-21swapper/2122:48:2114
9124991390,85cyclictest0-21swapper/2122:48:2114
90779913947,61cyclictest0-21swapper/922:45:2931
90779913947,61cyclictest0-21swapper/922:45:2931
9130991380,88cyclictest0-21swapper/2320:43:4416
90919913831,103cyclictest0-21swapper/1300:25:165
9077991380,85cyclictest0-21swapper/921:55:1431
90369913820,102cyclictest8046-21latency_hist20:00:000
91449913749,61cyclictest12775-21taskset23:09:0019
91449913749,61cyclictest12775-21taskset23:09:0019
90919913729,107cyclictest0-21swapper/1300:19:375
90779913749,57cyclictest0-21swapper/922:31:2131
90779913749,57cyclictest0-21swapper/922:31:2131
90539913766,43cyclictest0-21swapper/321:44:2723
9053991370,83cyclictest0-21swapper/323:37:4323
90369913751,61cyclictest0-21swapper/021:35:450
90369913727,65cyclictest0-21swapper/023:43:380
91449913646,56cyclictest0-21swapper/2622:20:0719
91449913646,56cyclictest0-21swapper/2622:20:0619
90919913630,74cyclictest0-21swapper/1322:40:125
90919913630,74cyclictest0-21swapper/1322:40:125
9091991360,81cyclictest0-21swapper/1322:15:375
9091991360,81cyclictest0-21swapper/1322:15:375
9072991363,125cyclictest0-21swapper/820:45:0130
90369913638,65cyclictest0-21swapper/000:25:500
90369913627,67cyclictest0-21swapper/023:30:000
91449913550,51cyclictest0-21swapper/2623:17:4019
90559913548,58cyclictest0-21swapper/423:23:4426
90539913540,62cyclictest0-21swapper/323:01:5623
90539913540,62cyclictest0-21swapper/323:01:5623
90539913524,66cyclictest0-21swapper/300:13:1723
90369913552,58cyclictest0-21swapper/021:19:370
90369913529,71cyclictest0-21swapper/022:48:200
90369913529,71cyclictest0-21swapper/022:48:200
90369913526,67cyclictest0-21swapper/019:47:390
90369913526,64cyclictest0-21swapper/021:22:450
90369913521,23cyclictest0-21swapper/020:45:250
9110991340,86cyclictest0-21swapper/1821:16:2210
90779913450,60cyclictest0-21swapper/922:17:4131
90779913450,60cyclictest0-21swapper/922:17:4031
90539913442,57cyclictest0-21swapper/300:37:0523
90369913448,61cyclictest0-21swapper/022:28:310
90369913448,61cyclictest0-21swapper/022:28:310
90369913447,62cyclictest0-21swapper/021:33:590
90369913432,68cyclictest0-21swapper/022:30:130
90369913432,68cyclictest0-21swapper/022:30:130
90369913429,70cyclictest0-21swapper/021:45:160
90369913428,92cyclictest0-21swapper/022:56:040
90369913428,92cyclictest0-21swapper/022:56:030
90369913428,71cyclictest0-21swapper/021:54:170
90369913428,70cyclictest0-21swapper/020:36:480
90369913428,69cyclictest0-21swapper/020:20:180
9144991330,82cyclictest0-21swapper/2621:55:1519
9124991330,82cyclictest0-21swapper/2123:45:0014
90559913326,81cyclictest16493-21cpuspeed_turbos22:05:1126
90559913326,81cyclictest16493-21cpuspeed_turbos22:05:1126
90539913328,68cyclictest0-21swapper/322:18:0723
90539913328,68cyclictest0-21swapper/322:18:0623
9053991330,82cyclictest0-21swapper/321:36:0723
90369913356,61cyclictest0-21swapper/021:55:240
90369913332,76cyclictest0-21swapper/023:59:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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