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2026-02-16 - 17:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Mon Feb 16, 2026 12:49:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
372399312116,1cyclictest151rcu_preempt12:32:1417
3273912910,283ptp4l0-21swapper/107:08:361
330891249238,8phc2sys0-21swapper/207:05:2512
36359915822,135cyclictest0-21swapper/511:30:5527
36359915822,135cyclictest0-21swapper/511:28:1427
36149915832,88cyclictest0-21swapper/008:47:060
36149915832,88cyclictest0-21swapper/008:47:050
36359915621,83cyclictest0-21swapper/510:12:2227
36359915621,83cyclictest0-21swapper/510:12:2227
36359915621,100cyclictest0-21swapper/509:21:3427
36359915621,100cyclictest0-21swapper/509:21:3427
36359915417,113cyclictest0-21swapper/508:10:1027
37289915359,91cyclictest0-21swapper/2511:06:4018
36359915221,93cyclictest0-21swapper/509:15:4127
36359915221,93cyclictest0-21swapper/509:15:4127
36359914721,80cyclictest0-21swapper/511:42:0827
36149914773,2cyclictest151rcu_preempt09:51:140
36149914773,2cyclictest151rcu_preempt09:51:140
3614991469,120cyclictest14667-21sed08:10:000
37289914553,74cyclictest0-21swapper/2512:33:1518
37289914549,6cyclictest0-21swapper/2511:24:5118
3731991440,84cyclictest0-21swapper/2611:39:1619
3731991430,84cyclictest0-21swapper/2607:55:2219
3617991430,85cyclictest0-21swapper/109:26:201
3617991430,85cyclictest0-21swapper/109:26:201
3728991429,131cyclictest151rcu_preempt10:02:3218
3728991429,131cyclictest151rcu_preempt10:02:3118
37289914147,54cyclictest0-21swapper/2512:23:5318
3617991411,86cyclictest0-21swapper/110:57:111
3617991400,85cyclictest0-21swapper/110:02:401
3617991400,85cyclictest0-21swapper/110:02:391
37319913944,58cyclictest0-21swapper/2611:55:1819
3731991390,82cyclictest0-21swapper/2609:35:1819
3731991390,82cyclictest0-21swapper/2609:35:1819
3731991390,81cyclictest0-21swapper/2610:05:1419
3731991390,81cyclictest0-21swapper/2610:05:1419
3643991390,85cyclictest0-21swapper/711:18:0829
3617991390,84cyclictest0-21swapper/112:28:351
37319913841,61cyclictest0-21swapper/2612:23:0519
3731991380,85cyclictest0-21swapper/2611:52:0619
36179913842,60cyclictest0-21swapper/109:57:511
36179913842,60cyclictest0-21swapper/109:57:511
37319913718,72cyclictest0-21swapper/2612:31:0719
3731991370,81cyclictest0-21swapper/2608:40:1419
3731991360,80cyclictest0-21swapper/2611:08:1819
36359913622,77cyclictest0-21swapper/510:49:1427
36179913648,57cyclictest0-21swapper/108:35:201
36179913629,71cyclictest0-21swapper/112:01:331
36179913626,66cyclictest0-21swapper/111:00:241
37319913543,64cyclictest0-21swapper/2611:15:4719
3731991350,81cyclictest0-21swapper/2611:00:1719
3731991350,79cyclictest0-21swapper/2610:00:2519
3731991350,79cyclictest0-21swapper/2610:00:2519
3695991358,78cyclictest0-21swapper/1809:51:1110
3695991358,78cyclictest0-21swapper/1809:51:1110
3664991359,103cyclictest151rcu_preempt07:15:244
36179913549,61cyclictest0-21swapper/109:41:501
36179913549,61cyclictest0-21swapper/109:41:501
36179913549,54cyclictest0-21swapper/111:09:291
3617991350,82cyclictest0-21swapper/110:09:051
3617991350,82cyclictest0-21swapper/110:09:041
37319913429,65cyclictest0-21swapper/2610:55:5819
37319913427,67cyclictest0-21swapper/2611:11:3019
3731991340,80cyclictest0-21swapper/2612:35:2419
3731991340,79cyclictest0-21swapper/2609:30:2719
3731991340,79cyclictest0-21swapper/2609:30:2719
3731991340,78cyclictest0-21swapper/2612:02:1519
36959913417,112cyclictest151rcu_preempt12:16:0110
36179913449,67cyclictest0-21swapper/111:42:051
36179913445,57cyclictest0-21swapper/108:41:081
36179913429,69cyclictest0-21swapper/112:24:501
37319913346,65cyclictest0-21swapper/2612:10:1719
37319913328,64cyclictest0-21swapper/2610:30:2119
3731991330,77cyclictest0-21swapper/2609:20:1919
3731991330,77cyclictest0-21swapper/2609:20:1919
36439913342,90cyclictest0-21swapper/710:50:2029
36179913347,54cyclictest0-21swapper/111:38:371
36179913342,66cyclictest0-21swapper/110:45:251
36179913328,68cyclictest0-21swapper/108:17:231
36179913327,67cyclictest0-21swapper/112:38:431
36179913326,69cyclictest0-21swapper/111:55:271
36149913317,94cyclictest151rcu_preempt12:04:150
3743991320,84cyclictest0-21swapper/2911:12:0422
37319913231,66cyclictest0-21swapper/2610:44:1519
3731991320,76cyclictest0-21swapper/2607:31:1919
36179913253,70cyclictest0-21swapper/111:30:191
36179913247,62cyclictest0-21swapper/110:40:041
36179913231,67cyclictest0-21swapper/107:30:551
36179913228,67cyclictest0-21swapper/112:16:321
36179913227,65cyclictest0-21swapper/111:25:311
36179913226,65cyclictest0-21swapper/108:00:171
37319913129,65cyclictest0-21swapper/2610:25:3219
3731991310,81cyclictest0-21swapper/2609:00:0219
3731991310,81cyclictest0-21swapper/2609:00:0219
36179913155,59cyclictest0-21swapper/109:39:401
36179913155,59cyclictest0-21swapper/109:39:401
36179913140,60cyclictest0-21swapper/109:10:151
36179913140,60cyclictest0-21swapper/109:10:151
36179913132,73cyclictest0-21swapper/107:37:191
36179913131,70cyclictest0-21swapper/108:50:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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