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2026-07-24 - 04:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Fri Jul 24, 2026 00:49:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912750,267ptp4l0-21swapper/119:09:451
74579917553,84cyclictest0-21swapper/1622:21:568
73969917225,128cyclictest0-21swapper/800:20:1730
73969916924,87cyclictest0-21swapper/823:31:0530
27912167159,6sleep280-21swapper/2819:05:1521
74579916449,69cyclictest0-21swapper/1622:56:338
75629915940,117cyclictest0-21swapper/3023:55:4324
73469915928,34cyclictest0-21swapper/100:08:351
73469915928,129cyclictest0-21swapper/122:55:551
74579915834,123cyclictest0-21swapper/1623:30:118
73469915828,115cyclictest0-21swapper/121:35:441
73469915828,115cyclictest0-21swapper/121:35:441
73469915728,89cyclictest0-21swapper/121:45:221
73469915728,84cyclictest0-21swapper/123:20:151
73469915728,128cyclictest0-21swapper/123:36:001
73469915727,83cyclictest0-21swapper/123:50:261
73469915628,86cyclictest0-21swapper/122:29:431
73469915627,79cyclictest0-21swapper/122:00:191
75629915336,115cyclictest0-21swapper/3022:27:0024
73469915324,81cyclictest0-21swapper/100:29:261
748799151133,1cyclictest0-21swapper/2000:34:2713
74579915025,121cyclictest0-21swapper/1600:20:268
73469915020,94cyclictest0-21swapper/122:06:441
74579914920,100cyclictest0-21swapper/1622:09:058
73969914924,83cyclictest0-21swapper/820:05:2130
75629914830,105cyclictest0-21swapper/3000:07:2724
75629914730,83cyclictest0-21swapper/3021:45:5124
73969914523,79cyclictest0-21swapper/822:55:1730
75629914426,117cyclictest0-21swapper/3022:08:5024
73969914421,85cyclictest0-21swapper/822:26:2930
7396991440,83cyclictest0-21swapper/822:46:2830
74029914318,115cyclictest0-21swapper/920:00:1231
7346991430,90cyclictest0-21swapper/100:21:261
75629914224,115cyclictest0-21swapper/3000:01:3524
74579913934,60cyclictest0-21swapper/1622:30:198
73969913924,76cyclictest0-21swapper/820:00:0130
75629913841,56cyclictest0-21swapper/3021:10:0124
74579913823,114cyclictest0-21swapper/1623:10:258
73469913825,73cyclictest0-21swapper/123:58:591
7571991370,79cyclictest0-21swapper/3122:25:5625
7549991371,85cyclictest0-21swapper/2822:49:5121
74579913751,57cyclictest0-21swapper/1620:09:228
74579913626,60cyclictest0-21swapper/1623:26:268
7402991369,76cyclictest0-21swapper/921:15:0131
7402991369,76cyclictest0-21swapper/921:15:0131
74579913550,69cyclictest0-21swapper/1622:10:418
74579913528,63cyclictest0-21swapper/1600:03:168
74579913527,68cyclictest0-21swapper/1600:16:098
74579913523,68cyclictest0-21swapper/1621:26:268
74579913512,72cyclictest0-21swapper/1622:01:598
74579913510,73cyclictest0-21swapper/1621:40:368
74579913426,65cyclictest0-21swapper/1600:10:148
73649913473,1cyclictest151rcu_preempt22:18:3526
74579913341,58cyclictest0-21swapper/1620:27:248
74579913341,58cyclictest0-21swapper/1620:27:248
74579913328,63cyclictest0-21swapper/1623:00:148
74579913326,70cyclictest0-21swapper/1622:36:518
74579913324,68cyclictest0-21swapper/1622:41:018
7418991330,86cyclictest0-21swapper/1100:31:503
330891133125,6phc2sys0-21swapper/219:07:1512
74579913248,70cyclictest0-21swapper/1619:45:538
74579913245,58cyclictest0-21swapper/1600:31:058
74579913244,53cyclictest0-21swapper/1623:56:228
74579913230,78cyclictest0-21swapper/1622:47:268
74579913227,66cyclictest0-21swapper/1623:07:108
7418991320,85cyclictest0-21swapper/1119:19:443
7418991320,69cyclictest0-21swapper/1122:00:433
73469913250,81cyclictest22-21ksoftirqd/100:12:211
7549991310,85cyclictest0-21swapper/2821:40:1621
74579913150,55cyclictest0-21swapper/1620:01:558
74579913150,54cyclictest0-21swapper/1619:20:218
74579913132,64cyclictest0-21swapper/1622:51:088
74579913129,69cyclictest0-21swapper/1600:37:328
74579913129,68cyclictest0-21swapper/1623:37:398
74579913128,68cyclictest0-21swapper/1619:55:208
74579913127,68cyclictest0-21swapper/1621:30:568
74579913126,60cyclictest0-21swapper/1619:54:488
74579913125,71cyclictest0-21swapper/1622:18:488
73879913135,74cyclictest0-21swapper/700:30:0429
75629913021,64cyclictest0-21swapper/3000:30:0524
74579913039,60cyclictest0-21swapper/1620:51:268
74579913039,60cyclictest0-21swapper/1620:51:258
74579913038,57cyclictest0-21swapper/1622:28:108
74579913029,68cyclictest0-21swapper/1621:53:558
74579913028,68cyclictest0-21swapper/1620:19:548
74579913028,66cyclictest0-21swapper/1619:40:258
74579913026,69cyclictest0-21swapper/1619:39:518
7418991300,83cyclictest0-21swapper/1123:00:533
7571991290,71cyclictest0-21swapper/3100:08:3325
74579912931,71cyclictest0-21swapper/1623:47:498
74579912929,65cyclictest0-21swapper/1600:25:148
74579912928,71cyclictest0-21swapper/1621:49:388
74579912928,71cyclictest0-21swapper/1620:39:098
74579912928,71cyclictest0-21swapper/1620:39:098
74579912928,69cyclictest0-21swapper/1621:38:588
74579912928,69cyclictest0-21swapper/1621:38:588
74579912927,68cyclictest0-21swapper/1621:05:198
74579912927,68cyclictest0-21swapper/1621:05:198
7457991291,69cyclictest0-21swapper/1623:15:098
73879912916,110cyclictest151rcu_preempt21:45:0429
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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