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2026-02-08 - 10:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Sun Feb 08, 2026 00:48:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912250,217ptp4l0-21swapper/119:05:291
276099917712,3cyclictest142250irq/65-enp5s0-t21:45:122
27584991644,101cyclictest0-21swapper/621:15:1328
27584991644,101cyclictest0-21swapper/621:15:1328
275779916134,84cyclictest151rcu_preempt22:39:3827
275779916023,73cyclictest151rcu_preempt20:30:5027
275779916023,73cyclictest151rcu_preempt20:30:5027
27577991602,154cyclictest151rcu_preempt20:36:4427
27577991602,154cyclictest151rcu_preempt20:36:4327
275779915125,84cyclictest151rcu_preempt22:01:1027
275779915118,86cyclictest151rcu_preempt21:45:3927
276549914911,108cyclictest0-21swapper/1720:00:269
277359914632,113cyclictest0-21swapper/3022:16:3224
277359914531,98cyclictest0-21swapper/3023:41:3124
275779914552,45cyclictest151rcu_preempt22:28:5827
275779914526,77cyclictest151rcu_preempt23:45:5627
275779914525,92cyclictest151rcu_preempt22:58:2227
277109914325,68cyclictest0-21swapper/2621:43:5219
275699914350,63cyclictest0-21swapper/422:50:2526
275469914324,95cyclictest0-21swapper/022:04:380
275469914324,118cyclictest0-21swapper/021:49:040
275469914324,117cyclictest0-21swapper/023:51:490
277049914213,95cyclictest0-21swapper/2523:35:0218
275779914236,87cyclictest151rcu_preempt19:52:2327
275469914224,90cyclictest0-21swapper/000:10:140
275469914222,115cyclictest0-21swapper/023:48:590
275779914081,15cyclictest151rcu_preempt23:38:5927
277109913948,57cyclictest0-21swapper/2623:06:4319
275469913924,100cyclictest0-21swapper/022:27:000
275469913923,76cyclictest0-21swapper/023:40:180
275469913820,92cyclictest0-21swapper/021:58:130
277109913749,59cyclictest0-21swapper/2623:28:3819
275699913745,61cyclictest0-21swapper/400:04:1726
330891136128,6phc2sys0-21swapper/219:08:0412
276549913611,92cyclictest0-21swapper/1722:53:509
275779913680,15cyclictest151rcu_preempt23:57:4127
275699913649,57cyclictest0-21swapper/421:00:0226
275699913649,57cyclictest0-21swapper/421:00:0126
277049913527,63cyclictest0-21swapper/2500:14:1918
275699913528,68cyclictest0-21swapper/421:05:2226
275699913528,68cyclictest0-21swapper/421:05:2226
275699913528,65cyclictest0-21swapper/423:30:1326
275699913528,64cyclictest0-21swapper/423:05:1126
275699913522,75cyclictest0-21swapper/422:41:1026
275469913523,67cyclictest0-21swapper/022:46:010
275469913519,96cyclictest0-21swapper/020:30:300
275469913519,96cyclictest0-21swapper/020:30:290
277109913452,56cyclictest28775-21kworker/26:022:49:0419
277109913451,56cyclictest0-21swapper/2623:17:2419
277109913447,57cyclictest0-21swapper/2621:21:2619
277109913447,57cyclictest0-21swapper/2621:21:2619
277109913445,57cyclictest0-21swapper/2600:34:2319
277109913440,59cyclictest0-21swapper/2621:59:2319
277049913450,51cyclictest0-21swapper/2523:45:4418
27577991349,90cyclictest151rcu_preempt20:11:0427
27577991349,90cyclictest151rcu_preempt20:11:0427
275699913428,70cyclictest0-21swapper/421:18:0826
275699913428,70cyclictest0-21swapper/421:18:0826
275699913428,66cyclictest0-21swapper/400:35:2526
275699913427,64cyclictest0-21swapper/422:20:1126
275699913423,71cyclictest0-21swapper/421:29:2526
275469913424,70cyclictest0-21swapper/023:01:490
277109913346,63cyclictest0-21swapper/2622:53:5319
277109913340,61cyclictest0-21swapper/2619:50:2019
277109913330,74cyclictest0-21swapper/2621:25:4219
277109913328,66cyclictest0-21swapper/2600:36:3119
277109913327,69cyclictest0-21swapper/2623:59:0619
277109913325,67cyclictest0-21swapper/2600:00:1119
275779913336,67cyclictest151rcu_preempt00:19:0327
275699913344,69cyclictest0-21swapper/419:30:1426
275699913327,69cyclictest0-21swapper/420:22:0226
275699913327,69cyclictest0-21swapper/420:22:0226
275699913321,79cyclictest40-21ksoftirqd/422:15:2326
275469913324,68cyclictest0-21swapper/020:45:010
275469913324,68cyclictest0-21swapper/020:45:010
275469913316,90cyclictest0-21swapper/021:11:130
275469913316,90cyclictest0-21swapper/021:11:130
277109913243,58cyclictest0-21swapper/2621:15:0119
277109913243,58cyclictest0-21swapper/2621:15:0119
277109913226,67cyclictest0-21swapper/2623:21:4219
276549913278,54cyclictest118-21ksoftirqd/1721:29:069
275699913245,53cyclictest0-21swapper/422:34:0626
275699913242,67cyclictest0-21swapper/400:28:1026
275699913232,72cyclictest0-21swapper/420:15:3326
275699913232,72cyclictest0-21swapper/420:15:3226
275699913229,71cyclictest0-21swapper/421:48:3726
275699913229,68cyclictest0-21swapper/423:20:5026
275699913228,67cyclictest0-21swapper/421:43:0026
275699913226,73cyclictest0-21swapper/421:10:1126
275699913226,73cyclictest0-21swapper/421:10:1126
275469913224,61cyclictest0-21swapper/021:35:140
277109913147,62cyclictest0-21swapper/2623:50:0119
277109913127,69cyclictest0-21swapper/2622:09:3219
276549913111,115cyclictest0-21swapper/1722:30:139
275779913118,90cyclictest151rcu_preempt23:14:5627
275699913137,61cyclictest0-21swapper/422:12:0926
275699913129,72cyclictest0-21swapper/423:00:1826
275699913129,72cyclictest0-21swapper/421:24:5126
275699913129,72cyclictest0-21swapper/421:24:5026
275699913129,71cyclictest0-21swapper/420:10:1926
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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