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2026-03-05 - 20:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8.osadl.org (updated Thu Mar 05, 2026 12:49:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2714599349145,201cyclictest151rcu_preempt09:46:3922
3273913310,323ptp4l0-21swapper/107:08:231
270489925658,2cyclictest151rcu_preempt09:45:195
270289916942,94cyclictest0-21swapper/811:52:4630
270289915931,104cyclictest0-21swapper/809:59:4830
270289915833,124cyclictest0-21swapper/810:55:1830
270289914528,67cyclictest0-21swapper/809:42:1930
27154991440,91cyclictest0-21swapper/3007:48:3524
27130991420,88cyclictest0-21swapper/2709:50:2220
271549914157,83cyclictest0-21swapper/3009:28:2924
271549914157,83cyclictest0-21swapper/3009:28:2924
269839914177,63cyclictest14062-21switchtime11:40:230
270839914011,128cyclictest0-21swapper/2112:35:5214
271459913947,90cyclictest0-21swapper/2911:18:3522
271169913957,63cyclictest0-21swapper/2512:28:3218
271169913951,52cyclictest0-21swapper/2511:35:0518
270839913912,126cyclictest0-21swapper/2110:33:0114
270839913912,103cyclictest0-21swapper/2110:14:4614
271169913829,65cyclictest0-21swapper/2509:33:1418
270839913812,97cyclictest0-21swapper/2109:03:4014
270839913812,97cyclictest0-21swapper/2109:03:4014
270839913812,89cyclictest0-21swapper/2110:45:5014
270839913812,125cyclictest0-21swapper/2110:52:1614
270839913812,106cyclictest0-21swapper/2110:24:2714
27077991380,81cyclictest0-21swapper/2009:11:3113
27077991380,81cyclictest0-21swapper/2009:11:3113
271169913748,65cyclictest0-21swapper/2510:16:3118
271169913728,64cyclictest0-21swapper/2512:22:0718
271169913728,62cyclictest0-21swapper/2509:17:4418
271169913728,62cyclictest0-21swapper/2509:17:4318
270839913713,70cyclictest0-21swapper/2111:00:4914
270839913712,73cyclictest0-21swapper/2111:16:5014
270289913722,86cyclictest0-21swapper/811:06:3030
270289913718,83cyclictest0-21swapper/811:24:4030
271169913630,64cyclictest0-21swapper/2510:56:0318
271169913629,65cyclictest0-21swapper/2510:54:5918
270839913612,76cyclictest0-21swapper/2109:19:4814
270839913612,76cyclictest0-21swapper/2109:19:4714
270839913612,75cyclictest0-21swapper/2112:06:3214
270839913612,68cyclictest0-21swapper/2112:11:5314
271169913550,67cyclictest0-21swapper/2511:29:4518
271169913529,64cyclictest0-21swapper/2512:18:2318
271169913529,62cyclictest0-21swapper/2510:40:0118
271169913529,61cyclictest0-21swapper/2509:57:1618
271169913528,64cyclictest0-21swapper/2511:08:2218
271169913528,63cyclictest0-21swapper/2509:36:2618
271169913528,63cyclictest0-21swapper/2509:36:2618
271169913526,50cyclictest0-21swapper/2511:41:2918
270839913512,92cyclictest0-21swapper/2110:40:1614
270839913512,101cyclictest0-21swapper/2107:55:1114
330891134127,6phc2sys0-21swapper/207:05:3612
271169913430,65cyclictest0-21swapper/2511:30:3218
270779913427,74cyclictest151rcu_preempt07:25:1413
271169913331,71cyclictest0-21swapper/2511:46:0218
271169913327,63cyclictest0-21swapper/2509:24:4118
271169913327,63cyclictest0-21swapper/2509:24:4018
271169913326,64cyclictest0-21swapper/2511:00:2018
271169913230,69cyclictest0-21swapper/2511:57:1918
271169913230,60cyclictest0-21swapper/2512:30:0818
271169913226,62cyclictest0-21swapper/2511:11:0218
270619913216,82cyclictest0-21swapper/1610:37:178
270289913219,82cyclictest0-21swapper/812:16:2030
27000991320,83cyclictest0-21swapper/309:36:1923
27000991320,83cyclictest0-21swapper/309:36:1923
271169913127,62cyclictest0-21swapper/2507:40:1418
271549913046,79cyclictest0-21swapper/3011:30:5324
271169913029,63cyclictest0-21swapper/2512:39:1318
271629912945,51cyclictest0-21swapper/3109:20:3025
271629912945,51cyclictest0-21swapper/3109:20:2925
271459912950,78cyclictest0-21swapper/2911:10:3322
271169912928,63cyclictest0-21swapper/2511:16:2318
271169912927,60cyclictest0-21swapper/2510:36:5018
271169912926,60cyclictest0-21swapper/2510:49:0618
27145991280,87cyclictest0-21swapper/2910:16:3522
271169912829,62cyclictest0-21swapper/2510:12:4618
270779912810,115cyclictest151rcu_preempt07:17:4513
27145991271,86cyclictest0-21swapper/2909:14:3522
27145991271,86cyclictest0-21swapper/2909:14:3422
271169912727,57cyclictest0-21swapper/2509:05:2618
271169912727,57cyclictest0-21swapper/2509:05:2618
270839912712,77cyclictest0-21swapper/2111:11:2414
270289912718,84cyclictest32140-21sshd10:47:4430
270249912724,46cyclictest0-21swapper/710:50:2629
271629912645,56cyclictest0-21swapper/3110:21:5825
271309912644,51cyclictest0-21swapper/2712:34:1520
271249912614,62cyclictest10233-21taskset10:32:1719
27130991250,74cyclictest0-21swapper/2707:43:3220
271169912526,58cyclictest0-21swapper/2508:00:1518
270249912543,54cyclictest0-21swapper/709:46:1729
270249912540,57cyclictest0-21swapper/710:27:5829
27024991250,74cyclictest0-21swapper/712:30:2129
271629912452,58cyclictest0-21swapper/3112:20:3725
271169912427,57cyclictest0-21swapper/2508:30:1018
271169912427,57cyclictest0-21swapper/2508:30:0918
270249912425,61cyclictest0-21swapper/711:16:3629
271629912352,55cyclictest0-21swapper/3110:59:5425
271629912345,49cyclictest0-21swapper/3112:03:3025
271459912332,54cyclictest0-21swapper/2910:23:4722
271309912343,52cyclictest0-21swapper/2708:55:1920
271309912343,52cyclictest0-21swapper/2708:55:1920
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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