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2026-07-27 - 05:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Mon Jul 27, 2026 00:49:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891288280,6phc2sys0-21swapper/219:08:2712
256762283275,6sleep280-21swapper/2819:05:1621
3273912630,255ptp4l0-21swapper/119:07:111
29985991953,7cyclictest151rcu_preempt22:12:0712
29985991953,7cyclictest151rcu_preempt22:12:0712
30104991480,88cyclictest0-21swapper/1720:55:249
30104991480,87cyclictest0-21swapper/1700:15:189
30025991450,78cyclictest0-21swapper/721:50:1629
30104991430,86cyclictest0-21swapper/1723:02:059
30104991430,86cyclictest0-21swapper/1723:02:059
30008991430,88cyclictest0-21swapper/520:08:4327
268162141133,6sleep310-21swapper/3119:05:1925
30163991401,87cyclictest0-21swapper/2522:09:1818
30163991401,87cyclictest0-21swapper/2522:09:1818
30163991400,87cyclictest0-21swapper/2500:15:1318
301049914015,98cyclictest29770-21taskset19:31:479
300969914015,77cyclictest151rcu_preempt23:15:158
30008991400,83cyclictest0-21swapper/520:53:4627
299959914032,72cyclictest0-21swapper/323:01:5123
299959914032,72cyclictest0-21swapper/323:01:5123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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