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2026-11-01 - 02:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Sat Oct 31, 2026 12:49:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913370,330ptp4l0-21swapper/107:07:471
33999300101,195cyclictest151rcu_preempt09:35:0120
3339920219,130cyclictest0-21swapper/2610:43:5719
32693991786,75cyclictest178572latency09:25:198
333991571,135cyclictest0-21swapper/2610:45:2619
3339915019,35cyclictest0-21swapper/2612:12:3919
32716991498,83cyclictest0-21swapper/1908:22:1011
32716991498,83cyclictest0-21swapper/1908:22:1011
3339914819,128cyclictest0-21swapper/2611:52:2219
3339914819,119cyclictest0-21swapper/2611:02:3819
3339914819,114cyclictest0-21swapper/2610:26:1919
3339914818,123cyclictest11913-21sshd11:35:1519
327169914860,66cyclictest0-21swapper/1912:11:2811
3339914719,107cyclictest0-21swapper/2608:30:2019
3339914719,107cyclictest0-21swapper/2608:30:2019
3339914718,106cyclictest0-21swapper/2608:10:0119
326799914744,63cyclictest0-21swapper/1412:14:366
326799914742,72cyclictest0-21swapper/1410:02:036
3339914618,98cyclictest0-21swapper/2610:13:2919
3339914419,77cyclictest0-21swapper/2612:33:3119
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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