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2026-01-27 - 15:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Tue Jan 27, 2026 12:48:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913280,319ptp4l0-21swapper/107:09:441
45419918625,98cyclictest0-21swapper/2510:50:1418
45419918625,98cyclictest0-21swapper/2510:50:1418
45279917031,86cyclictest0-21swapper/2212:05:0015
45279916918,128cyclictest0-21swapper/2211:35:2115
45279916918,128cyclictest0-21swapper/2211:35:2115
45279916121,98cyclictest0-21swapper/2209:48:4315
44769915427,121cyclictest0-21swapper/1011:58:242
44769915427,121cyclictest0-21swapper/1011:58:242
44769915328,79cyclictest0-21swapper/1009:40:302
44769915228,85cyclictest0-21swapper/1009:35:402
44769915228,78cyclictest0-21swapper/1010:11:302
4445991450,86cyclictest0-21swapper/407:20:0326
45419914451,69cyclictest0-21swapper/2511:53:1818
45419914451,69cyclictest0-21swapper/2511:53:1818
44769914216,111cyclictest0-21swapper/1009:27:402
45659914154,58cyclictest0-21swapper/3007:51:4924
4445991410,83cyclictest0-21swapper/409:44:4226
45659914055,59cyclictest0-21swapper/3011:48:3324
45659914055,59cyclictest0-21swapper/3011:48:3324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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