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2026-09-10 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Thu Sep 10, 2026 12:49:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
606499324126,1cyclictest151rcu_preempt09:10:5111
606499324126,1cyclictest151rcu_preempt09:10:5111
3273913160,309ptp4l0-21swapper/107:09:191
61359922428,1cyclictest151rcu_preempt10:27:3121
45432149142,6sleep00-21swapper/007:06:510
6020991480,87cyclictest0-21swapper/1307:46:525
6014991460,85cyclictest0-21swapper/1210:05:364
6014991460,85cyclictest0-21swapper/1210:05:364
59649914247,50cyclictest151rcu_preempt10:32:5312
61279914142,61cyclictest0-21swapper/2712:17:3120
6127991410,82cyclictest0-21swapper/2709:21:0920
6127991410,82cyclictest0-21swapper/2709:21:0920
6014991410,88cyclictest0-21swapper/1210:40:204
5979991398,70cyclictest0-21swapper/507:18:0327
6014991370,86cyclictest0-21swapper/1211:12:544
5979991370,83cyclictest0-21swapper/511:03:5627
61279913231,67cyclictest0-21swapper/2709:46:4720
61279913231,67cyclictest0-21swapper/2709:46:4720
61279913230,68cyclictest0-21swapper/2709:51:3720
61279913230,68cyclictest0-21swapper/2709:51:3620
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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