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2026-03-13 - 18:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Fri Mar 13, 2026 12:49:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273912730,266ptp4l0-21swapper/107:05:411
3273912730,266ptp4l0-21swapper/107:05:411
330891261249,9phc2sys0-21swapper/207:05:1612
330891261249,9phc2sys0-21swapper/207:05:1612
3096299218153,1cyclictest151rcu_preempt12:22:0224
3096299218153,1cyclictest151rcu_preempt12:22:0224
308959921417,1cyclictest151rcu_preempt11:45:2113
308959921417,1cyclictest151rcu_preempt11:45:2013
30822991800,87cyclictest0-21swapper/1010:15:192
309089916733,56cyclictest0-21swapper/2209:20:1115
308649915018,122cyclictest0-21swapper/1610:33:438
309629914928,90cyclictest0-21swapper/3010:53:5124
309629914928,120cyclictest0-21swapper/3011:58:3224
309629914928,120cyclictest0-21swapper/3011:58:3124
309629914828,73cyclictest0-21swapper/3010:45:1824
309629914827,115cyclictest0-21swapper/3010:04:0824
309629914825,91cyclictest0-21swapper/3011:27:3224
309629914825,91cyclictest0-21swapper/3011:27:3124
309629914732,112cyclictest0-21swapper/3012:17:1424
309629914732,112cyclictest0-21swapper/3012:17:1324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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