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2025-05-03 - 01:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Fri May 02, 2025 12:49:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265559918634,97cyclictest0-21swapper/2611:33:4219
265559918130,102cyclictest0-21swapper/2610:04:5919
265579916942,126cyclictest0-21swapper/2710:07:4020
2482911690,161ptp4l0-21swapper/107:08:281
2482911690,161ptp4l0-21swapper/107:08:281
265579916337,92cyclictest0-21swapper/2711:20:2120
265579916032,127cyclictest0-21swapper/2712:20:1220
264919916058,92cyclictest0-21swapper/1412:04:286
264919916058,92cyclictest0-21swapper/1412:04:286
329891158149,6phc2sys0-21swapper/207:05:2312
329891158149,6phc2sys0-21swapper/207:05:2312
264959915824,86cyclictest0-21swapper/1510:45:257
265579915326,80cyclictest0-21swapper/2708:40:0120
265559915124,80cyclictest0-21swapper/2612:31:2519
2645799151150,1cyclictest151rcu_preempt12:12:3728
265579915024,86cyclictest0-21swapper/2710:35:2720
264579914732,114cyclictest0-21swapper/610:08:0128
265559914422,86cyclictest0-21swapper/2612:05:1319
264919914441,101cyclictest0-21swapper/1408:28:376
264579914432,83cyclictest0-21swapper/612:15:2028
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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