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2026-06-12 - 00:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Thu Jun 11, 2026 12:49:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913280,313ptp4l0-21swapper/107:05:231
223259932081,39cyclictest106-21ksoftirqd/1509:18:477
2225299317131,1cyclictest151rcu_preempt09:48:5226
223829924038,5cyclictest151rcu_preempt11:38:5918
22228991973,39cyclictest13-21ksoftirqd/010:10:110
222639914052,59cyclictest0-21swapper/611:26:3728
2225299140129,3cyclictest151rcu_preempt12:13:3626
222639913954,60cyclictest0-21swapper/611:42:2528
222639913947,56cyclictest0-21swapper/609:17:0128
222639913827,66cyclictest0-21swapper/607:49:2428
222639913827,66cyclictest0-21swapper/607:49:2428
223979913720,66cyclictest151rcu_preempt08:40:1921
222639913756,57cyclictest0-21swapper/609:30:2428
222639913726,63cyclictest0-21swapper/607:44:3628
222639913726,63cyclictest0-21swapper/607:44:3528
22403991360,79cyclictest0-21swapper/2912:05:1522
222639913649,56cyclictest0-21swapper/609:13:1728
222639913639,60cyclictest0-21swapper/610:55:2328
222639913630,69cyclictest0-21swapper/612:32:3928
222639913629,61cyclictest0-21swapper/611:52:3328
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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