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2025-09-04 - 06:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Thu Sep 04, 2025 00:49:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
196029920732,119cyclictest0-21swapper/3020:55:1924
2482911630,155ptp4l0-21swapper/119:09:181
196029915538,79cyclictest0-21swapper/3000:23:4424
196029915333,85cyclictest0-21swapper/3000:12:4924
19456991516,118cyclictest151rcu_preempt23:18:540
19456991516,118cyclictest151rcu_preempt23:18:540
196029914938,94cyclictest0-21swapper/3022:50:1424
196029914938,94cyclictest0-21swapper/3022:50:1424
196029914930,90cyclictest0-21swapper/3000:38:0924
194629914847,70cyclictest0-21swapper/123:36:131
194629914847,70cyclictest0-21swapper/123:36:131
194629914846,73cyclictest0-21swapper/122:48:071
194629914846,73cyclictest0-21swapper/122:48:071
196029914728,84cyclictest0-21swapper/3023:05:1024
196029914728,84cyclictest0-21swapper/3023:05:1024
196029914323,32cyclictest0-21swapper/3021:53:3324
195139914317,79cyclictest0-21swapper/1000:35:412
135762143134,7sleep100-21swapper/1019:05:122
195249914231,63cyclictest0-21swapper/1322:04:175
19553991410,86cyclictest0-21swapper/2000:00:0113
19553991410,86cyclictest0-21swapper/2000:00:0113
196029914022,90cyclictest0-21swapper/3022:05:1924
196029914022,105cyclictest0-21swapper/3022:16:3224
195249914031,63cyclictest0-21swapper/1321:35:255
19602991387,66cyclictest151rcu_preempt20:00:0024
19524991363,80cyclictest0-21swapper/1320:41:115
195249913629,66cyclictest0-21swapper/1300:10:375
196029913524,75cyclictest0-21swapper/3000:01:1624
196029913524,75cyclictest0-21swapper/3000:01:1624
195139913517,117cyclictest0-21swapper/1019:50:202
194629913533,81cyclictest0-21swapper/122:38:301
194629913533,81cyclictest0-21swapper/122:38:301
196029913431,59cyclictest0-21swapper/3022:44:1924
195539913410,74cyclictest0-21swapper/2000:13:1913
194629913431,13cyclictest0-21swapper/123:21:461
194629913431,13cyclictest0-21swapper/123:21:461
19456991341,80cyclictest0-21swapper/000:36:050
19609991330,86cyclictest0-21swapper/3122:09:5025
19456991330,72cyclictest0-21swapper/021:15:260
195249913244,53cyclictest0-21swapper/1320:26:425
195249913227,61cyclictest0-21swapper/1323:10:145
195249913227,61cyclictest0-21swapper/1323:10:135
194629913231,50cyclictest0-21swapper/123:46:221
19609991318,112cyclictest151rcu_preempt20:08:5025
195249913128,62cyclictest0-21swapper/1322:33:535
194629913132,46cyclictest0-21swapper/123:05:131
194629913132,46cyclictest0-21swapper/123:05:121
194569913173,56cyclictest32321-21taskset19:17:500
195809913045,72cyclictest0-21swapper/2522:16:1118
195809913045,55cyclictest0-21swapper/2523:44:0618
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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