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2026-09-02 - 08:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Wed Sep 02, 2026 00:49:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
160329948487,198cyclictest151rcu_preempt22:48:5217
160329948487,198cyclictest151rcu_preempt22:48:5117
330891275266,6phc2sys0-21swapper/219:05:1412
1599199260171,55cyclictest0-21swapper/1920:04:4811
3273912480,240ptp4l0-21swapper/119:08:531
159609918429,141cyclictest0-21swapper/1321:38:165
159609917530,92cyclictest0-21swapper/1322:32:465
159609917530,92cyclictest0-21swapper/1322:32:465
159609917334,119cyclictest0-21swapper/1319:45:205
158809917153,88cyclictest0-21swapper/222:30:1512
158809917153,88cyclictest0-21swapper/222:30:1412
160449917021,91cyclictest0-21swapper/2622:30:1919
160449917021,91cyclictest0-21swapper/2622:30:1819
1588099161108,52cyclictest28-21ksoftirqd/222:11:5012
1588099161108,52cyclictest28-21ksoftirqd/222:11:5012
159609915333,77cyclictest0-21swapper/1323:17:095
160519915042,56cyclictest151rcu_preempt19:10:2021
15890991460,83cyclictest0-21swapper/421:29:3526
15915991440,85cyclictest0-21swapper/720:15:1929
160519914244,44cyclictest151rcu_preempt19:45:0221
15915991420,84cyclictest0-21swapper/719:20:1729
15890991400,82cyclictest0-21swapper/419:25:2326
159609913946,57cyclictest0-21swapper/1323:07:305
15890991390,81cyclictest0-21swapper/422:10:3126
15890991390,81cyclictest0-21swapper/422:10:3026
159499913848,58cyclictest0-21swapper/1122:30:043
159499913848,58cyclictest0-21swapper/1122:30:033
15949991381,80cyclictest0-21swapper/1122:59:593
15890991380,82cyclictest0-21swapper/423:45:1226
158709913832,72cyclictest0-21swapper/021:56:000
158709913832,72cyclictest0-21swapper/021:56:000
159609913752,61cyclictest0-21swapper/1300:37:385
159609913748,59cyclictest0-21swapper/1323:26:135
158709913732,83cyclictest0-21swapper/021:20:460
158709913730,75cyclictest0-21swapper/023:15:060
159609913654,59cyclictest0-21swapper/1300:26:565
159609913648,59cyclictest0-21swapper/1323:23:005
159609913629,67cyclictest0-21swapper/1320:47:305
159609913628,63cyclictest0-21swapper/1322:41:525
159609913628,63cyclictest0-21swapper/1322:41:525
159609913627,67cyclictest0-21swapper/1320:56:345
159499913631,72cyclictest0-21swapper/1119:20:383
158909913649,60cyclictest0-21swapper/400:17:2526
158909913624,72cyclictest0-21swapper/400:08:0526
158809913623,61cyclictest0-21swapper/222:20:5012
158809913623,61cyclictest0-21swapper/222:20:4912
158759913649,61cyclictest0-21swapper/100:23:441
158759913626,109cyclictest0-21swapper/121:33:141
158709913632,50cyclictest0-21swapper/021:15:230
159609913554,59cyclictest0-21swapper/1320:25:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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