You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-05 - 14:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Thu Mar 05, 2026 00:48:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
330891287279,6phc2sys0-21swapper/219:09:1112
330891287279,6phc2sys0-21swapper/219:09:1112
3273912450,237ptp4l0-21swapper/119:06:191
3273912450,237ptp4l0-21swapper/119:06:181
77039919033,94cyclictest0-21swapper/1819:30:1510
76549918531,121cyclictest0-21swapper/1121:40:283
76549918429,154cyclictest0-21swapper/1121:16:093
76549918327,141cyclictest0-21swapper/1123:48:303
76549918327,141cyclictest0-21swapper/1123:48:293
7722991700,167cyclictest143-21ksoftirqd/2121:14:1214
76549916021,103cyclictest0-21swapper/1122:12:173
77229914931,84cyclictest1630-21taskset22:19:0814
77229914728,84cyclictest0-21swapper/2121:34:3014
76619914730,116cyclictest0-21swapper/1219:25:224
76549914622,71cyclictest0-21swapper/1122:55:023
7590991460,84cyclictest0-21swapper/122:00:531
7722991450,84cyclictest0-21swapper/2122:00:0914
76479914526,36cyclictest0-21swapper/1019:55:282
7601991440,89cyclictest0-21swapper/319:28:5023
7722991430,84cyclictest0-21swapper/2100:26:0414
77039914353,85cyclictest0-21swapper/1823:33:0710
77039914353,85cyclictest0-21swapper/1823:33:0610
76549914232,68cyclictest0-21swapper/1100:26:323
76479914125,92cyclictest0-21swapper/1023:56:042
76619913924,114cyclictest0-21swapper/1200:30:144
76619913824,91cyclictest0-21swapper/1222:35:154
76619913723,113cyclictest0-21swapper/1200:35:204
75909913735,31cyclictest0-21swapper/100:32:001
75909913729,37cyclictest0-21swapper/123:10:541
75909913729,37cyclictest0-21swapper/123:10:541
7722991360,83cyclictest0-21swapper/2122:58:2514
7722991360,81cyclictest0-21swapper/2122:45:3614
7722991360,81cyclictest0-21swapper/2122:45:3514
76549913529,62cyclictest0-21swapper/1120:25:243
76549913527,66cyclictest0-21swapper/1123:15:223
76549913527,66cyclictest0-21swapper/1123:15:223
75909913554,64cyclictest0-21swapper/123:30:101
75909913554,64cyclictest0-21swapper/123:30:091
75909913545,57cyclictest0-21swapper/122:42:361
75909913545,57cyclictest0-21swapper/122:42:361
77229913433,77cyclictest0-21swapper/2123:17:0714
77229913433,77cyclictest0-21swapper/2123:17:0714
7661991347,74cyclictest0-21swapper/1223:35:314
76549913429,73cyclictest0-21swapper/1119:20:123
7670991339,82cyclictest0-21swapper/1300:17:565
76619913322,81cyclictest0-21swapper/1221:17:074
76549913329,72cyclictest0-21swapper/1119:25:153
76479913320,105cyclictest0-21swapper/1021:39:472
75909913347,76cyclictest0-21swapper/122:37:461
75909913332,67cyclictest0-21swapper/100:01:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional