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2026-04-19 - 21:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Sun Apr 19, 2026 12:49:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94929924547,2cyclictest151rcu_preempt10:35:5020
93809922115,198cyclictest151rcu_preempt09:52:0923
93809922115,198cyclictest151rcu_preempt09:52:0923
93659920938,127cyclictest0-21swapper/009:46:300
93659920938,127cyclictest0-21swapper/009:46:300
9482991849,125cyclictest0-21swapper/2411:10:2017
94879918113,148cyclictest0-21swapper/2511:53:0418
94879918013,155cyclictest0-21swapper/2509:20:2718
94879918013,155cyclictest0-21swapper/2509:20:2718
3273911790,170ptp4l0-21swapper/107:09:571
94879917813,164cyclictest0-21swapper/2512:35:2118
94879917813,148cyclictest0-21swapper/2508:55:1618
94879917813,148cyclictest0-21swapper/2508:55:1618
94879917613,155cyclictest0-21swapper/2511:55:5918
94879917413,121cyclictest0-21swapper/2509:15:0618
94879917413,121cyclictest0-21swapper/2509:15:0618
9365991700,37cyclictest0-21swapper/012:17:160
948799163161,1cyclictest167-21ksoftirqd/2510:34:1218
9370991616,98cyclictest151rcu_preempt08:30:051
93659915920,135cyclictest151rcu_preempt09:30:340
93659915920,135cyclictest151rcu_preempt09:30:340
94879915813,119cyclictest30248-21taskset12:07:2818
94259915851,69cyclictest151rcu_preempt07:59:524
94259915648,66cyclictest151rcu_preempt11:37:554
93659915530,85cyclictest0-21swapper/008:05:160
93659915512,138cyclictest0-21swapper/009:52:030
93659915512,138cyclictest0-21swapper/009:52:030
93659915430,88cyclictest0-21swapper/009:10:130
93659915430,88cyclictest0-21swapper/009:10:130
93659915330,74cyclictest0-21swapper/011:06:120
946399150148,1cyclictest131-21ksoftirqd/1909:27:1711
946399150148,1cyclictest131-21ksoftirqd/1909:27:1711
94879914751,67cyclictest151rcu_preempt11:06:4818
93659914633,109cyclictest151rcu_preempt11:41:110
93659914632,57cyclictest0-21swapper/007:55:230
9422991452,110cyclictest0-21swapper/1110:23:083
9482991447,104cyclictest0-21swapper/2410:06:5917
9482991427,134cyclictest0-21swapper/2409:10:0117
9482991427,134cyclictest0-21swapper/2409:10:0117
94639914250,82cyclictest0-21swapper/1910:32:4411
9482991417,98cyclictest0-21swapper/2412:20:2217
9482991417,100cyclictest0-21swapper/2408:55:1517
9482991417,100cyclictest0-21swapper/2408:55:1517
9482991416,109cyclictest0-21swapper/2410:55:2217
94259914117,103cyclictest151rcu_preempt12:00:064
9482991397,93cyclictest0-21swapper/2409:33:0317
9482991397,93cyclictest0-21swapper/2409:33:0317
9391991370,82cyclictest0-21swapper/512:15:5727
9370991370,83cyclictest0-21swapper/111:23:301
9370991370,83cyclictest0-21swapper/109:36:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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