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2025-12-05 - 06:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Fri Dec 05, 2025 00:49:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482912620,253ptp4l0-21swapper/119:05:471
53529921842,173cyclictest151rcu_preempt21:19:0631
5424991991,1cyclictest151rcu_preempt23:09:1417
5424991963,181cyclictest161-21ksoftirqd/2421:00:2917
53979917645,130cyclictest0-21swapper/1820:11:2110
5424991745,140cyclictest161-21ksoftirqd/2423:11:5117
5348991666,0cyclictest64-21ksoftirqd/800:33:1130
53979916231,106cyclictest0-21swapper/1800:15:3710
54199915216,111cyclictest0-21swapper/2321:40:3516
54249915017,100cyclictest0-21swapper/2400:30:2917
53169914913,115cyclictest0-21swapper/121:25:391
53579914730,95cyclictest0-21swapper/1000:25:392
5357991470,85cyclictest0-21swapper/1000:34:432
5340991470,87cyclictest0-21swapper/621:34:3428
5340991460,86cyclictest0-21swapper/623:17:4228
5316991449,125cyclictest0-21swapper/123:47:331
54249914330,109cyclictest9516-21cut21:20:0117
5340991430,86cyclictest0-21swapper/622:37:3628
5340991420,85cyclictest0-21swapper/621:45:4628
5340991410,83cyclictest0-21swapper/623:12:2128
5357991400,82cyclictest0-21swapper/1021:21:482
53409914048,60cyclictest0-21swapper/622:19:5828
53579913927,69cyclictest0-21swapper/1019:14:372
53579913927,69cyclictest0-21swapper/1019:14:372
5419991380,86cyclictest0-21swapper/2321:07:3316
53579913853,61cyclictest0-21swapper/1022:33:572
53579913828,69cyclictest0-21swapper/1020:40:152
53579913827,110cyclictest0-21swapper/1021:17:002
5357991380,87cyclictest0-21swapper/1000:17:382
5357991380,80cyclictest0-21swapper/1000:10:082
53409913849,58cyclictest0-21swapper/621:44:4228
53409913848,59cyclictest0-21swapper/621:51:0828
53409913847,57cyclictest0-21swapper/622:48:4928
5340991380,86cyclictest0-21swapper/621:28:4028
5340991380,84cyclictest0-21swapper/623:20:2328
5340991380,83cyclictest0-21swapper/600:31:3728
5411991375,130cyclictest0-21swapper/2123:16:2014
5340991370,85cyclictest0-21swapper/622:07:1028
5340991370,80cyclictest0-21swapper/622:10:2128
5357991360,84cyclictest0-21swapper/1022:18:412
53409913644,58cyclictest0-21swapper/600:01:0028
53409913627,69cyclictest0-21swapper/622:26:2328
5340991360,84cyclictest0-21swapper/622:21:3428
5316991361,98cyclictest0-21swapper/122:35:231
5419991350,81cyclictest0-21swapper/2322:49:3316
53579913543,62cyclictest0-21swapper/1022:20:342
5357991350,79cyclictest0-21swapper/1019:25:202
5357991350,79cyclictest0-21swapper/1019:25:192
53409913553,59cyclictest0-21swapper/621:15:2328
54289913449,57cyclictest167-21ksoftirqd/2522:17:5518
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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