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2026-01-19 - 09:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Mon Jan 19, 2026 00:48:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3273913410,310ptp4l0-21swapper/119:05:131
3273913410,310ptp4l0-21swapper/119:05:121
330891311302,7phc2sys0-21swapper/219:05:1712
330891311302,7phc2sys0-21swapper/219:05:1712
207489919953,1cyclictest151rcu_preempt00:07:2431
207489919953,1cyclictest151rcu_preempt00:07:2331
207969915245,33cyclictest143-21ksoftirqd/2121:58:4714
193562146138,6sleep280-21swapper/2819:07:0621
193562146138,6sleep280-21swapper/2819:07:0621
20801991452,21cyclictest0-21swapper/2222:02:3215
20796991440,82cyclictest0-21swapper/2123:15:4514
20801991430,90cyclictest0-21swapper/2222:38:5315
20801991421,28cyclictest0-21swapper/2223:12:0115
208289914025,88cyclictest0-21swapper/2819:10:2221
207969913837,25cyclictest0-21swapper/2119:20:2414
207969913755,56cyclictest0-21swapper/2123:25:5414
207969913752,59cyclictest0-21swapper/2121:43:4914
20712991370,132cyclictest0-21swapper/321:19:2823
20776991360,84cyclictest0-21swapper/1623:45:378
20776991360,84cyclictest0-21swapper/1623:45:368
20756991360,81cyclictest0-21swapper/1123:05:253
208379913553,60cyclictest0-21swapper/3020:59:3624
208379913545,59cyclictest0-21swapper/3021:48:4724
208289913540,61cyclictest0-21swapper/2821:19:1421
20792991350,80cyclictest0-21swapper/2020:05:0013
20756991355,106cyclictest0-21swapper/1122:31:503
20712991350,84cyclictest0-21swapper/300:10:3123
20712991350,84cyclictest0-21swapper/300:10:3023
208379913446,53cyclictest0-21swapper/3023:27:0824
208289913427,106cyclictest0-21swapper/2822:00:1921
20792991340,85cyclictest0-21swapper/2023:53:3713
20792991340,85cyclictest0-21swapper/2023:53:3713
20792991340,82cyclictest0-21swapper/2019:50:2713
20756991346,107cyclictest0-21swapper/1123:10:143
207969913352,57cyclictest0-21swapper/2123:55:5114
207969913352,57cyclictest0-21swapper/2123:55:5014
207969913352,55cyclictest0-21swapper/2122:35:4014
207969913342,55cyclictest0-21swapper/2119:10:2714
20712991330,86cyclictest34-21ksoftirqd/319:13:5323
208379913247,56cyclictest0-21swapper/3020:15:3124
208379913240,67cyclictest0-21swapper/3000:16:4924
208379913240,67cyclictest0-21swapper/3000:16:4924
208289913249,62cyclictest0-21swapper/2821:43:2021
208289913246,59cyclictest0-21swapper/2819:20:1621
208289913244,58cyclictest0-21swapper/2821:29:5021
208289913243,60cyclictest0-21swapper/2822:36:1421
207969913252,58cyclictest0-21swapper/2120:15:0614
207969913250,56cyclictest0-21swapper/2122:07:5314
207969913250,52cyclictest0-21swapper/2121:35:4914
207969913227,69cyclictest0-21swapper/2100:33:4714
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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