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2025-06-17 - 01:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Mon Jun 16, 2025 12:49:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482912350,220ptp4l0-21swapper/107:05:241
201849917119,97cyclictest0-21swapper/1110:56:553
201849917019,109cyclictest0-21swapper/1110:05:363
201849917019,109cyclictest0-21swapper/1110:05:363
201849916817,124cyclictest0-21swapper/1111:55:143
329891164156,6phc2sys0-21swapper/207:05:2112
201889915832,111cyclictest0-21swapper/1212:32:054
201889915732,124cyclictest0-21swapper/1209:40:174
201889915732,124cyclictest0-21swapper/1209:40:174
201889915729,121cyclictest0-21swapper/1210:50:004
201889915628,127cyclictest0-21swapper/1207:20:214
201889914718,128cyclictest0-21swapper/1209:29:044
201889914718,128cyclictest0-21swapper/1209:29:044
201849914613,129cyclictest151rcu_preempt12:05:213
201889914530,69cyclictest0-21swapper/1210:53:374
20208991440,87cyclictest0-21swapper/1607:15:018
201889914418,99cyclictest0-21swapper/1209:10:214
20281991430,113cyclictest0-21swapper/2910:27:1722
20281991430,113cyclictest0-21swapper/2910:27:1622
201889914135,62cyclictest0-21swapper/1209:58:594
201889914135,62cyclictest0-21swapper/1209:58:594
20281991390,86cyclictest0-21swapper/2909:41:2022
20281991390,86cyclictest0-21swapper/2909:41:1922
201849913819,73cyclictest0-21swapper/1110:40:523
20208991371,85cyclictest0-21swapper/1610:58:238
20184991370,84cyclictest0-21swapper/1108:25:403
201699913522,76cyclictest0-21swapper/711:44:2429
201699913447,59cyclictest0-21swapper/707:53:3229
201699913348,57cyclictest0-21swapper/712:03:3929
20241991320,85cyclictest0-21swapper/2111:27:0014
201699913150,57cyclictest0-21swapper/710:44:1329
201699913142,56cyclictest0-21swapper/710:50:2529
201699913128,70cyclictest0-21swapper/709:46:4929
201699913128,70cyclictest0-21swapper/709:46:4929
201699913126,61cyclictest0-21swapper/711:20:2129
20208991300,81cyclictest0-21swapper/1610:44:418
201699913049,60cyclictest0-21swapper/711:34:1529
201699913029,69cyclictest0-21swapper/710:05:1729
201699913029,69cyclictest0-21swapper/710:05:1629
201699913028,68cyclictest0-21swapper/710:58:3529
201699913027,67cyclictest0-21swapper/707:36:5929
201699912929,69cyclictest0-21swapper/707:30:0229
201699912929,67cyclictest0-21swapper/707:10:1629
201699912928,65cyclictest0-21swapper/708:59:4829
20169991290,73cyclictest0-21swapper/709:30:4529
20169991290,73cyclictest0-21swapper/709:30:4529
2022599128127,1cyclictest0-21swapper/1912:01:1911
201889912835,59cyclictest0-21swapper/1210:02:124
201889912828,60cyclictest0-21swapper/1212:05:394
20173991280,75cyclictest0-21swapper/809:36:1130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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