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2025-08-29 - 11:59

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8s.osadl.org (updated Fri Aug 29, 2025 00:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46462950,0sleep00-21swapper/022:01:570
2120916352,6phc2sys0-21swapper/319:07:193
2120916251,6phc2sys0-21swapper/719:08:557
114091610,30ptp4l0-21swapper/019:05:540
114091600,5ptp4l0-21swapper/519:05:215
114091600,29ptp4l0-21swapper/119:06:451
761025545,6sleep60-21swapper/619:05:506
780525139,7sleep20-21swapper/219:08:182
759724634,7sleep40-21swapper/419:05:394
114091350,0ptp4l0-21swapper/522:00:175
114091340,0ptp4l0-21swapper/620:25:016
114091330,0ptp4l0-21swapper/519:20:175
114091330,0ptp4l0-21swapper/119:50:221
114091320,0ptp4l0-21swapper/120:50:171
114091320,0ptp4l0-21swapper/100:25:161
114091310,0ptp4l0-21swapper/521:54:425
114091310,0ptp4l0-21swapper/123:28:451
114091310,0ptp4l0-21swapper/122:25:191
114091310,0ptp4l0-21swapper/023:00:130
114091300,0ptp4l31424-21diskmemload21:42:255
114091300,0ptp4l0-21swapper/523:19:005
114091300,0ptp4l0-21swapper/520:00:235
114091300,0ptp4l0-21swapper/121:34:201
114091300,0ptp4l0-21swapper/021:45:210
114091300,0ptp4l0-21swapper/019:20:180
114091290,0ptp4l31424-21diskmemload22:15:161
114091290,0ptp4l0-21swapper/523:22:415
114091290,0ptp4l0-21swapper/522:46:305
114091290,0ptp4l0-21swapper/521:36:215
114091290,0ptp4l0-21swapper/521:11:025
114091290,0ptp4l0-21swapper/421:12:374
114091290,0ptp4l0-21swapper/123:15:191
114091290,0ptp4l0-21swapper/100:10:011
114091290,0ptp4l0-21swapper/021:30:530
114091290,0ptp4l0-21swapper/020:50:190
823299288,15cyclictest0-21swapper/500:10:125
114091280,2ptp4l0-21swapper/023:22:480
114091280,0ptp4l0-21swapper/722:48:137
114091280,0ptp4l0-21swapper/623:24:416
114091280,0ptp4l0-21swapper/523:32:405
114091280,0ptp4l0-21swapper/523:32:395
114091280,0ptp4l0-21swapper/523:03:135
114091280,0ptp4l0-21swapper/521:34:155
114091280,0ptp4l0-21swapper/323:20:443
114091280,0ptp4l0-21swapper/123:55:391
114091280,0ptp4l0-21swapper/119:25:171
114091280,0ptp4l0-21swapper/023:42:500
114091280,0ptp4l0-21swapper/021:57:130
823299278,15cyclictest17049-21kworker/5:223:53:075
114091270,0ptp4l31424-21diskmemload21:21:431
114091270,0ptp4l0-21swapper/621:15:576
114091270,0ptp4l0-21swapper/523:12:175
114091270,0ptp4l0-21swapper/521:56:195
114091270,0ptp4l0-21swapper/519:26:315
114091270,0ptp4l0-21swapper/519:15:175
114091270,0ptp4l0-21swapper/422:28:144
114091270,0ptp4l0-21swapper/421:30:574
114091270,0ptp4l0-21swapper/421:00:184
114091270,0ptp4l0-21swapper/321:19:503
114091270,0ptp4l0-21swapper/222:40:242
114091270,0ptp4l0-21swapper/123:51:111
114091270,0ptp4l0-21swapper/123:35:471
114091270,0ptp4l0-21swapper/123:14:431
114091270,0ptp4l0-21swapper/121:53:531
114091260,2ptp4l0-21swapper/522:36:525
114091260,2ptp4l0-21swapper/500:18:105
114091260,0ptp4l0-21swapper/722:34:597
114091260,0ptp4l0-21swapper/621:24:146
114091260,0ptp4l0-21swapper/523:27:535
114091260,0ptp4l0-21swapper/522:31:005
114091260,0ptp4l0-21swapper/522:20:195
114091260,0ptp4l0-21swapper/423:43:354
114091260,0ptp4l0-21swapper/423:37:184
114091260,0ptp4l0-21swapper/423:30:254
114091260,0ptp4l0-21swapper/423:30:244
114091260,0ptp4l0-21swapper/422:10:574
114091260,0ptp4l0-21swapper/421:28:454
114091260,0ptp4l0-21swapper/400:23:564
114091260,0ptp4l0-21swapper/122:55:141
114091260,0ptp4l0-21swapper/122:53:591
114091260,0ptp4l0-21swapper/122:44:401
114091260,0ptp4l0-21swapper/122:30:231
114091260,0ptp4l0-21swapper/121:38:141
114091260,0ptp4l0-21swapper/120:11:411
114091260,0ptp4l0-21swapper/100:20:511
114091260,0ptp4l0-21swapper/023:50:150
114091260,0ptp4l0-21swapper/000:37:390
114091250,1ptp4l6890-21irqstats00:25:185
114091250,0ptp4l0-21swapper/622:06:226
114091250,0ptp4l0-21swapper/523:41:465
114091250,0ptp4l0-21swapper/522:50:215
114091250,0ptp4l0-21swapper/519:40:165
114091250,0ptp4l0-21swapper/500:30:195
114091250,0ptp4l0-21swapper/500:21:415
114091250,0ptp4l0-21swapper/422:00:124
114091250,0ptp4l0-21swapper/322:05:173
114091250,0ptp4l0-21swapper/300:20:183
114091250,0ptp4l0-21swapper/123:47:311
114091250,0ptp4l0-21swapper/121:45:351
114091250,0ptp4l0-21swapper/121:44:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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