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2025-12-21 - 05:13

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8s.osadl.org (updated Sun Dec 21, 2025 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1361426434,6sleep70-21swapper/719:07:567
111391640,6ptp4l0-21swapper/019:06:040
53902610,0sleep00-21swapper/021:10:100
162592610,0sleep70-21swapper/719:15:007
111391610,5ptp4l0-21swapper/419:06:424
1349525937,7sleep10-21swapper/119:06:221
276832560,0sleep20-21swapper/219:35:212
1881915633,7phc2sys0-21swapper/519:06:425
1187925242,6sleep20-21swapper/219:05:102
1344524624,7sleep60-21swapper/619:05:466
1342424635,7sleep30-21swapper/319:05:273
111391310,4ptp4l0-21swapper/520:05:175
111391310,4ptp4l0-21swapper/520:05:175
111391280,2ptp4l0-21swapper/322:50:203
111391280,0ptp4l0-21swapper/020:35:130
111391270,0ptp4l0-21swapper/321:55:193
111391270,0ptp4l0-21swapper/022:05:250
111391270,0ptp4l0-21swapper/020:10:150
111391260,0ptp4l0-21swapper/422:15:134
111391260,0ptp4l0-21swapper/100:12:111
111391250,1ptp4l5550-21irqrtprio22:20:155
111391250,0ptp4l0-21swapper/500:15:135
111391250,0ptp4l0-21swapper/320:54:293
111391250,0ptp4l0-21swapper/121:00:131
111391250,0ptp4l0-21swapper/023:20:010
111391240,1ptp4l2682-21df_inode23:25:134
111391240,1ptp4l24057-21fw_conntrack20:40:127
111391240,1ptp4l15253-21irqstats20:20:181
111391240,1ptp4l10392-21smart_sda23:40:194
111391240,0ptp4l0-21swapper/523:35:155
111391240,0ptp4l0-21swapper/520:15:565
111391240,0ptp4l0-21swapper/423:45:184
111391240,0ptp4l0-21swapper/423:10:114
111391240,0ptp4l0-21swapper/423:05:204
111391240,0ptp4l0-21swapper/422:10:124
111391240,0ptp4l0-21swapper/421:50:004
111391240,0ptp4l0-21swapper/420:35:164
111391240,0ptp4l0-21swapper/223:25:172
111391240,0ptp4l0-21swapper/122:00:121
111391240,0ptp4l0-21swapper/121:40:191
111391240,0ptp4l0-21swapper/121:15:171
111391240,0ptp4l0-21swapper/119:20:191
111391240,0ptp4l0-21swapper/100:39:591
111391230,1ptp4l25166-21sed19:30:217
111391230,1ptp4l23185-21cpuspeed_turbos00:10:114
111391230,1ptp4l11997-21ls21:25:004
111391230,0ptp4l0-21swapper/721:55:007
111391230,0ptp4l0-21swapper/719:15:277
111391230,0ptp4l0-21swapper/623:30:216
111391230,0ptp4l0-21swapper/523:50:165
111391230,0ptp4l0-21swapper/522:30:145
111391230,0ptp4l0-21swapper/521:40:205
111391230,0ptp4l0-21swapper/521:30:205
111391230,0ptp4l0-21swapper/521:15:005
111391230,0ptp4l0-21swapper/519:25:165
111391230,0ptp4l0-21swapper/423:40:004
111391230,0ptp4l0-21swapper/422:25:204
111391230,0ptp4l0-21swapper/421:35:194
111391230,0ptp4l0-21swapper/421:05:164
111391230,0ptp4l0-21swapper/420:22:344
111391230,0ptp4l0-21swapper/400:20:124
111391230,0ptp4l0-21swapper/322:50:013
111391230,0ptp4l0-21swapper/322:50:003
111391230,0ptp4l0-21swapper/321:45:113
111391230,0ptp4l0-21swapper/123:35:001
111391230,0ptp4l0-21swapper/122:30:211
111391230,0ptp4l0-21swapper/121:10:181
111391230,0ptp4l0-21swapper/120:05:201
111391230,0ptp4l0-21swapper/120:05:201
111391230,0ptp4l0-21swapper/119:25:221
111391230,0ptp4l0-21swapper/022:45:220
111391230,0ptp4l0-21swapper/022:45:210
111391230,0ptp4l0-21swapper/022:40:010
111391230,0ptp4l0-21swapper/022:25:170
111391230,0ptp4l0-21swapper/021:05:200
111391230,0ptp4l0-21swapper/020:40:160
111391230,0ptp4l0-21swapper/020:25:220
111391230,0ptp4l0-21swapper/019:25:230
111391230,0ptp4l0-21swapper/000:35:190
111391220,0ptp4l26270-21latency_hist19:35:004
111391220,0ptp4l20533-21sensors19:20:185
111391220,0ptp4l0-21swapper/723:10:207
111391220,0ptp4l0-21swapper/722:50:167
111391220,0ptp4l0-21swapper/721:55:117
111391220,0ptp4l0-21swapper/721:45:217
111391220,0ptp4l0-21swapper/720:50:177
111391220,0ptp4l0-21swapper/719:30:007
111391220,0ptp4l0-21swapper/623:00:206
111391220,0ptp4l0-21swapper/600:30:156
111391220,0ptp4l0-21swapper/522:43:565
111391220,0ptp4l0-21swapper/522:35:215
111391220,0ptp4l0-21swapper/521:08:105
111391220,0ptp4l0-21swapper/520:45:155
111391220,0ptp4l0-21swapper/520:30:165
111391220,0ptp4l0-21swapper/520:20:215
111391220,0ptp4l0-21swapper/519:45:145
111391220,0ptp4l0-21swapper/500:05:175
111391220,0ptp4l0-21swapper/423:55:174
111391220,0ptp4l0-21swapper/423:30:124
111391220,0ptp4l0-21swapper/423:20:204
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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