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2026-02-05 - 09:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackcslot8s.osadl.org (updated Thu Feb 05, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
111391750,5ptp4l0-21swapper/019:05:100
1067826736,16sleep30-21swapper/319:05:213
111391610,29ptp4l0-21swapper/119:05:551
1881916050,6phc2sys0-21swapper/219:05:312
1077526050,6sleep70-21swapper/719:05:507
199412550,0sleep60-21swapper/621:32:066
111391510,5ptp4l0-21swapper/519:09:345
1078125040,6sleep40-21swapper/419:05:554
1077424635,6sleep60-21swapper/619:05:486
137762430,0sleep50-21swapper/519:15:005
111391360,1ptp4l19705-21memory23:45:160
111391340,0ptp4l0-21swapper/021:50:590
111391330,0ptp4l6933-21ssh00:14:021
111391330,0ptp4l0-21swapper/120:05:121
111391320,2ptp4l0-21swapper/121:19:281
111391320,0ptp4l0-21swapper/122:42:071
111391310,3ptp4l0-21swapper/121:58:581
111391310,0ptp4l0-21swapper/023:10:070
111391300,0ptp4l0-21swapper/422:46:144
111391290,3ptp4l0-21swapper/400:32:284
111391290,2ptp4l0-21swapper/022:27:170
111391290,0ptp4l0-21swapper/523:34:215
111391290,0ptp4l0-21swapper/422:51:434
111391290,0ptp4l0-21swapper/123:17:431
111391290,0ptp4l0-21swapper/122:50:061
111391290,0ptp4l0-21swapper/122:00:091
111391290,0ptp4l0-21swapper/021:16:350
111391280,0ptp4l0-21swapper/100:18:261
111391280,0ptp4l0-21swapper/022:37:030
111391280,0ptp4l0-21swapper/019:15:150
111391270,2ptp4l0-21swapper/000:22:220
111391270,1ptp4l0-21swapper/422:29:544
111391270,0ptp4l0-21swapper/523:16:485
111391270,0ptp4l0-21swapper/500:20:535
111391270,0ptp4l0-21swapper/423:42:274
111391270,0ptp4l0-21swapper/423:22:054
111391270,0ptp4l0-21swapper/123:01:081
111391270,0ptp4l0-21swapper/122:36:331
111391270,0ptp4l0-21swapper/023:36:140
111391270,0ptp4l0-21swapper/022:23:310
111391270,0ptp4l0-21swapper/022:18:280
111391270,0ptp4l0-21swapper/000:33:380
111391270,0ptp4l0-21swapper/000:25:070
111391260,4ptp4l9-21ksoftirqd/000:20:000
111391260,0ptp4l0-21swapper/719:48:067
111391260,0ptp4l0-21swapper/520:15:195
111391260,0ptp4l0-21swapper/123:33:211
111391260,0ptp4l0-21swapper/122:55:191
111391260,0ptp4l0-21swapper/122:24:101
111391260,0ptp4l0-21swapper/120:20:191
111391260,0ptp4l0-21swapper/023:31:090
111391260,0ptp4l0-21swapper/023:26:360
111391260,0ptp4l0-21swapper/021:36:560
111391260,0ptp4l0-21swapper/019:35:180
111391250,1ptp4l19169-21df_inode23:45:124
111391250,1ptp4l13737-21cut19:15:010
111391250,1ptp4l13399-21sed20:20:205
111391250,0ptp4l0-21swapper/523:35:125
111391250,0ptp4l0-21swapper/522:40:125
111391250,0ptp4l0-21swapper/522:15:125
111391250,0ptp4l0-21swapper/521:18:425
111391250,0ptp4l0-21swapper/520:05:095
111391250,0ptp4l0-21swapper/423:55:164
111391250,0ptp4l0-21swapper/423:14:564
111391250,0ptp4l0-21swapper/423:05:184
111391250,0ptp4l0-21swapper/422:34:534
111391250,0ptp4l0-21swapper/421:50:124
111391250,0ptp4l0-21swapper/421:41:264
111391250,0ptp4l0-21swapper/421:00:154
111391250,0ptp4l0-21swapper/420:55:144
111391250,0ptp4l0-21swapper/419:15:014
111391250,0ptp4l0-21swapper/122:15:101
111391250,0ptp4l0-21swapper/121:22:381
111391250,0ptp4l0-21swapper/119:11:471
111391250,0ptp4l0-21swapper/100:35:571
111391250,0ptp4l0-21swapper/100:31:191
111391250,0ptp4l0-21swapper/100:28:541
111391250,0ptp4l0-21swapper/023:50:130
111391250,0ptp4l0-21swapper/022:56:510
111391250,0ptp4l0-21swapper/022:06:220
111391250,0ptp4l0-21swapper/022:06:210
111391250,0ptp4l0-21swapper/021:55:200
111391250,0ptp4l0-21swapper/000:38:020
111391240,2ptp4l0-21swapper/000:05:270
111391240,1ptp4l9160-21sensors23:30:184
111391240,1ptp4l6759-21df21:15:124
111391240,1ptp4l530-21conntrack21:05:140
111391240,1ptp4l29216-21ps21:45:154
111391240,1ptp4l12338-21irqrtprio23:35:151
111391240,0ptp4l0-21swapper/523:09:105
111391240,0ptp4l0-21swapper/522:00:185
111391240,0ptp4l0-21swapper/521:38:065
111391240,0ptp4l0-21swapper/520:25:215
111391240,0ptp4l0-21swapper/520:10:145
111391240,0ptp4l0-21swapper/519:25:135
111391240,0ptp4l0-21swapper/519:25:135
111391240,0ptp4l0-21swapper/500:35:505
111391240,0ptp4l0-21swapper/422:18:194
111391240,0ptp4l0-21swapper/422:10:404
111391240,0ptp4l0-21swapper/421:56:484
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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