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2025-11-30 - 14:39

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Sun Nov 30, 2025 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114091690,30ptp4l0-21swapper/019:05:190
2120916252,6phc2sys0-21swapper/219:05:102
3097726050,6sleep70-21swapper/719:09:217
114091570,5ptp4l0-21swapper/419:07:244
89532560,0sleep10-21swapper/121:35:161
108292550,0sleep71093-21runrttasks21:38:037
3098425432,7sleep30-21swapper/319:09:253
2120915443,6phc2sys0-21swapper/619:09:406
3098025140,6sleep10-21swapper/119:09:231
114091470,6ptp4l0-21swapper/519:05:155
114091360,0ptp4l0-21swapper/521:25:185
114091320,0ptp4l0-21swapper/523:30:155
114091320,0ptp4l0-21swapper/500:15:155
114091320,0ptp4l0-21swapper/122:55:141
114091310,0ptp4l0-21swapper/520:45:175
114091310,0ptp4l0-21swapper/100:03:241
114091300,0ptp4l0-21swapper/621:05:006
114091300,0ptp4l0-21swapper/520:00:185
114091300,0ptp4l0-21swapper/022:05:490
114091290,0ptp4l0-21swapper/622:41:506
114091290,0ptp4l0-21swapper/622:28:116
114091290,0ptp4l0-21swapper/600:02:286
114091290,0ptp4l0-21swapper/522:41:355
114091290,0ptp4l0-21swapper/521:11:095
114091290,0ptp4l0-21swapper/121:26:051
114091290,0ptp4l0-21swapper/023:43:240
114091290,0ptp4l0-21swapper/023:35:500
114091290,0ptp4l0-21swapper/020:30:200
114091280,0ptp4l0-21swapper/623:39:186
114091280,0ptp4l0-21swapper/523:46:045
114091280,0ptp4l0-21swapper/520:50:155
114091280,0ptp4l0-21swapper/221:16:332
114091280,0ptp4l0-21swapper/100:14:421
114091270,0ptp4l0-21swapper/623:48:136
114091270,0ptp4l0-21swapper/523:52:185
114091270,0ptp4l0-21swapper/523:25:365
114091270,0ptp4l0-21swapper/522:58:455
114091270,0ptp4l0-21swapper/522:15:055
114091270,0ptp4l0-21swapper/521:47:085
114091270,0ptp4l0-21swapper/423:36:134
114091270,0ptp4l0-21swapper/421:13:374
114091270,0ptp4l0-21swapper/420:42:054
114091270,0ptp4l0-21swapper/222:45:242
114091270,0ptp4l0-21swapper/222:33:082
114091270,0ptp4l0-21swapper/123:46:471
114091270,0ptp4l0-21swapper/023:29:010
114091260,2ptp4l1796-21cut00:30:010
114091260,0ptp4l0-21swapper/623:15:246
114091260,0ptp4l0-21swapper/522:25:345
114091260,0ptp4l0-21swapper/522:09:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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