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2026-01-21 - 13:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Wed Jan 21, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1834026846,7sleep20-21swapper/219:08:182
302572660,0sleep00-21swapper/019:30:190
111391600,5ptp4l0-21swapper/119:06:291
111391590,5ptp4l0-21swapper/519:08:115
1881915533,7phc2sys0-21swapper/719:06:267
1822425332,7sleep30-21swapper/319:06:513
111391520,5ptp4l0-21swapper/419:05:084
125472510,0sleep30-21swapper/300:10:093
1832624937,7sleep60-21swapper/619:08:066
1813524533,7sleep00-21swapper/019:05:450
111391320,0ptp4l0-21swapper/500:19:415
111391320,0ptp4l0-21swapper/500:19:405
111391320,0ptp4l0-21swapper/423:09:334
111391320,0ptp4l0-21swapper/000:39:040
111391310,0ptp4l0-21swapper/523:20:165
111391310,0ptp4l0-21swapper/520:55:185
111391310,0ptp4l0-21swapper/423:39:564
111391310,0ptp4l0-21swapper/421:38:334
111391310,0ptp4l0-21swapper/421:38:324
111391310,0ptp4l0-21swapper/400:20:254
111391310,0ptp4l0-21swapper/023:09:000
111391300,2ptp4l0-21swapper/023:32:030
111391300,0ptp4l0-21swapper/423:29:534
111391300,0ptp4l0-21swapper/422:01:394
111391300,0ptp4l0-21swapper/400:07:444
111391300,0ptp4l0-21swapper/400:00:594
111391300,0ptp4l0-21swapper/322:22:313
111391300,0ptp4l0-21swapper/021:59:210
111391300,0ptp4l0-21swapper/021:43:280
111391300,0ptp4l0-21swapper/021:43:280
111391300,0ptp4l0-21swapper/000:25:110
111391290,3ptp4l0-21swapper/422:50:034
111391290,3ptp4l0-21swapper/020:30:160
111391290,2ptp4l0-21swapper/622:17:486
111391290,0ptp4l0-21swapper/523:25:175
111391290,0ptp4l0-21swapper/423:22:014
111391290,0ptp4l0-21swapper/423:02:104
111391290,0ptp4l0-21swapper/421:51:124
111391290,0ptp4l0-21swapper/421:44:054
111391290,0ptp4l0-21swapper/421:44:054
111391290,0ptp4l0-21swapper/421:21:294
111391290,0ptp4l0-21swapper/421:18:054
111391290,0ptp4l0-21swapper/022:20:060
111391290,0ptp4l0-21swapper/021:45:000
111391290,0ptp4l0-21swapper/021:26:240
111391290,0ptp4l0-21swapper/021:21:590
111391280,3ptp4l101ktimersoftd/019:10:170
111391280,0ptp4l0-21swapper/622:21:406
111391280,0ptp4l0-21swapper/523:37:485
111391280,0ptp4l0-21swapper/523:32:365
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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