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2026-01-31 - 17:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Sat Jan 31, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
111391660,2ptp4l0-21swapper/007:05:210
111391620,5ptp4l0-21swapper/107:07:351
111391620,1ptp4l0-21swapper/407:05:234
113492610,0sleep30-21swapper/310:05:013
203022570,0sleep0101ktimersoftd/009:30:520
111391570,6ptp4l0-21swapper/507:09:015
1176825646,6sleep20-21swapper/207:06:062
1179225432,7sleep60-21swapper/607:06:266
1881915332,7phc2sys0-21swapper/307:09:073
1177525140,7sleep70-21swapper/707:06:117
111391340,0ptp4l0-21swapper/210:00:142
111391320,0ptp4l0-21swapper/412:01:104
111391320,0ptp4l0-21swapper/410:47:364
111391320,0ptp4l0-21swapper/011:38:060
111391310,3ptp4l0-21swapper/010:16:280
111391310,2ptp4l0-21swapper/012:00:160
111391310,0ptp4l0-21swapper/411:28:234
111391310,0ptp4l0-21swapper/408:45:194
111391310,0ptp4l0-21swapper/012:33:470
111391300,0ptp4l0-21swapper/711:37:007
111391300,0ptp4l0-21swapper/509:28:135
111391300,0ptp4l0-21swapper/411:30:204
12367992924,1cyclictest12338-21processes09:20:184
111391290,3ptp4l0-21swapper/412:15:174
111391290,0ptp4l0-21swapper/512:06:465
111391290,0ptp4l0-21swapper/508:30:135
111391290,0ptp4l0-21swapper/412:34:104
111391290,0ptp4l0-21swapper/412:24:504
111391290,0ptp4l0-21swapper/411:57:024
111391290,0ptp4l0-21swapper/411:48:424
111391290,0ptp4l0-21swapper/410:43:384
111391290,0ptp4l0-21swapper/410:22:084
111391290,0ptp4l0-21swapper/408:59:574
111391290,0ptp4l0-21swapper/012:23:110
111391290,0ptp4l0-21swapper/012:08:100
111391290,0ptp4l0-21swapper/011:56:390
111391290,0ptp4l0-21swapper/009:13:370
111391280,0ptp4l0-21swapper/512:25:505
111391280,0ptp4l0-21swapper/512:15:525
111391280,0ptp4l0-21swapper/412:12:044
111391280,0ptp4l0-21swapper/412:06:024
111391280,0ptp4l0-21swapper/411:35:064
111391280,0ptp4l0-21swapper/409:16:544
111391280,0ptp4l0-21swapper/211:56:182
111391280,0ptp4l0-21swapper/011:52:050
111391280,0ptp4l0-21swapper/011:29:340
111391280,0ptp4l0-21swapper/011:23:570
111391280,0ptp4l0-21swapper/010:38:390
111391280,0ptp4l0-21swapper/009:59:400
111391270,3ptp4l0-21swapper/011:14:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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