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2026-02-10 - 17:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Tue Feb 10, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
111391720,28ptp4l0-21swapper/107:05:151
89892630,0sleep10-21swapper/109:55:171
111391620,5ptp4l0-21swapper/007:07:180
111391600,5ptp4l0-21swapper/507:06:285
111391600,5ptp4l0-21swapper/407:07:224
1558525747,6sleep70-21swapper/707:09:127
149262570,0sleep20-21swapper/212:19:062
268762560,0sleep30-21swapper/311:50:153
1563025433,6sleep60-21swapper/607:09:436
1545025242,6sleep20-21swapper/207:07:312
1529624735,7sleep30-21swapper/307:05:313
111391330,0ptp4l0-21swapper/109:28:501
111391320,0ptp4l0-21swapper/512:20:155
111391320,0ptp4l0-21swapper/111:46:431
111391310,0ptp4l0-21swapper/511:00:075
111391310,0ptp4l0-21swapper/112:09:121
111391310,0ptp4l0-21swapper/111:05:011
111391300,1ptp4l1590399cyclictest09:51:250
111391300,0ptp4l0-21swapper/412:14:114
111391300,0ptp4l0-21swapper/411:58:544
111391300,0ptp4l0-21swapper/112:21:181
111391300,0ptp4l0-21swapper/111:51:331
111391300,0ptp4l0-21swapper/107:55:191
111391290,4ptp4l0-21swapper/509:26:405
111391290,2ptp4l0-21swapper/509:23:125
111391290,0ptp4l0-21swapper/510:39:015
111391290,0ptp4l0-21swapper/411:42:284
111391290,0ptp4l0-21swapper/410:57:304
111391290,0ptp4l0-21swapper/410:36:314
111391290,0ptp4l0-21swapper/409:43:334
111391290,0ptp4l0-21swapper/409:36:524
111391290,0ptp4l0-21swapper/009:37:480
111391280,2ptp4l0-21swapper/510:41:115
111391280,2ptp4l0-21swapper/510:30:495
111391280,0ptp4l0-21swapper/710:25:137
111391280,0ptp4l0-21swapper/710:25:127
111391280,0ptp4l0-21swapper/610:04:226
111391280,0ptp4l0-21swapper/512:19:595
111391280,0ptp4l0-21swapper/510:51:045
111391280,0ptp4l0-21swapper/509:13:465
111391280,0ptp4l0-21swapper/411:39:074
111391280,0ptp4l0-21swapper/411:14:104
111391280,0ptp4l0-21swapper/411:09:344
111391280,0ptp4l0-21swapper/407:30:204
111391270,1ptp4l25986-21ssh12:34:404
111391270,0ptp4l0-21swapper/512:00:365
111391270,0ptp4l0-21swapper/511:44:495
111391270,0ptp4l0-21swapper/509:51:495
111391270,0ptp4l0-21swapper/509:05:115
111391270,0ptp4l0-21swapper/412:00:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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