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2025-09-18 - 08:27

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Thu Sep 18, 2025 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114091730,0ptp4l32575-21df_inode22:55:141
2120917251,6phc2sys0-21swapper/319:09:133
194826746,6sleep60-21swapper/619:05:386
192926644,6sleep70-21swapper/719:05:237
114091620,5ptp4l0-21swapper/119:06:291
114091620,30ptp4l0-21swapper/019:05:420
114091610,12ptp4l0-21swapper/519:05:135
205225948,6sleep20-21swapper/219:06:532
114091570,5ptp4l0-21swapper/419:05:564
184522550,0sleep50-21swapper/500:06:145
322272540,0sleep0111rcuc/000:26:360
114091330,0ptp4l0-21swapper/522:30:165
114091320,0ptp4l0-21swapper/522:15:205
114091320,0ptp4l0-21swapper/400:32:114
114091320,0ptp4l0-21swapper/121:15:131
114091310,0ptp4l0-21swapper/421:00:174
114091310,0ptp4l0-21swapper/122:29:361
114091300,0ptp4l0-21swapper/520:00:175
114091300,0ptp4l0-21swapper/123:53:011
114091300,0ptp4l0-21swapper/021:00:150
114091290,3ptp4l0-21swapper/100:18:221
114091290,0ptp4l0-21swapper/522:39:265
114091290,0ptp4l0-21swapper/521:54:105
114091290,0ptp4l0-21swapper/500:20:135
114091290,0ptp4l0-21swapper/323:51:413
114091280,0ptp4l0-21swapper/522:00:025
114091280,0ptp4l0-21swapper/519:25:105
114091280,0ptp4l0-21swapper/500:25:515
114091280,0ptp4l0-21swapper/121:48:311
114091280,0ptp4l0-21swapper/021:43:310
114091280,0ptp4l0-21swapper/021:15:410
114091270,0ptp4l0-21swapper/500:32:155
114091270,0ptp4l0-21swapper/123:45:471
114091270,0ptp4l0-21swapper/123:45:471
114091270,0ptp4l0-21swapper/122:08:011
114091270,0ptp4l0-21swapper/121:52:031
114091270,0ptp4l0-21swapper/100:20:591
114091260,0ptp4l0-21swapper/523:01:445
114091260,0ptp4l0-21swapper/522:41:045
114091260,0ptp4l0-21swapper/500:03:285
114091260,0ptp4l0-21swapper/422:07:234
114091260,0ptp4l0-21swapper/123:56:451
114091260,0ptp4l0-21swapper/122:40:121
114091260,0ptp4l0-21swapper/122:19:461
114091260,0ptp4l0-21swapper/121:43:331
114091260,0ptp4l0-21swapper/121:38:351
114091260,0ptp4l0-21swapper/121:27:351
114091260,0ptp4l0-21swapper/120:05:191
114091260,0ptp4l0-21swapper/022:52:540
114091260,0ptp4l0-21swapper/022:14:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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