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2026-01-18 - 13:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Sun Jan 18, 2026 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53502720,0sleep10-21swapper/121:15:181
996726645,6sleep70-21swapper/719:05:437
996726645,6sleep70-21swapper/719:05:427
111391630,24ptp4l0-21swapper/019:05:200
111391630,24ptp4l0-21swapper/019:05:190
111391620,31ptp4l0-21swapper/119:08:181
111391620,31ptp4l0-21swapper/119:08:181
1881916050,6phc2sys0-21swapper/219:08:072
1881916050,6phc2sys0-21swapper/219:08:062
1030926050,6sleep40-21swapper/419:09:574
1030926050,6sleep40-21swapper/419:09:564
40592590,1sleep5551rcuc/522:41:435
111391590,5ptp4l0-21swapper/519:08:485
111391590,5ptp4l0-21swapper/519:08:475
117482530,0sleep20-21swapper/219:10:172
1015125230,6sleep60-21swapper/619:07:586
1015125230,6sleep60-21swapper/619:07:586
241492480,0sleep10-21swapper/123:55:011
1004524735,7sleep30-21swapper/319:06:433
1004524735,7sleep30-21swapper/319:06:433
111391350,0ptp4l0-21swapper/123:45:001
111391340,0ptp4l0-21swapper/419:20:194
111391340,0ptp4l0-21swapper/122:35:171
111391330,0ptp4l0-21swapper/023:12:150
111391320,0ptp4l0-21swapper/423:59:054
111391320,0ptp4l0-21swapper/422:30:154
111391320,0ptp4l0-21swapper/421:53:004
111391320,0ptp4l0-21swapper/421:42:504
111391320,0ptp4l0-21swapper/421:42:504
111391320,0ptp4l0-21swapper/123:02:181
111391320,0ptp4l0-21swapper/022:00:140
111391310,1ptp4l49-21ksoftirqd/422:25:124
111391310,0ptp4l0-21swapper/423:28:594
111391310,0ptp4l0-21swapper/022:15:390
111391310,0ptp4l0-21swapper/022:13:150
111391300,0ptp4l0-21swapper/721:45:117
111391300,0ptp4l0-21swapper/423:50:374
111391300,0ptp4l0-21swapper/422:16:204
111391300,0ptp4l0-21swapper/421:58:564
111391300,0ptp4l0-21swapper/022:35:500
1058499308,11cyclictest0-21swapper/022:25:040
111391290,3ptp4l0-21swapper/423:10:544
111391290,2ptp4l0-21swapper/100:32:131
111391290,0ptp4l0-21swapper/723:33:427
111391290,0ptp4l0-21swapper/400:10:414
111391290,0ptp4l0-21swapper/023:05:400
111391290,0ptp4l0-21swapper/022:08:580
111391290,0ptp4l0-21swapper/021:51:110
111391280,3ptp4l0-21swapper/400:37:474
111391280,2ptp4l0-21swapper/021:34:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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