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2026-07-23 - 05:16

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Thu Jul 23, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180692630,0sleep70-21swapper/721:39:547
426926150,6sleep70-21swapper/719:06:247
111391590,5ptp4l0-21swapper/419:06:204
111391570,5ptp4l0-21swapper/019:07:350
149202560,0sleep60-21swapper/622:18:386
1881915332,7phc2sys0-21swapper/119:08:051
104162520,0sleep50-21swapper/520:30:165
438325141,6sleep20-21swapper/219:07:482
445124837,6sleep60-21swapper/619:08:406
434724736,7sleep30-21swapper/319:07:243
1881914634,7phc2sys0-21swapper/519:09:395
111391320,0ptp4l0-21swapper/123:20:201
111391310,0ptp4l0-21swapper/123:01:431
111391300,0ptp4l0-21swapper/100:31:201
111391290,0ptp4l0-21swapper/522:45:035
111391290,0ptp4l0-21swapper/522:45:035
111391290,0ptp4l0-21swapper/423:42:524
111391290,0ptp4l0-21swapper/422:57:554
111391290,0ptp4l0-21swapper/422:38:514
111391290,0ptp4l0-21swapper/422:04:124
111391290,0ptp4l0-21swapper/421:43:544
111391290,0ptp4l0-21swapper/421:39:504
111391290,0ptp4l0-21swapper/400:39:004
111391290,0ptp4l0-21swapper/121:38:281
111391290,0ptp4l0-21swapper/021:49:170
111391290,0ptp4l0-21swapper/020:15:160
111391290,0ptp4l0-21swapper/019:45:190
111391290,0ptp4l0-21swapper/000:28:470
111391280,0ptp4l0-21swapper/423:06:494
111391280,0ptp4l0-21swapper/322:36:493
111391280,0ptp4l0-21swapper/122:42:021
111391280,0ptp4l0-21swapper/122:22:561
111391280,0ptp4l0-21swapper/100:29:191
111391280,0ptp4l0-21swapper/023:16:420
111391280,0ptp4l0-21swapper/022:43:060
111391280,0ptp4l0-21swapper/021:51:470
111391280,0ptp4l0-21swapper/021:43:340
111391270,0ptp4l17735-21ssh22:21:194
111391270,0ptp4l0-21swapper/721:42:027
111391270,0ptp4l0-21swapper/423:56:464
111391270,0ptp4l0-21swapper/423:45:424
111391270,0ptp4l0-21swapper/423:32:294
111391270,0ptp4l0-21swapper/423:24:364
111391270,0ptp4l0-21swapper/422:25:504
111391270,0ptp4l0-21swapper/400:25:364
111391270,0ptp4l0-21swapper/400:03:244
111391270,0ptp4l0-21swapper/123:55:161
111391270,0ptp4l0-21swapper/121:50:211
111391270,0ptp4l0-21swapper/121:11:311
111391270,0ptp4l0-21swapper/120:20:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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