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2026-04-18 - 17:35

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Sat Apr 18, 2026 12:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
279772710,0sleep20-21swapper/210:21:082
210452640,0sleep50-21swapper/510:11:185
111391620,5ptp4l0-21swapper/407:08:544
111391620,28ptp4l0-21swapper/107:06:381
111391600,29ptp4l0-21swapper/007:06:540
72382590,0sleep60-21swapper/610:39:156
1703825747,6sleep70-21swapper/707:09:397
6022560,0sleep60-21swapper/609:44:276
1677825332,6sleep20-21swapper/207:06:122
1706324837,6sleep60-21swapper/607:09:546
1504124836,7sleep30-21swapper/307:05:023
1672624736,7sleep50-21swapper/507:05:365
1737699407,11cyclictest0-21swapper/507:39:555
111391320,0ptp4l0-21swapper/412:35:014
111391320,0ptp4l0-21swapper/009:15:130
111391310,0ptp4l0-21swapper/511:25:125
111391310,0ptp4l0-21swapper/508:45:155
111391310,0ptp4l0-21swapper/010:44:560
111391310,0ptp4l0-21swapper/009:33:050
111391300,0ptp4l0-21swapper/507:20:125
111391300,0ptp4l0-21swapper/411:37:144
111391300,0ptp4l0-21swapper/410:15:194
111391300,0ptp4l0-21swapper/409:33:404
111391300,0ptp4l0-21swapper/012:27:100
111391300,0ptp4l0-21swapper/012:13:250
111391290,3ptp4l0-21swapper/510:47:385
111391290,0ptp4l0-21swapper/412:21:304
111391290,0ptp4l0-21swapper/411:05:174
111391290,0ptp4l0-21swapper/409:25:114
111391290,0ptp4l0-21swapper/109:56:091
111391290,0ptp4l0-21swapper/011:26:530
111391280,3ptp4l0-21swapper/412:08:164
111391280,0ptp4l0-21swapper/511:59:305
111391280,0ptp4l0-21swapper/511:39:235
111391280,0ptp4l0-21swapper/411:43:304
111391280,0ptp4l0-21swapper/411:43:304
111391280,0ptp4l0-21swapper/409:49:374
111391280,0ptp4l0-21swapper/409:12:364
111391280,0ptp4l0-21swapper/407:10:164
111391280,0ptp4l0-21swapper/310:26:523
111391280,0ptp4l0-21swapper/012:40:000
111391280,0ptp4l0-21swapper/012:33:280
111391280,0ptp4l0-21swapper/012:07:260
111391280,0ptp4l0-21swapper/011:10:120
111391280,0ptp4l0-21swapper/010:51:380
111391280,0ptp4l0-21swapper/009:55:030
111391280,0ptp4l0-21swapper/007:15:180
111391270,0ptp4l0-21swapper/512:39:105
111391270,0ptp4l0-21swapper/511:46:345
111391270,0ptp4l0-21swapper/509:22:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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