You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-07 - 18:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Sat Feb 07, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218222650,0sleep20-21swapper/207:40:172
111391620,5ptp4l0-21swapper/407:05:514
571725937,7sleep10-21swapper/107:07:251
559525949,6sleep70-21swapper/707:05:547
562825533,7sleep30-21swapper/307:06:143
1881915533,7phc2sys0-21swapper/007:05:260
563625443,7sleep20-21swapper/207:06:222
111391540,5ptp4l0-21swapper/507:06:525
62212500,0sleep60-21swapper/609:20:176
563124837,6sleep60-21swapper/607:06:176
111391380,0ptp4l0-21swapper/010:50:140
111391380,0ptp4l0-21swapper/010:50:140
111391350,0ptp4l0-21swapper/510:50:195
111391350,0ptp4l0-21swapper/510:50:195
111391330,9ptp4l0-21swapper/511:02:215
111391330,0ptp4l0-21swapper/512:35:555
111391330,0ptp4l0-21swapper/508:00:115
111391320,0ptp4l0-21swapper/711:30:147
111391320,0ptp4l0-21swapper/507:10:145
111391320,0ptp4l0-21swapper/411:20:114
111391310,0ptp4l0-21swapper/508:30:195
111391310,0ptp4l0-21swapper/411:44:184
111391310,0ptp4l0-21swapper/410:25:174
111391310,0ptp4l0-21swapper/410:00:194
111391310,0ptp4l0-21swapper/110:21:111
111391310,0ptp4l0-21swapper/010:25:320
111391300,2ptp4l0-21swapper/412:25:144
111391300,0ptp4l0-21swapper/511:50:195
111391300,0ptp4l0-21swapper/511:10:415
111391300,0ptp4l0-21swapper/107:35:201
111391300,0ptp4l0-21swapper/012:21:410
111391300,0ptp4l0-21swapper/011:20:280
111391290,2ptp4l0-21swapper/012:10:490
111391290,0ptp4l0-21swapper/512:03:045
111391290,0ptp4l0-21swapper/410:51:134
111391290,0ptp4l0-21swapper/410:51:124
111391290,0ptp4l0-21swapper/409:58:464
111391290,0ptp4l0-21swapper/408:20:174
111391290,0ptp4l0-21swapper/208:05:152
111391290,0ptp4l0-21swapper/012:19:200
111391290,0ptp4l0-21swapper/011:35:140
111391290,0ptp4l0-21swapper/010:01:460
111391290,0ptp4l0-21swapper/009:56:010
111391290,0ptp4l0-21swapper/009:35:140
111391280,2ptp4l0-21swapper/108:00:181
111391280,0ptp4l0-21swapper/508:50:125
111391280,0ptp4l0-21swapper/412:18:184
111391280,0ptp4l0-21swapper/411:37:354
111391280,0ptp4l0-21swapper/409:25:324
111391280,0ptp4l0-21swapper/409:21:074
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional