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2026-02-17 - 18:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Tue Feb 17, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247652790,0sleep50-21swapper/509:00:195
111391670,0ptp4l14810-21fw_conntrack09:35:111
398926339,7sleep40-21swapper/407:06:304
111391630,5ptp4l0-21swapper/707:07:247
1881916138,7phc2sys0-21swapper/007:08:010
419925343,6sleep20-21swapper/207:09:082
395725342,7sleep10-21swapper/107:06:031
395225232,6sleep50-21swapper/507:05:595
111391520,6ptp4l0-21swapper/307:08:113
403524736,6sleep60-21swapper/607:07:036
111391330,0ptp4l0-21swapper/409:29:324
111391310,0ptp4l0-21swapper/012:10:160
111391300,0ptp4l0-21swapper/512:15:145
111391300,0ptp4l0-21swapper/411:17:064
111391300,0ptp4l0-21swapper/409:23:314
111391300,0ptp4l0-21swapper/409:13:314
111391300,0ptp4l0-21swapper/408:55:124
111391300,0ptp4l0-21swapper/407:17:094
111391300,0ptp4l0-21swapper/010:25:200
111391290,0ptp4l0-21swapper/012:25:230
111391280,0ptp4l0-21swapper/711:04:427
111391280,0ptp4l0-21swapper/511:07:495
111391280,0ptp4l0-21swapper/411:01:204
111391280,0ptp4l0-21swapper/410:51:474
111391280,0ptp4l0-21swapper/410:45:124
111391280,0ptp4l0-21swapper/311:42:303
111391280,0ptp4l0-21swapper/012:16:350
111391280,0ptp4l0-21swapper/012:08:520
111391280,0ptp4l0-21swapper/010:16:530
111391280,0ptp4l0-21swapper/010:01:090
111391270,0ptp4l0-21swapper/711:50:247
111391270,0ptp4l0-21swapper/512:31:385
111391270,0ptp4l0-21swapper/510:33:405
111391270,0ptp4l0-21swapper/412:08:584
111391270,0ptp4l0-21swapper/411:26:404
111391270,0ptp4l0-21swapper/410:43:134
111391270,0ptp4l0-21swapper/312:26:283
111391270,0ptp4l0-21swapper/311:22:423
111391270,0ptp4l0-21swapper/310:57:423
111391270,0ptp4l0-21swapper/012:03:390
111391270,0ptp4l0-21swapper/011:59:460
111391270,0ptp4l0-21swapper/011:20:120
111391270,0ptp4l0-21swapper/011:05:120
111391260,0ptp4l0-21swapper/712:28:417
111391260,0ptp4l0-21swapper/711:42:187
111391260,0ptp4l0-21swapper/511:27:525
111391260,0ptp4l0-21swapper/510:58:335
111391260,0ptp4l0-21swapper/509:58:055
111391260,0ptp4l0-21swapper/509:47:035
111391260,0ptp4l0-21swapper/410:12:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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