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2026-03-03 - 20:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Tue Mar 03, 2026 12:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159522660,1sleep557-21ksoftirqd/511:53:555
111391620,31ptp4l0-21swapper/207:08:532
111391620,31ptp4l0-21swapper/007:06:330
1881916138,6phc2sys0-21swapper/407:07:394
289932600,0sleep40-21swapper/409:11:004
289932600,0sleep40-21swapper/409:10:594
170642590,0sleep00-21swapper/009:40:120
111391590,5ptp4l0-21swapper/107:05:221
224922580,0sleep10-21swapper/107:49:591
18832570,0sleep50-21swapper/509:19:595
264632550,0sleep20-21swapper/207:55:212
334125443,6sleep70-21swapper/707:09:467
111391540,5ptp4l0-21swapper/507:07:525
111391530,5ptp4l0-21swapper/607:08:596
102424634,7sleep30-21swapper/307:05:023
111391360,0ptp4l0-21swapper/508:25:115
111391360,0ptp4l0-21swapper/108:05:121
111391350,0ptp4l0-21swapper/109:44:151
111391340,0ptp4l0-21swapper/112:25:161
111391340,0ptp4l0-21swapper/011:50:160
111391320,0ptp4l0-21swapper/010:49:290
111391310,0ptp4l0-21swapper/009:10:440
111391310,0ptp4l0-21swapper/009:10:430
111391300,0ptp4l0-21swapper/511:19:195
111391300,0ptp4l0-21swapper/509:13:305
111391300,0ptp4l0-21swapper/509:13:305
111391300,0ptp4l0-21swapper/112:12:251
111391300,0ptp4l0-21swapper/012:34:170
111391300,0ptp4l0-21swapper/011:46:470
111391300,0ptp4l0-21swapper/011:46:470
111391300,0ptp4l0-21swapper/010:16:230
111391300,0ptp4l0-21swapper/010:07:030
111391300,0ptp4l0-21swapper/009:49:360
111391290,0ptp4l0-21swapper/511:40:215
111391290,0ptp4l0-21swapper/412:21:234
111391290,0ptp4l0-21swapper/410:34:264
111391290,0ptp4l0-21swapper/307:20:193
111391290,0ptp4l0-21swapper/111:51:291
111391290,0ptp4l0-21swapper/111:40:221
111391290,0ptp4l0-21swapper/012:37:410
111391290,0ptp4l0-21swapper/011:37:530
111391290,0ptp4l0-21swapper/011:25:040
111391290,0ptp4l0-21swapper/011:03:130
111391290,0ptp4l0-21swapper/008:58:300
111391280,0ptp4l0-21swapper/510:04:365
111391280,0ptp4l0-21swapper/411:44:194
111391280,0ptp4l0-21swapper/111:58:281
111391280,0ptp4l0-21swapper/109:27:551
111391280,0ptp4l0-21swapper/108:55:141
111391280,0ptp4l0-21swapper/108:15:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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