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2026-07-07 - 12:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 07, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25774992727,0cyclictest0-21swapper/222:20:142
25773992716,11cyclictest0-21swapper/121:28:131
25774992320,2cyclictest10206-21acpi23:30:122
2577499225,13cyclictest0-21swapper/223:01:122
25774992214,3cyclictest30661-21sort23:09:002
2577499220,18cyclictest0-21swapper/219:46:072
2577399220,0cyclictest0-21swapper/122:25:171
2577299220,4cyclictest0-21swapper/020:38:170
25774992115,3cyclictest0-21swapper/220:24:272
2577499210,3cyclictest0-21swapper/221:29:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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