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2026-09-04 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Sep 04, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31791992413,10cyclictest0-21swapper/123:10:211
3179099242,14cyclictest0-21swapper/021:15:080
3179099231,4cyclictest0-21swapper/019:15:010
31792992220,1cyclictest4311-21mii-tool23:05:152
3179299220,18cyclictest0-21swapper/223:20:002
3179299214,16cyclictest1856-21systemd-udevd21:02:512
3179299210,20cyclictest870-21systemd-logind22:06:512
3179099210,21cyclictest0-21swapper/021:35:160
3179299203,3cyclictest0-21swapper/219:29:512
3179299200,19cyclictest843-21systemd-network20:06:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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