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2026-04-21 - 06:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Apr 21, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14824993321,10cyclictest29847-21kworker/1:121:55:151
14824992818,0cyclictest0-21swapper/122:01:501
14820992216,3cyclictest9-21ksoftirqd/022:28:040
1482999210,20cyclictest843-21systemd-network22:00:462
1482499210,20cyclictest870-21systemd-logind23:18:511
1482499210,18cyclictest0-21swapper/123:59:231
14820992112,5cyclictest0-21swapper/020:45:020
1482099210,7cyclictest870-21systemd-logind20:23:520
14824992017,2cyclictest3976-21H222:10:211
1482099202,3cyclictest0-21swapper/023:34:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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