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2025-12-26 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Dec 26, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21130992514,2cyclictest3393-21pzem20:30:221
2113099240,6cyclictest25433-21if_lxdbr000:00:161
21130992315,7cyclictest0-21swapper/100:27:311
2113099220,3cyclictest0-21swapper/121:13:501
2113099220,19cyclictest0-21swapper/123:21:241
2112999220,5cyclictest0-21swapper/019:28:330
2112999213,2cyclictest0-21swapper/022:30:140
2112999210,20cyclictest843-21systemd-network20:18:260
21132992014,3cyclictest0-21swapper/222:15:162
2113099200,19cyclictest3296-21python300:20:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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