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2026-07-30 - 09:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 30, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14972992826,0cyclictest0-21swapper/123:27:131
14972992726,0cyclictest0-21swapper/121:16:361
14972992725,2cyclictest0-21swapper/122:56:351
14968992721,5cyclictest21168-21iwlist22:10:150
14972992625,0cyclictest0-21swapper/123:53:501
14972992625,0cyclictest0-21swapper/100:20:101
14972992616,10cyclictest0-21swapper/123:37:381
14972992524,0cyclictest0-21swapper/123:48:361
14972992524,0cyclictest0-21swapper/123:18:131
14972992524,0cyclictest0-21swapper/100:05:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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