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2026-02-21 - 01:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Feb 20, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5976992218,3cyclictest3058-21rs:main2
5975992222,0cyclictest0-21swapper/111:15:151
597599220,18cyclictest0-21swapper/111:40:141
597499220,21cyclictest0-21swapper/010:53:460
597599214,11cyclictest0-21swapper/110:27:591
5974992116,3cyclictest0-21swapper/009:15:030
5976992016,3cyclictest0-21swapper/209:08:492
5975992016,3cyclictest0-21swapper/109:07:271
597699192,1cyclictest0-21swapper/211:24:162
597599193,9cyclictest0-21swapper/111:33:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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