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2026-07-08 - 12:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 08, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27032992314,0cyclictest0-21swapper/219:25:162
27032992214,5cyclictest0-21swapper/219:17:542
2702399220,18cyclictest0-21swapper/023:57:100
2702399204,15cyclictest0-21swapper/020:56:500
27023992017,2cyclictest3983-21H222:10:210
27023992017,2cyclictest3053-21systemd-logind20:38:530
2702399201,4cyclictest31815-21cpuspeed_turbos20:15:150
2703299193,1cyclictest28-21ksoftirqd/222:53:472
27032991917,1cyclictest28-21ksoftirqd/221:57:512
27032991916,2cyclictest19171-21cpuspeed_turbos20:50:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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