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2026-01-02 - 21:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jan 02, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21676992414,10cyclictest0-21swapper/111:45:131
2167599242,21cyclictest0-21swapper/007:20:010
2167599240,18cyclictest23030-21nfsd411:55:190
2167599230,0cyclictest0-21swapper/011:20:130
21677992222,0cyclictest0-21swapper/209:44:522
2167699220,4cyclictest0-21swapper/108:18:081
2167799214,10cyclictest0-21swapper/207:28:202
21676992112,5cyclictest0-21swapper/111:38:391
2167799206,8cyclictest0-21swapper/207:55:012
21677992018,1cyclictest0-21swapper/210:16:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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