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2026-02-23 - 14:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 23, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2507299270,2cyclictest13347-21nfsd422:35:172
2507299246,17cyclictest0-21swapper/222:40:542
2507299240,19cyclictest4750-21perf19:30:012
25072992212,5cyclictest0-21swapper/220:48:422
2506399226,2cyclictest17165-21missed_timers23:40:170
2507299204,15cyclictest0-21swapper/220:25:022
2506399202,1cyclictest0-21swapper/020:32:070
25063992018,1cyclictest0-21swapper/023:15:000
25072991917,1cyclictest29071-21cat23:05:142
2507299190,18cyclictest0-21swapper/223:04:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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