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2026-03-03 - 00:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 02, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20882993129,2cyclictest0-21swapper/111:09:381
2088199263,18cyclictest0-21swapper/012:20:000
20881992523,1cyclictest14833-21mii-tool10:45:150
2088399230,5cyclictest0-21swapper/207:21:002
20882992119,1cyclictest16392-21date10:50:011
2088299210,1cyclictest0-21swapper/109:58:451
20881992117,3cyclictest0-21swapper/008:19:530
2088399204,15cyclictest0-21swapper/211:25:142
20882992016,3cyclictest0-21swapper/108:04:241
2088399192,2cyclictest8488-21cpuspeed_turbos10:35:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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