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2026-05-14 - 22:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu May 14, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3360993517,17cyclictest0-21swapper/007:30:120
336099240,0cyclictest0-21swapper/012:30:120
336799230,18cyclictest0-21swapper/111:43:391
336099220,18cyclictest0-21swapper/012:19:500
336799210,3cyclictest0-21swapper/107:25:181
336099210,3cyclictest11707-21nvmesmart_nvme012:05:170
336099210,20cyclictest0-21swapper/011:18:470
336099210,18cyclictest0-21swapper/008:55:190
336099204,15cyclictest0-21swapper/011:45:150
336099203,11cyclictest9359-21munin-run10:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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