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2026-04-03 - 10:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 03, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22293992525,0cyclictest0-21swapper/020:05:170
22294992414,10cyclictest0-21swapper/121:15:181
2229599237,15cyclictest0-21swapper/200:27:522
2229499230,23cyclictest0-21swapper/120:54:541
2229499230,23cyclictest0-21swapper/120:30:141
2229499220,18cyclictest0-21swapper/100:00:211
2229399220,0cyclictest0-21swapper/022:40:160
22295992117,3cyclictest0-21swapper/220:01:172
2229599210,20cyclictest843-21systemd-network22:51:362
2229499210,20cyclictest0-21swapper/119:38:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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