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2026-08-11 - 23:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 11, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1631899272,24cyclictest21-21ksoftirqd/111:45:161
16318992617,0cyclictest0-21swapper/107:10:091
16324992523,1cyclictest28-21ksoftirqd/207:15:142
16324992416,7cyclictest28-21ksoftirqd/208:00:482
1631499230,5cyclictest0-21swapper/011:25:090
1632499222,19cyclictest28-21ksoftirqd/207:59:522
1631499210,18cyclictest18039-21fschecks_time09:05:150
16324992016,1cyclictest0-21swapper/211:03:572
16318992018,1cyclictest21-21ksoftirqd/107:19:301
1631499204,15cyclictest0-21swapper/010:53:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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