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2026-02-22 - 03:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 21, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
930799236,16cyclictest4420-21cut09:50:161
930799230,5cyclictest0-21swapper/110:10:211
9307992222,0cyclictest11100-21mii-tool09:05:161
9307992215,3cyclictest0-21swapper/107:15:141
930799220,18cyclictest0-21swapper/109:00:151
931199210,5cyclictest0-21swapper/208:42:072
931199210,3cyclictest0-21swapper/211:10:302
930799212,17cyclictest0-21swapper/109:42:361
930799212,17cyclictest0-21swapper/109:42:361
9307992121,0cyclictest0-21swapper/110:55:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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