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2026-08-26 - 01:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 25, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2519899230,5cyclictest0-21swapper/211:10:132
2519499230,5cyclictest0-21swapper/011:22:460
2519899220,21cyclictest843-21systemd-network10:37:052
2519499226,2cyclictest3053-21systemd-logind08:28:520
2519499220,4cyclictest0-21swapper/010:20:000
2519899216,14cyclictest0-21swapper/210:46:052
25195992112,0cyclictest0-21swapper/110:01:321
25194992114,4cyclictest0-21swapper/010:42:030
2519499210,0cyclictest9-21ksoftirqd/009:20:030
2519499202,3cyclictest26885-21ntpq07:10:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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