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2026-09-10 - 18:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Sep 10, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2072799252,16cyclictest23698-21munin-run12:00:000
2072999230,5cyclictest0-21swapper/209:53:182
2072899230,5cyclictest0-21swapper/112:33:521
2072899230,5cyclictest0-21swapper/110:44:271
2072899220,18cyclictest0-21swapper/111:19:031
2072799220,21cyclictest843-21systemd-network10:46:220
2072799220,21cyclictest843-21systemd-network10:46:220
20729992113,3cyclictest0-21swapper/209:37:412
20728992121,0cyclictest0-21swapper/108:10:161
20728992121,0cyclictest0-21swapper/108:10:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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