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2026-07-17 - 22:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 17, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10969992727,0cyclictest0-21swapper/010:23:320
1097199234,14cyclictest3958-21perf09:50:002
1097199230,5cyclictest0-21swapper/210:37:422
1097099230,5cyclictest0-21swapper/110:00:091
1097099230,22cyclictest843-21systemd-network10:18:131
10970992214,4cyclictest0-21swapper/111:50:221
1097099220,7cyclictest399-20systemd-journal11:30:011
1097199210,3cyclictest0-21swapper/210:04:112
1097099212,16cyclictest0-21swapper/109:30:141
1097099204,15cyclictest21-21ksoftirqd/108:52:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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