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2026-04-20 - 17:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 20, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3184799250,24cyclictest21-21ksoftirqd/112:31:281
31842992321,1cyclictest9-21ksoftirqd/008:35:010
3184299230,18cyclictest0-21swapper/009:35:050
31847992117,3cyclictest0-21swapper/109:43:391
31847992111,10cyclictest0-21swapper/109:15:201
3185199200,19cyclictest24280-21cpuspeed_turbos08:50:132
3184799204,15cyclictest0-21swapper/108:50:061
31847992018,1cyclictest3979-21H222:10:211
3184799200,17cyclictest0-21swapper/108:05:021
3185199193,15cyclictest3991-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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