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2026-07-28 - 06:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 28, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22024993230,2cyclictest0-21swapper/122:15:201
2202999230,18cyclictest0-21swapper/221:35:172
2202499230,5cyclictest0-21swapper/121:07:101
2202499230,18cyclictest27744-21python323:10:001
2202399220,4cyclictest0-21swapper/022:46:000
22029992116,4cyclictest13895-21munin-run20:50:012
2202999200,19cyclictest870-21systemd-logind22:36:512
2202999200,17cyclictest0-21swapper/219:29:572
2202499200,15cyclictest0-21swapper/123:38:311
22023992017,2cyclictest9-21ksoftirqd/021:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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