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2026-08-20 - 14:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Aug 20, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28946992711,2cyclictest0-21swapper/022:40:130
28947992625,0cyclictest0-21swapper/121:35:011
28947992220,2cyclictest0-21swapper/120:54:491
2894699214,16cyclictest31585-21sort00:00:010
2894699212,18cyclictest0-21swapper/000:35:150
28946992118,2cyclictest8116-21chrt19:29:100
28946992117,3cyclictest7690-21ls22:20:010
28946992117,3cyclictest5519-21cat23:10:200
28946992117,3cyclictest18518-21idleruntime-cro20:45:000
28946992117,3cyclictest18066-21awk21:40:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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