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2026-05-30 - 22:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 30, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20083992819,9cyclictest0-21swapper/109:25:121
20083992523,1cyclictest0-21swapper/112:12:511
20084992414,5cyclictest0-21swapper/209:40:172
2008299242,15cyclictest0-21swapper/007:19:060
2008299231,21cyclictest0-21swapper/011:15:160
2008299230,15cyclictest0-21swapper/009:35:140
2008399220,21cyclictest843-21systemd-network08:51:351
2008299222,1cyclictest5462sleep009:23:560
20082992214,2cyclictest12942-21apache_volume11:40:120
20082992214,2cyclictest0-21swapper/009:40:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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