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2025-11-01 - 17:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Nov 01, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2709992516,0cyclictest0-21swapper/209:50:152
269899230,5cyclictest8565-21latency_hist07:20:020
269899230,5cyclictest0-21swapper/010:10:010
2709992213,6cyclictest454-21plymouthd10:49:252
2698992222,0cyclictest0-21swapper/009:00:200
269899220,6cyclictest0-21swapper/010:40:180
269899212,3cyclictest23240-21nvmesmart_nvme008:40:180
269899210,3cyclictest0-21swapper/009:23:380
269899210,20cyclictest0-21swapper/011:21:200
270999202,17cyclictest0-21swapper/209:05:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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