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2026-08-31 - 22:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 31, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2858599276,16cyclictest0-21swapper/107:35:211
2858999230,5cyclictest0-21swapper/209:13:092
2858999230,21cyclictest14253-21nfsd408:35:182
2858099227,1cyclictest101rcuc/010:47:580
28589992113,3cyclictest0-21swapper/211:33:502
28585992119,1cyclictest21-21ksoftirqd/110:40:321
2858099212,13cyclictest0-21swapper/009:10:220
2858099210,1cyclictest0-21swapper/007:22:520
28589992017,2cyclictest399-20systemd-journal09:50:002
28589992014,4cyclictest4099-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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