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2026-06-11 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jun 11, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1564299233,9cyclictest0-21swapper/008:50:020
1564299230,18cyclictest0-21swapper/009:20:010
1564299212,15cyclictest0-21swapper/010:22:180
1564299204,6cyclictest0-21swapper/011:41:320
1564299203,16cyclictest3979-21H222:10:210
1564299200,18cyclictest0-21swapper/010:25:310
1564299200,18cyclictest0-21swapper/008:15:560
15651991917,1cyclictest28-21ksoftirqd/210:11:542
15651991916,2cyclictest8381-21needreboot11:40:162
1565199190,3cyclictest0-21swapper/211:54:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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