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2026-07-21 - 08:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 21, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7198992423,1cyclictest0-21swapper/200:32:182
719199236,14cyclictest0-21swapper/021:20:170
719399227,11cyclictest14077-21latency_hist20:20:011
7193992211,4cyclictest32746-21python323:44:591
7198992119,1cyclictest97762chrt19:14:472
719899205,1cyclictest28-21ksoftirqd/222:00:552
719899204,15cyclictest0-21swapper/220:13:232
7198992018,1cyclictest28-21ksoftirqd/222:28:592
719899201,1cyclictest0-21swapper/220:23:242
719899200,19cyclictest426-21systemd-udevd23:30:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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