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2026-06-25 - 11:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jun 25, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22241993836,2cyclictest21-21ksoftirqd/122:03:131
22241993736,0cyclictest0-21swapper/100:08:251
2224199370,36cyclictest0-21swapper/121:34:071
22241993635,0cyclictest0-21swapper/123:39:151
22241993635,0cyclictest0-21swapper/121:01:011
2224199360,35cyclictest0-21swapper/122:22:571
2224299350,35cyclictest0-21swapper/223:05:142
2224199350,35cyclictest7032-21kworker/1:121:38:481
2224199350,35cyclictest23965-21kworker/1:021:28:581
2224199350,0cyclictest0-21swapper/120:46:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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