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2026-02-16 - 11:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 16, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17879992424,0cyclictest0-21swapper/221:05:002
17878992421,2cyclictest18862-21nfsd422:00:191
17877992417,6cyclictest0-21swapper/019:40:010
17879992321,1cyclictest5733-21mii-tool22:35:162
1787799238,14cyclictest0-21swapper/019:32:110
1787999213,17cyclictest0-21swapper/222:04:022
1787999211,2cyclictest0-21swapper/223:55:152
1787899210,7cyclictest843-21systemd-network00:30:401
17877992118,2cyclictest18820-21nfsd422:00:190
1787999203,16cyclictest15813-21date23:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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