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2026-07-09 - 00:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 08, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1134799230,5cyclictest0-21swapper/109:28:421
11347992213,0cyclictest0-21swapper/111:30:161
11351992117,3cyclictest0-21swapper/212:18:222
11347992117,1cyclictest0-21swapper/112:25:141
1134299213,15cyclictest0-21swapper/008:30:130
11351992016,1cyclictest0-21swapper/211:32:262
1135199201,2cyclictest0-21swapper/210:15:202
1135199200,19cyclictest0-21swapper/210:36:132
1134799204,15cyclictest0-21swapper/109:17:291
11347992017,2cyclictest11792-21cstates10:00:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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