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2026-07-25 - 15:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 25, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31936992914,1cyclictest0-21swapper/121:05:121
3193699230,5cyclictest0-21swapper/120:10:141
3193499230,5cyclictest6614-21sed23:10:000
3193999220,17cyclictest0-21swapper/220:36:272
3193999220,17cyclictest0-21swapper/220:36:272
3193699220,4cyclictest0-21swapper/119:53:171
3193499224,15cyclictest0-21swapper/020:45:140
31939992114,3cyclictest0-21swapper/220:30:142
3193699214,1cyclictest0-21swapper/119:30:211
3193699210,17cyclictest0-21swapper/120:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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