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2026-02-01 - 06:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 01, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2649899230,22cyclictest0-21swapper/119:40:141
2649799230,5cyclictest9803-21cat20:35:010
26499992212,5cyclictest0-21swapper/221:30:162
2649899220,21cyclictest870-21systemd-logind19:48:511
26497992216,5cyclictest0-21swapper/019:15:010
2649799220,18cyclictest0-21swapper/021:28:510
2649799214,13cyclictest16694-21gpgv22:40:000
26499992016,3cyclictest0-21swapper/221:20:432
26498992012,7cyclictest843-21systemd-network22:57:451
2649899200,16cyclictest0-21swapper/120:53:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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