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2026-07-12 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 12, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30398992727,0cyclictest0-21swapper/208:05:542
3039899230,22cyclictest0-21swapper/211:30:142
3039899230,18cyclictest0-21swapper/210:45:182
30396992322,1cyclictest0-21swapper/012:15:000
30396992322,1cyclictest0-21swapper/012:15:000
3039699220,4cyclictest0-21swapper/012:39:000
3039899213,17cyclictest0-21swapper/211:10:012
30397992113,3cyclictest0-21swapper/112:00:531
30396992121,0cyclictest32346-21mii-tool09:05:140
30396992112,0cyclictest0-21swapper/007:20:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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