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2026-05-25 - 01:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun May 24, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5755992625,0cyclictest0-21swapper/009:30:150
5755992323,0cyclictest0-21swapper/010:20:130
575799221,13cyclictest0-21swapper/209:05:172
575799210,17cyclictest0-21swapper/210:30:402
5756992114,3cyclictest0-21swapper/111:06:031
575699210,20cyclictest843-21systemd-network07:31:111
575599210,20cyclictest0-21swapper/008:32:320
575799205,10cyclictest3450-21gsd-color09:40:012
575799204,9cyclictest0-21swapper/209:10:172
575799204,15cyclictest0-21swapper/209:57:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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