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2026-05-17 - 17:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun May 17, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26927993129,2cyclictest0-21swapper/107:29:591
2693199223,16cyclictest3678-21grep08:20:162
26927992213,6cyclictest8137-21fschecks_time09:25:141
2692199221,4cyclictest0-21swapper/007:55:010
2692199220,21cyclictest0-21swapper/009:55:430
2693199212,18cyclictest0-21swapper/211:01:532
26921992113,4cyclictest0-21swapper/011:24:170
26931992017,2cyclictest2069-21systemd-udevd08:18:522
2693199200,19cyclictest0-21swapper/212:00:132
26921992017,2cyclictest4099-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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