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2025-11-05 - 10:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Nov 05, 2025 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15074992421,2cyclictest4523-21H212:26:330
15075992314,5cyclictest0-21swapper/123:50:201
1507499220,4cyclictest0-21swapper/000:12:260
1507599210,4cyclictest0-21swapper/123:56:091
1507599210,3cyclictest0-21swapper/119:17:211
1507699203,15cyclictest21242-21smartctl23:10:202
15076992015,3cyclictest10479-21grep23:50:152
15075992012,4cyclictest0-21swapper/100:27:491
1507699192,16cyclictest0-21swapper/200:29:022
15076991917,1cyclictest28-21ksoftirqd/221:20:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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