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2026-09-14 - 17:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Sep 14, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1990899230,18cyclictest10465-21tr10:40:132
1990899228,13cyclictest0-21swapper/212:28:002
1990899224,3cyclictest880-21rs:main2
1990399220,21cyclictest843-21systemd-network09:48:561
1989999220,18cyclictest0-21swapper/010:34:080
1990899213,12cyclictest0-21swapper/211:47:552
1990899210,20cyclictest843-21systemd-network11:52:592
1990399213,16cyclictest10900-21latency_hist12:35:001
19903992121,0cyclictest0-21swapper/111:40:161
1989999210,6cyclictest426-21systemd-udevd08:46:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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