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2026-06-15 - 19:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 15, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12184992710,11cyclictest26817-21latency_hist22:30:002
1218499250,20cyclictest9304-21nfsd420:00:192
1217899230,5cyclictest0-21swapper/119:57:011
1217499230,5cyclictest0-21swapper/023:12:020
12184992222,0cyclictest0-21swapper/220:34:062
1217499226,14cyclictest0-21swapper/019:49:590
1217499220,17cyclictest0-21swapper/000:15:180
1218499214,2cyclictest23037-21grep22:20:182
1218499213,17cyclictest0-21swapper/221:00:022
12184992114,3cyclictest0-21swapper/223:45:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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