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2026-07-11 - 17:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 11, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30604992826,0cyclictest0-21swapper/109:30:221
30602992415,9cyclictest0-21swapper/011:27:160
30604992312,10cyclictest0-21swapper/111:40:161
3060299220,4cyclictest0-21swapper/011:22:250
3061099210,3cyclictest0-21swapper/210:30:192
30604992112,0cyclictest0-21swapper/111:27:161
3060499210,20cyclictest0-21swapper/112:25:181
30610992015,4cyclictest8044-21tr12:10:132
3061099200,3cyclictest0-21swapper/211:51:112
3060499203,16cyclictest2872-21systemd-logind09:20:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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