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2026-06-01 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 01, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19007992928,0cyclictest0-21swapper/111:31:221
1900799235,16cyclictest2857-21in:imuxsock08:25:001
1900799230,5cyclictest0-21swapper/107:48:101
19007992219,2cyclictest2069-21systemd-udevd10:36:521
1900299212,17cyclictest0-21swapper/010:40:010
19011992012,7cyclictest26069-21cut11:10:132
1901199200,19cyclictest843-21systemd-network08:00:392
19007992016,3cyclictest0-21swapper/111:52:531
19002992018,1cyclictest9-21ksoftirqd/007:32:230
1901199193,2cyclictest3979-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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