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2026-07-22 - 23:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 22, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2470799223,16cyclictest3979-21H222:10:210
2470999213,11cyclictest11237-21gpgv08:40:012
24707992121,0cyclictest0-21swapper/010:10:170
2470799210,20cyclictest843-21systemd-network09:34:550
2470999204,9cyclictest0-21swapper/210:45:012
2470999203,16cyclictest0-21swapper/208:28:222
2470799200,19cyclictest14499-21snapd08:02:300
2470799200,19cyclictest14499-21snapd08:02:300
2470999193,15cyclictest0-21swapper/209:23:092
2470899193,1cyclictest3991-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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