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2026-07-04 - 04:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 04, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1696999270,22cyclictest3979-21H222:10:210
16972992414,5cyclictest0-21swapper/220:10:132
1696999242,2cyclictest2524-21expr21:35:140
16969992414,8cyclictest1829-21systemd-journal23:09:000
1697299230,5cyclictest0-21swapper/220:46:252
16969992314,8cyclictest5137-21tune2fs22:35:140
16969992314,7cyclictest26616-21tlsmgr21:31:500
16969992314,7cyclictest26616-21tlsmgr21:31:500
1696999230,21cyclictest26800-21kernelversion21:20:160
1696999230,17cyclictest2007-21systemd-journal20:29:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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