You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-09 - 20:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 09, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7535992323,0cyclictest0-21swapper/208:28:262
7535992314,4cyclictest25971-21python312:25:002
753299220,18cyclictest0-21swapper/007:50:010
7532992121,0cyclictest0-21swapper/011:51:580
753299210,16cyclictest0-21swapper/011:19:110
753599202,17cyclictest0-21swapper/210:45:422
753599200,19cyclictest843-21systemd-network08:11:412
753399206,13cyclictest0-21swapper/108:20:131
753299203,11cyclictest0-21swapper/012:10:150
753599192,16cyclictest8042-21expr10:55:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional