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2026-03-06 - 00:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Mar 05, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30833993533,0cyclictest0-21swapper/112:23:481
30833992414,5cyclictest0-21swapper/109:30:141
30833992414,5cyclictest0-21swapper/109:30:131
3082999230,18cyclictest0-21swapper/011:05:130
3083399213,12cyclictest2634-21apt-config12:00:001
3083399212,18cyclictest0-21swapper/110:52:251
3083399204,15cyclictest0-21swapper/111:48:071
3083399200,19cyclictest843-21systemd-network10:55:361
30829992012,4cyclictest0-21swapper/008:35:000
3082999200,4cyclictest0-21swapper/010:23:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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