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2026-04-02 - 18:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 02, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1653099230,20cyclictest0-21swapper/010:10:180
1653299224,17cyclictest0-21swapper/208:46:402
1653299224,17cyclictest0-21swapper/208:46:402
1653099220,18cyclictest0-21swapper/009:24:350
1653199212,18cyclictest0-21swapper/108:30:171
1653099215,9cyclictest0-21swapper/007:36:140
16530992113,4cyclictest0-21swapper/012:26:390
16532992016,3cyclictest0-21swapper/207:26:392
1653199200,3cyclictest0-21swapper/108:44:231
16532991916,2cyclictest1901-21cut11:50:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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