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2026-09-23 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 23, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16079993322,10cyclictest32131-21cat23:25:151
1608099240,0cyclictest0-21swapper/200:25:162
1608099234,16cyclictest17019-21grep19:10:132
1607999230,3cyclictest0-21swapper/121:44:191
1607899237,15cyclictest0-21swapper/022:40:200
16078992210,11cyclictest0-21swapper/019:50:180
1607899220,18cyclictest0-21swapper/021:38:570
1608099214,13cyclictest0-21swapper/200:10:202
16080992118,2cyclictest3053-21systemd-logind19:56:512
16080992118,2cyclictest23695-21munin-plugin-st22:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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