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2026-08-20 - 01:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Aug 19, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10660992615,11cyclictest0-21swapper/209:10:172
10660992213,5cyclictest0-21swapper/210:50:122
1065699220,18cyclictest0-21swapper/111:41:331
1066099217,13cyclictest0-21swapper/208:15:502
1066099213,17cyclictest0-21swapper/209:27:112
1066099210,20cyclictest870-21systemd-logind08:30:212
10660992020,0cyclictest0-21swapper/210:00:172
10660992017,1cyclictest0-21swapper/211:33:582
10660992016,3cyclictest0-21swapper/212:37:332
10660992016,3cyclictest0-21swapper/209:03:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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