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2026-05-16 - 14:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 16, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1221099230,0cyclictest0-21swapper/100:30:141
1220999223,18cyclictest9-21ksoftirqd/023:55:410
12209992113,4cyclictest0-21swapper/022:50:050
1220999204,15cyclictest0-21swapper/000:18:000
1220999201,18cyclictest0-21swapper/023:24:330
1221199190,1cyclictest0-21swapper/221:45:122
1221199190,1cyclictest0-21swapper/200:10:332
1221099192,3cyclictest14496-21snapd00:22:571
1221099192,16cyclictest17403-21sessionclean23:09:011
1221099192,16cyclictest17403-21sessionclean23:09:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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