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2026-05-12 - 06:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue May 12, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26493993230,2cyclictest0-21swapper/121:46:541
2649799246,17cyclictest12046-21sed00:25:002
2649799242,15cyclictest0-21swapper/219:12:262
2649799240,1cyclictest0-21swapper/222:46:322
2649799240,13cyclictest0-21swapper/223:37:522
2649299240,5cyclictest0-21swapper/022:20:010
2649299240,3cyclictest21504-21date19:55:170
2649299240,2cyclictest31496-21awk00:00:170
2649299240,11cyclictest0-21swapper/023:47:540
2649799234,17cyclictest32377-21expr20:15:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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