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2026-02-24 - 06:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Feb 24, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2358799340,0cyclictest0-21swapper/019:45:150
23587992727,0cyclictest0-21swapper/022:10:150
2358899243,14cyclictest0-21swapper/120:12:171
2358799240,24cyclictest0-21swapper/000:05:150
2358899230,18cyclictest0-21swapper/123:25:151
23587992323,0cyclictest0-21swapper/023:30:150
23587992219,2cyclictest5028-21fschecks_count22:25:150
2358799220,5cyclictest0-21swapper/020:05:020
2358799220,4cyclictest0-21swapper/023:28:230
2358799214,1cyclictest0-21swapper/023:49:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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