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2026-09-14 - 03:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Sep 13, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2965299230,20cyclictest0-21swapper/111:29:191
2965299230,20cyclictest0-21swapper/111:29:181
2965299210,3cyclictest0-21swapper/108:25:161
2965299210,18cyclictest0-21swapper/111:55:181
2964799213,11cyclictest18037-21perf11:35:000
2964799210,3cyclictest0-21swapper/009:30:010
2965799203,16cyclictest21222-21awk07:50:192
2965799200,3cyclictest3991-21H222:10:212
2965799193,15cyclictest5083-21expr10:10:242
2965799193,15cyclictest0-21swapper/212:10:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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