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2025-11-19 - 12:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Nov 19, 2025 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226799220,18cyclictest0-21swapper/123:08:421
2262992214,4cyclictest0-21swapper/021:43:440
226799211,18cyclictest4500-21VM12:26:331
226799200,15cyclictest0-21swapper/120:55:241
2273991916,2cyclictest24720-21php7.023:39:002
2273991915,3cyclictest0-21swapper/220:35:212
2273991913,5cyclictest0-21swapper/221:35:202
227399191,16cyclictest27828-21wc23:45:002
227399190,4cyclictest30991-21cpuspeed_turbos21:55:152
227399190,18cyclictest0-21swapper/222:45:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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