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2025-06-29 - 00:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jun 28, 2025 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1633799230,5cyclictest0-21swapper/208:55:422
16333992313,7cyclictest0-21swapper/109:15:191
1633199230,20cyclictest0-21swapper/012:06:110
1633799227,13cyclictest0-21swapper/208:53:372
16337992213,5cyclictest0-21swapper/210:00:002
1633799220,4cyclictest25607-21cpuspeed_turbos10:15:172
1633799220,21cyclictest4608-21cstates10:35:172
16333992212,9cyclictest18663-21nfsd411:55:191
1633399220,4cyclictest0-21swapper/109:06:061
1633399210,20cyclictest823-21systemd-network08:10:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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