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2026-07-22 - 12:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 22, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9402993331,1cyclictest0-21swapper/021:00:130
941299250,20cyclictest23201-21fschecks_count20:30:142
941299230,5cyclictest0-21swapper/223:50:002
941299230,5cyclictest0-21swapper/222:39:352
9402992314,5cyclictest0-21swapper/022:36:280
9406992212,0cyclictest0-21swapper/100:25:181
940699210,21cyclictest0-21swapper/121:09:451
940299211,4cyclictest455-21plymouthd21:23:400
940299210,3cyclictest0-21swapper/023:18:500
940299210,3cyclictest0-21swapper/023:18:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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