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2026-05-31 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun May 31, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20045992314,5cyclictest0-21swapper/007:15:180
20045992311,5cyclictest24576-21grep12:00:110
2004799220,19cyclictest0-21swapper/212:19:592
2004699220,18cyclictest0-21swapper/109:10:001
2004699210,17cyclictest0-21swapper/108:33:571
2004599217,13cyclictest0-21swapper/011:49:110
2004599210,3cyclictest30195-21cpuspeed_turbos12:10:140
20047992018,1cyclictest0-21swapper/210:22:582
20047992016,3cyclictest0-21swapper/209:05:182
2004699200,19cyclictest843-21systemd-network11:00:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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