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2026-02-09 - 16:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 09, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2653599214,10cyclictest0-21swapper/212:03:482
2653599206,13cyclictest0-21swapper/211:28:442
26535992016,3cyclictest0-21swapper/211:13:362
26535992014,1cyclictest0-21swapper/207:25:162
2652699202,17cyclictest562-21fschecks_time07:20:150
2652699202,17cyclictest0-21swapper/009:32:490
26526992018,1cyclictest9-21ksoftirqd/008:20:510
26526992014,3cyclictest0-21swapper/010:11:500
2653599192,1cyclictest0-21swapper/212:30:402
2653599192,16cyclictest5601-21lxd10:36:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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