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2026-06-23 - 10:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jun 23, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20412993331,2cyclictest0-21swapper/121:00:351
20412993322,11cyclictest0-21swapper/123:39:001
20412993230,2cyclictest0-21swapper/120:43:091
20412993230,2cyclictest0-21swapper/100:27:191
20412993230,0cyclictest0-21swapper/122:29:431
20412993130,0cyclictest0-21swapper/121:06:421
20412993029,1cyclictest15157-21kworker/1:120:36:511
20412993029,0cyclictest0-21swapper/122:21:101
20412993028,2cyclictest0-21swapper/100:33:061
20412992929,0cyclictest21-21ksoftirqd/120:54:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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