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2026-06-11 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jun 11, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1484992318,4cyclictest28012-21needreboot23:45:172
1484992212,5cyclictest0-21swapper/219:30:012
148399220,21cyclictest843-21systemd-network20:26:081
148399220,18cyclictest0-21swapper/123:22:111
148399202,17cyclictest0-21swapper/123:11:221
1483992015,4cyclictest30842-21nfsd420:00:191
1484991917,1cyclictest0-21swapper/221:05:002
1484991915,3cyclictest0-21swapper/219:59:332
1484991913,3cyclictest17171-21nvmesmart_nvme023:25:192
148499190,2cyclictest3979-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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