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2026-04-10 - 09:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 10, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27380993512,14cyclictest4032-21accounts22:10:212
27380992212,5cyclictest0-21swapper/219:35:132
2738099220,21cyclictest843-21systemd-network21:22:432
2738099220,21cyclictest0-21swapper/200:17:432
2737799220,20cyclictest426-21systemd-udevd00:36:510
2737899214,16cyclictest0-21swapper/100:03:241
27378992118,2cyclictest3414-21master22:32:161
2737899210,3cyclictest0-21swapper/122:28:261
27380992016,3cyclictest0-21swapper/200:02:542
27380992014,3cyclictest0-21swapper/200:27:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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