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2026-05-02 - 23:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 02, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1816699284,6cyclictest0-21swapper/011:23:550
18175992414,5cyclictest0-21swapper/211:15:202
1817599240,17cyclictest29329-21turbostat09:25:012
1817599230,16cyclictest0-21swapper/209:48:182
1816699236,3cyclictest7232-21/usr/sbin/munin09:40:140
1816699236,3cyclictest7232-21/usr/sbin/munin09:40:140
1816699236,2cyclictest24535-21awk12:05:180
1816699236,16cyclictest10092-21latency_hist08:50:000
18175992213,6cyclictest3986-21H222:10:212
1817299222,17cyclictest11517-21cron09:50:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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