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2026-02-15 - 09:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 15, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15411993533,2cyclictest0-21swapper/121:00:141
15411992717,1cyclictest0-21swapper/121:45:021
1541199230,20cyclictest0-21swapper/100:10:131
1541199226,0cyclictest0-21swapper/123:40:141
1540799210,20cyclictest0-21swapper/021:41:430
1540799210,18cyclictest0-21swapper/020:21:510
15407992014,1cyclictest0-21swapper/000:20:250
15416991915,3cyclictest0-21swapper/220:45:232
1541699190,5cyclictest0-21swapper/200:30:142
1541699190,3cyclictest19765-21phpquery22:09:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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