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2026-08-30 - 07:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 30, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12843993331,2cyclictest0-21swapper/121:20:011
1284399262,15cyclictest28526-21latency_hist23:24:591
12844992219,2cyclictest29609-21latency_hist19:40:012
1284399214,11cyclictest0-21swapper/100:32:381
1284499202,13cyclictest19541-21gpgv20:20:012
1284299204,9cyclictest22582-21python323:15:000
1284299200,18cyclictest20842-21fgrep00:05:210
1284499193,15cyclictest0-21swapper/222:30:042
1284499192,2cyclictest9929-21nfsd420:00:172
1284499192,2cyclictest3983-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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