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2026-06-22 - 09:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 22, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24184992414,0cyclictest0-21swapper/123:34:421
24184992414,0cyclictest0-21swapper/123:34:421
2418399230,5cyclictest0-21swapper/022:39:200
2418599220,18cyclictest0-21swapper/222:59:562
2418599210,20cyclictest843-21systemd-network22:33:262
2418599210,20cyclictest0-21swapper/220:18:582
24183992119,1cyclictest0-21swapper/022:15:490
24185992017,2cyclictest15741-21nfsd419:50:192
2418599200,17cyclictest3981-21H222:10:212
2418499201,13cyclictest0-21swapper/123:02:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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