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2026-07-24 - 13:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 24, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128699343,24cyclictest0-21swapper/120:15:001
128699262,23cyclictest27347-21missed_timers22:45:171
128699260,2cyclictest18079-21perf00:25:001
128699253,21cyclictest0-21swapper/121:09:071
1286992414,5cyclictest10937-21grep21:20:151
128699234,18cyclictest0-21swapper/121:01:461
128699232,20cyclictest0-21swapper/121:15:191
128699230,2cyclictest26542-21sed19:55:011
128699230,2cyclictest17088-21cat23:25:011
128699230,2cyclictest12480-21apache_processe22:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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