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2026-01-14 - 12:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 14, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29322992624,1cyclictest7758-21mii-tool21:20:171
29317992626,0cyclictest0-21swapper/019:20:010
29317992424,0cyclictest0-21swapper/000:15:140
2932999230,18cyclictest0-21swapper/200:00:132
29317992317,5cyclictest9-21ksoftirqd/020:30:120
2932999220,18cyclictest0-21swapper/220:37:292
2931799220,5cyclictest0-21swapper/019:51:220
29322992117,3cyclictest3987-21H222:10:211
2932299210,20cyclictest0-21swapper/121:13:081
29329992018,1cyclictest0-21swapper/220:08:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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