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2026-09-05 - 11:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Sep 05, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21689992516,9cyclictest0-21swapper/119:30:011
2168999240,19cyclictest0-21swapper/121:14:081
21687992415,0cyclictest0-21swapper/021:40:140
2169199230,5cyclictest0-21swapper/221:53:172
2169199230,18cyclictest0-21swapper/222:40:132
21691992212,1cyclictest0-21swapper/222:05:162
2168999200,15cyclictest0-21swapper/100:10:051
2168799203,16cyclictest0-21swapper/023:05:020
21687992018,1cyclictest0-21swapper/021:35:140
2169199192,2cyclictest15859-21timerwakeupswit20:50:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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