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2026-07-31 - 11:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 31, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
919899250,6cyclictest19265-21fschecks_count00:10:181
919899230,5cyclictest0-21swapper/100:39:351
9202992218,3cyclictest24388-21awk19:35:192
920299220,21cyclictest843-21systemd-network20:43:362
920299207,12cyclictest0-21swapper/220:55:152
920299200,3cyclictest0-21swapper/223:13:122
920299192,3cyclictest0-21swapper/223:25:222
919899192,16cyclictest15977-21cpuspeed_turbos21:15:161
9198991917,1cyclictest0-21swapper/100:00:161
919399190,1cyclictest0-21swapper/019:45:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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