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2026-07-23 - 12:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 23, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
878699222,13cyclictest19738-21/usr/sbin/munin19:30:011
878799215,3cyclictest0-21swapper/219:35:112
878799210,20cyclictest0-21swapper/222:00:132
8787992018,1cyclictest28-21ksoftirqd/223:05:132
8787992016,3cyclictest0-21swapper/220:58:392
8787992014,4cyclictest399-20systemd-journal22:44:172
8785992014,5cyclictest0-21swapper/023:35:180
8785992013,6cyclictest22472-21sed22:25:000
878799193,15cyclictest28-21ksoftirqd/221:12:162
878799192,16cyclictest9587-21nvmesmart_nvme020:05:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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