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2026-08-21 - 14:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Aug 21, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19760992818,10cyclictest0-21swapper/120:00:211
1976099250,24cyclictest0-21swapper/122:45:141
1976199230,5cyclictest0-21swapper/222:57:062
19759992218,3cyclictest0-21swapper/021:56:410
1976199210,20cyclictest843-21systemd-network20:11:442
1976099212,16cyclictest0-21swapper/120:00:011
19760992112,0cyclictest0-21swapper/123:06:151
1975999210,3cyclictest0-21swapper/000:25:460
1976199202,17cyclictest0-21swapper/219:32:422
1976099202,17cyclictest0-21swapper/121:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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