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2026-08-18 - 20:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 18, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14235992420,3cyclictest4099-21H222:10:212
1423599240,19cyclictest0-21swapper/207:53:342
1423499240,19cyclictest0-21swapper/107:25:201
1423399230,5cyclictest0-21swapper/011:39:100
1423399220,4cyclictest0-21swapper/011:41:580
14235992117,3cyclictest0-21swapper/210:44:582
14234992118,2cyclictest4035-21H222:10:211
1423599202,17cyclictest3976-21H222:10:212
14235992017,2cyclictest3989-21H222:10:212
1423399202,2cyclictest0-21swapper/008:20:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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