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2026-09-18 - 08:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Sep 18, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
712599220,4cyclictest0-21swapper/020:48:170
712799212,18cyclictest9275-21cron00:00:002
7127992116,3cyclictest31753-21proc_pri23:40:212
712599212,18cyclictest0-21swapper/000:00:300
712799209,10cyclictest0-21swapper/220:45:162
712799204,15cyclictest0-21swapper/223:30:132
712799200,18cyclictest0-21swapper/221:32:322
712799192,2cyclictest28348-21nfsd419:45:182
712799192,2cyclictest1622-21nfsd419:55:172
7126991917,1cyclictest0-21swapper/123:41:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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