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2026-09-04 - 23:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Sep 04, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1165299270,4cyclictest0-21swapper/009:38:400
11662992414,5cyclictest0-21swapper/208:45:132
11652992421,2cyclictest14495-21snapd12:13:110
1165299237,6cyclictest0-21swapper/010:00:010
1165299230,5cyclictest0-21swapper/010:03:550
1165299230,16cyclictest21482-21latency_hist12:10:000
1165799220,18cyclictest0-21swapper/110:58:421
11652992215,1cyclictest0-21swapper/010:10:220
11652992214,2cyclictest30536-21kernelversion10:30:150
1165299221,15cyclictest188632sleep008:18:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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