You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-19 - 00:51
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 18, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15833992625,0cyclictest0-21swapper/111:38:411
1583299262,5cyclictest0-21swapper/012:40:010
15835992415,0cyclictest0-21swapper/207:50:162
1583599230,20cyclictest25756-21grep07:25:182
1583399220,18cyclictest0-21swapper/107:14:291
1583599201,2cyclictest22833-21python309:15:012
1583599200,17cyclictest0-21swapper/210:35:172
1583399203,16cyclictest19063-21cut10:05:001
15833992018,1cyclictest0-21swapper/109:40:181
15833992018,1cyclictest0-21swapper/108:18:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional