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2026-04-04 - 18:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Apr 04, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
369099236,11cyclictest0-21swapper/209:20:172
369099230,5cyclictest0-21swapper/212:25:182
368299230,5cyclictest0-21swapper/109:05:001
368299220,4cyclictest0-21swapper/108:15:431
3681992219,2cyclictest9805-21if_lxdbr011:05:170
368199220,8cyclictest0-21swapper/011:32:120
368199220,6cyclictest0-21swapper/008:45:440
368199220,18cyclictest0-21swapper/011:40:130
369099210,20cyclictest426-21systemd-udevd07:36:522
369099200,2cyclictest13172-21cat08:25:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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