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2026-02-16 - 23:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 16, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263399250,3cyclictest0-21swapper/212:22:292
263399230,20cyclictest0-21swapper/211:01:482
262299230,5cyclictest0-21swapper/008:32:190
262299230,18cyclictest0-21swapper/011:35:220
2633992215,6cyclictest0-21swapper/212:35:122
2633992214,7cyclictest0-21swapper/208:10:142
263399221,20cyclictest9961-21uname10:10:192
263399221,14cyclictest0-21swapper/208:50:142
263399220,2cyclictest19565-21users07:35:222
263399220,21cyclictest3407-21irqstats10:00:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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