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2026-06-09 - 10:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Jun 09, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30699993230,2cyclictest0-21swapper/021:10:160
30699993230,2cyclictest0-21swapper/021:10:150
30709992625,0cyclictest0-21swapper/222:42:082
30699992312,6cyclictest31856-21cut23:00:130
3070499223,13cyclictest0-21swapper/119:40:141
3069999220,4cyclictest0-21swapper/021:46:480
3069999220,18cyclictest0-21swapper/020:40:150
3070999212,18cyclictest0-21swapper/220:56:132
30709992112,7cyclictest28-21ksoftirqd/220:50:002
30699992113,4cyclictest0-21swapper/023:06:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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