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2026-09-20 - 06:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Sep 20, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
451992610,1cyclictest0-21swapper/221:35:142
451992523,1cyclictest0-21swapper/221:35:002
44699240,23cyclictest31823-21perf20:05:011
451992220,1cyclictest0-21swapper/220:10:172
44699220,18cyclictest0-21swapper/122:15:121
44299220,21cyclictest870-21systemd-logind19:36:520
44699214,16cyclictest19290-21perf20:40:001
44699214,16cyclictest0-21swapper/121:39:231
446992114,3cyclictest0-21swapper/120:55:161
44299214,1cyclictest3991-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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