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2026-09-05 - 23:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Sep 05, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31574992816,6cyclictest20181-21latency_hist11:35:010
3157699241,17cyclictest0-21swapper/211:25:002
3157699240,23cyclictest4674-21wc08:15:122
3157699240,20cyclictest15645-21chrt10:26:332
3157699232,1cyclictest0-21swapper/208:46:262
3157699231,2cyclictest12771-21chrt08:29:562
3157699230,3cyclictest23089-21perf11:40:012
3157699230,3cyclictest21297-21sshd08:41:332
3157699230,2cyclictest9652-21perf08:25:012
3157699230,22cyclictest27807-21expr08:55:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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