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2026-08-29 - 07:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 29, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
984799230,5cyclictest0-21swapper/223:40:002
984199210,20cyclictest843-21systemd-network19:45:410
984399204,15cyclictest0-21swapper/123:56:451
984399204,15cyclictest0-21swapper/123:56:451
984399200,0cyclictest0-21swapper/121:30:161
984199200,4cyclictest29784-21latency_hist00:30:000
984799193,15cyclictest0-21swapper/223:46:132
984799192,2cyclictest31670-21chrt22:36:082
984799192,16cyclictest9397-21chrt21:58:202
9847991917,1cyclictest0-21swapper/223:58:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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