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2026-08-02 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 02, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1344399255,1cyclictest0-21swapper/008:55:160
1344399243,20cyclictest0-21swapper/011:55:010
1344399242,1cyclictest0-21swapper/011:35:160
1344799230,23cyclictest0-21swapper/111:50:181
1344399230,22cyclictest19230-21sendmail-msp07:20:000
1344399226,14cyclictest0-21swapper/007:25:400
1344399225,15cyclictest3983-21H222:10:210
1344399222,2cyclictest3978-21H222:10:210
1344399222,18cyclictest0-21swapper/009:11:380
13443992214,7cyclictest20460-21expr11:10:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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