You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-09-17 - 15:37
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 17, 2025 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19324992321,1cyclictest28-21ksoftirqd/209:48:332
1932499231,18cyclictest28-21ksoftirqd/207:25:452
1932499230,22cyclictest0-21swapper/208:02:102
1932299230,22cyclictest0-21swapper/107:45:221
1932199230,5cyclictest0-21swapper/011:27:300
1932199220,21cyclictest823-21systemd-network09:39:520
1932499212,11cyclictest31577-21python311:20:012
1932499210,3cyclictest0-21swapper/211:55:172
1932199214,11cyclictest13822-21munin-run11:45:000
1932499192,3cyclictest0-21swapper/208:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional