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2026-05-26 - 04:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue May 26, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2448999290,0cyclictest0-21swapper/200:15:142
24484992715,11cyclictest4672-21nfsd400:15:181
24489992414,5cyclictest0-21swapper/222:25:132
24484992219,2cyclictest28971-21latency_hist00:05:011
24484992112,0cyclictest0-21swapper/121:50:151
2448499210,3cyclictest0-21swapper/100:25:011
24489992015,4cyclictest399-20systemd-journal19:50:012
24483992017,2cyclictest441-21sshd21:19:060
2448999194,1cyclictest0-21swapper/200:33:472
2448999193,1cyclictest28-21ksoftirqd/220:09:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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