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2026-01-22 - 08:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jan 22, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1888992814,0cyclictest0-21swapper/120:40:191
188799220,18cyclictest0-21swapper/000:03:300
188999215,1cyclictest13263-21cpuspeed_turbos20:25:172
1889992118,2cyclictest22619-21php7.021:39:002
1889992117,3cyclictest23884-21grep21:40:152
188999203,16cyclictest880-21rs:main2
188999203,16cyclictest2872-21systemd-logind21:48:512
1888992017,1cyclictest0-21swapper/100:13:081
188899200,19cyclictest843-21systemd-network23:06:411
188799200,17cyclictest0-21swapper/020:40:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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