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2026-05-23 - 23:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat May 23, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
707399236,13cyclictest0-21swapper/111:23:211
707499220,17cyclictest0-21swapper/210:43:512
707399220,21cyclictest21-21ksoftirqd/109:50:181
707299210,18cyclictest0-21swapper/009:43:350
707499202,17cyclictest3986-21H222:10:212
7072992018,1cyclictest0-21swapper/012:36:190
7072992012,6cyclictest0-21swapper/008:04:040
7074991916,2cyclictest3188-21cut08:55:192
7074991915,3cyclictest0-21swapper/210:22:532
7074991914,3cyclictest0-21swapper/208:47:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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