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2026-07-01 - 13:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 01, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9299992714,10cyclictest0-21swapper/122:56:201
9299992713,11cyclictest0-21swapper/122:18:491
929999253,15cyclictest0-21swapper/121:43:261
9299992422,2cyclictest0-21swapper/121:29:571
929999234,2cyclictest24296-21grep00:25:141
9299992314,0cyclictest0-21swapper/121:02:101
9300992220,1cyclictest1100-21snmpd20:12:202
929799220,21cyclictest0-21swapper/000:20:140
9299992119,2cyclictest0-21swapper/122:46:281
9299992118,2cyclictest0-21swapper/119:45:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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