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2026-06-24 - 23:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jun 24, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7648992915,8cyclictest23761-21seq07:38:020
765899252,18cyclictest0-21swapper/211:14:172
765899250,24cyclictest28-21ksoftirqd/207:10:212
765899250,24cyclictest28-21ksoftirqd/207:10:212
765899240,23cyclictest0-21swapper/211:30:012
7648992414,6cyclictest0-21swapper/007:56:000
7658992323,0cyclictest28-21ksoftirqd/207:34:072
765899230,22cyclictest0-21swapper/211:40:042
765899230,22cyclictest0-21swapper/210:49:042
764899235,14cyclictest9-21ksoftirqd/011:33:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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