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2026-08-17 - 13:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 17, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1923992727,0cyclictest0-21swapper/023:37:550
1927992516,9cyclictest0-21swapper/100:34:171
192799240,5cyclictest0-21swapper/100:10:191
1923992414,5cyclictest0-21swapper/021:45:180
193299235,12cyclictest0-21swapper/219:15:112
192399230,5cyclictest0-21swapper/022:05:150
1932992215,4cyclictest30407-21perf23:50:002
192799222,15cyclictest17557-21date20:35:011
1923992219,2cyclictest399-20systemd-journal20:30:010
1927992118,2cyclictest1274-21runrttasks19:26:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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