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2026-05-24 - 12:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun May 24, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2411099258,2cyclictest5984-21ntpq00:15:192
2410999230,7cyclictest23811-21idleruntime-cro22:00:001
2410899230,22cyclictest0-21swapper/020:28:510
2411099224,2cyclictest7812-21tr21:30:122
24109992218,3cyclictest0-21swapper/100:23:021
24109992211,10cyclictest0-21swapper/121:46:281
24109992118,2cyclictest3991-21H222:10:211
24110992018,1cyclictest28-21ksoftirqd/220:04:362
2410999202,16cyclictest4099-21H222:10:211
2411099193,2cyclictest3981-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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