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2026-06-10 - 07:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jun 10, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3231399240,19cyclictest0-21swapper/120:55:131
32318992322,0cyclictest0-21swapper/222:40:162
3231899230,5cyclictest0-21swapper/220:30:142
3230999230,5cyclictest0-21swapper/023:58:410
3231399220,22cyclictest0-21swapper/121:54:521
32318992118,1cyclictest0-21swapper/222:46:282
3230999214,13cyclictest28909-21grep23:50:000
32318992018,1cyclictest0-21swapper/200:00:142
32318992017,2cyclictest3979-21H222:10:212
3231399200,17cyclictest0-21swapper/119:39:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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