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2026-06-12 - 21:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jun 12, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1921399254,1cyclictest0-21swapper/212:15:502
1920499251,19cyclictest0-21swapper/009:30:010
1920499251,19cyclictest0-21swapper/009:30:000
1921399240,23cyclictest0-21swapper/208:08:102
1921399240,18cyclictest25155-21tr12:05:132
19204992314,6cyclictest0-21swapper/010:52:510
19213992220,1cyclictest14548-21ntp_kernel_pll_09:50:202
19209992222,0cyclictest0-21swapper/108:10:401
1920999214,11cyclictest20957-21latency_hist10:05:021
1921399204,15cyclictest28-21ksoftirqd/210:57:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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