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2026-02-02 - 21:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 02, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7024992819,9cyclictest0-21swapper/111:20:251
702599230,22cyclictest3979-21H222:10:212
702599230,17cyclictest0-21swapper/209:14:402
7025992214,7cyclictest6588-21taskset09:59:212
7025992214,7cyclictest6588-21taskset09:59:202
7025992214,7cyclictest28893-21cat08:44:562
702599220,21cyclictest7633-21cat10:00:132
702599220,21cyclictest17067-21awk10:15:202
702599220,21cyclictest16154-21ls07:25:012
702599220,21cyclictest0-21swapper/210:30:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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