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2026-09-19 - 12:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Sep 19, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
331199246,15cyclictest0-21swapper/122:04:591
331699230,5cyclictest0-21swapper/220:58:462
3311992314,0cyclictest0-21swapper/119:50:151
331099230,5cyclictest0-21swapper/022:35:150
331199220,21cyclictest843-21systemd-network22:55:281
331199220,18cyclictest0-21swapper/120:35:061
331099220,4cyclictest0-21swapper/000:08:500
331199212,5cyclictest0-21swapper/121:06:461
331699202,2cyclictest3981-21H222:10:212
3311992018,2cyclictest0-21swapper/120:35:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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