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2026-06-27 - 15:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jun 27, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1362799240,23cyclictest0-21swapper/222:10:382
1362799232,0cyclictest0-21swapper/221:38:402
13627992316,2cyclictest0-21swapper/220:50:372
13627992314,5cyclictest0-21swapper/223:04:042
1362799230,22cyclictest0-21swapper/220:03:482
1362499236,11cyclictest0-21swapper/120:00:101
1362499230,5cyclictest0-21swapper/120:53:321
1362499230,18cyclictest0-21swapper/120:11:191
13627992217,3cyclictest2007-21systemd-journal00:03:292
1362799220,0cyclictest0-21swapper/222:36:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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