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2026-06-28 - 20:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jun 28, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2781299258,16cyclictest11788-21grep08:35:012
27811992422,2cyclictest0-21swapper/110:39:581
27811992414,0cyclictest0-21swapper/111:04:101
2781099248,2cyclictest4099-21H222:10:210
2781299230,5cyclictest0-21swapper/211:57:452
27811992319,0cyclictest0-21swapper/110:34:181
27811992313,0cyclictest0-21swapper/111:09:521
2781199230,5cyclictest0-21swapper/109:38:171
27810992314,5cyclictest0-21swapper/009:01:140
27812992213,0cyclictest0-21swapper/211:33:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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