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2026-02-08 - 16:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 08, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30544993414,19cyclictest20277-21sort08:45:000
3054499287,2cyclictest15231-21tr11:25:140
3054499280,5cyclictest0-21swapper/009:24:110
3054499280,5cyclictest0-21swapper/008:51:030
30545992516,5cyclictest0-21swapper/110:16:171
30545992513,6cyclictest19144-21/usr/sbin/munin09:40:141
30544992514,9cyclictest1829-21systemd-journal07:25:020
3054599240,1cyclictest0-21swapper/110:07:371
3054799230,5cyclictest0-21swapper/212:20:202
3054599233,1cyclictest0-21swapper/112:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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