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2026-04-05 - 05:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 05, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2411799310,31cyclictest0-21swapper/119:10:151
24116992625,0cyclictest0-21swapper/020:55:170
2411799230,22cyclictest0-21swapper/100:00:561
2411799230,20cyclictest0-21swapper/121:06:051
24117992213,8cyclictest0-21swapper/100:14:501
2411699220,6cyclictest0-21swapper/000:32:190
2411699220,4cyclictest0-21swapper/019:19:360
2411799203,11cyclictest0-21swapper/121:45:511
2411799202,17cyclictest0-21swapper/121:14:061
2411799202,15cyclictest0-21swapper/122:01:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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