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2026-08-16 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 16, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7569992927,1cyclictest0-21swapper/122:23:001
7569992725,2cyclictest0-21swapper/120:26:191
7569992625,0cyclictest0-21swapper/121:18:551
756999250,1cyclictest0-21swapper/100:00:181
7564992513,6cyclictest0-21swapper/022:05:010
7569992415,9cyclictest0-21swapper/121:29:141
757399230,18cyclictest0-21swapper/222:35:192
7573992221,0cyclictest0-21swapper/220:26:192
757399220,4cyclictest0-21swapper/223:44:042
757399220,21cyclictest0-21swapper/222:23:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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