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2026-08-12 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Aug 12, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
765099220,18cyclictest0-21swapper/112:35:471
764699210,4cyclictest0-21swapper/010:50:010
765599200,19cyclictest0-21swapper/210:20:302
765599200,17cyclictest4099-21H222:10:212
765099204,0cyclictest0-21swapper/109:45:171
765099202,11cyclictest11186-21munin-run09:10:001
7650992017,2cyclictest31482-21timerwakeupswit08:45:211
7646992017,2cyclictest2872-21systemd-logind11:32:520
765599194,1cyclictest0-21swapper/210:14:442
765599193,15cyclictest28-21ksoftirqd/211:01:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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