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2026-05-25 - 15:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon May 25, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7063993030,0cyclictest0-21swapper/110:15:151
7067992918,10cyclictest0-21swapper/210:43:082
7063992817,10cyclictest0-21swapper/109:50:161
7058992818,9cyclictest0-21swapper/010:43:090
7067992222,0cyclictest0-21swapper/210:15:142
706799220,17cyclictest0-21swapper/210:20:182
706799212,18cyclictest0-21swapper/212:36:162
706799212,18cyclictest0-21swapper/212:36:152
7063992114,3cyclictest0-21swapper/107:20:191
705899215,12cyclictest0-21swapper/008:28:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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