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2026-08-18 - 04:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 18, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30778992516,9cyclictest0-21swapper/121:33:071
3077899222,17cyclictest0-21swapper/100:05:341
30778992220,1cyclictest21-21ksoftirqd/123:06:331
30773992119,1cyclictest17057-21if_eno121:35:180
30783992018,1cyclictest0-21swapper/219:10:162
3077899204,1cyclictest0-21swapper/123:43:311
30778992012,4cyclictest0-21swapper/122:05:121
30778992012,4cyclictest0-21swapper/122:05:121
3078399192,1cyclictest5577-21grep21:15:152
3078399192,1cyclictest5577-21grep21:15:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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