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2026-09-17 - 23:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Sep 17, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2181399241,5cyclictest201rcuc/112:19:571
21812992424,0cyclictest0-21swapper/010:12:100
2181399231,0cyclictest21-21ksoftirqd/111:14:111
21812992314,6cyclictest0-21swapper/009:25:050
2181299230,5cyclictest0-21swapper/007:19:530
21812992214,4cyclictest0-21swapper/011:30:310
21814992117,1cyclictest0-21swapper/207:50:002
21813992119,1cyclictest21-21ksoftirqd/108:25:021
21814992018,1cyclictest0-21swapper/211:01:092
2181399204,15cyclictest21-21ksoftirqd/110:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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