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2026-02-17 - 23:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Feb 17, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
271499230,5cyclictest15456-21perf11:20:002
271499230,5cyclictest0-21swapper/210:17:512
271399220,4cyclictest0-21swapper/108:53:091
271299220,18cyclictest0-21swapper/007:22:410
271499214,16cyclictest993-21dbus-daemon07:50:212
2714992016,3cyclictest3053-21systemd-logind08:50:522
271399200,19cyclictest426-21systemd-udevd09:26:521
271299202,1cyclictest0-21swapper/008:05:020
271299202,17cyclictest9-21ksoftirqd/010:21:330
271499190,3cyclictest4102-21grep10:00:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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