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2026-06-04 - 04:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jun 04, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31948992816,7cyclictest0-21swapper/020:50:480
3194899260,2cyclictest11366-21sed21:09:010
31949992416,5cyclictest0-21swapper/122:16:431
3194999230,19cyclictest0-21swapper/123:40:001
3194899230,15cyclictest0-21swapper/021:10:170
3194999222,19cyclictest304902chrt00:38:151
3194999222,19cyclictest30332chrt19:18:511
3194999220,21cyclictest9706-21perf23:05:011
3194999220,21cyclictest9069-21awk21:00:141
3194999220,21cyclictest24515-21grep00:25:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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