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2026-08-31 - 10:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 31, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1332599273,19cyclictest0-21swapper/000:29:590
1332599260,0cyclictest0-21swapper/023:50:120
1332899240,19cyclictest23949-21cpuspeed_turbos00:15:132
1332599242,18cyclictest0-21swapper/021:25:000
1332599233,11cyclictest600-21munin-run19:45:000
1332899225,13cyclictest0-21swapper/222:25:152
1332799220,4cyclictest0-21swapper/122:50:371
1332899215,1cyclictest28-21ksoftirqd/220:59:432
13328992119,1cyclictest28-21ksoftirqd/221:35:232
1332799210,20cyclictest0-21swapper/121:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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