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2026-05-19 - 08:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue May 19, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
751299253,14cyclictest0-21swapper/019:31:570
7521992314,5cyclictest0-21swapper/223:29:592
751599220,5cyclictest0-21swapper/119:18:451
752199202,1cyclictest0-21swapper/221:54:312
7515992017,2cyclictest11796-21cron00:05:011
7512992017,2cyclictest2638-21mii-tool20:55:160
752199193,15cyclictest28-21ksoftirqd/220:50:172
752199192,1cyclictest0-21swapper/223:45:162
7521991916,2cyclictest22122-21date23:25:022
7521991914,1cyclictest0-21swapper/223:15:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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