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2026-08-11 - 11:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 11, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
467899270,15cyclictest17200-21cpuspeed_turbos23:20:151
467899250,19cyclictest0-21swapper/121:45:011
467399220,18cyclictest0-21swapper/000:28:260
468499210,5cyclictest0-21swapper/200:17:152
468499210,20cyclictest843-21systemd-network21:24:022
468499210,20cyclictest537-21irqstats22:50:192
467899210,3cyclictest0-21swapper/121:03:471
467899210,1cyclictest0-21swapper/123:10:121
467899204,1cyclictest0-21swapper/119:40:341
4678992014,5cyclictest0-21swapper/121:35:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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