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2026-08-15 - 09:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 15, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12740992514,0cyclictest0-21swapper/122:15:511
1274099240,23cyclictest31506-21ps19:40:201
1274099237,14cyclictest0-21swapper/119:45:141
12735992323,0cyclictest0-21swapper/019:57:290
12735992319,3cyclictest17311-21grep20:15:010
1274499220,18cyclictest0-21swapper/223:30:212
12740992211,0cyclictest0-21swapper/120:43:111
12740992210,11cyclictest0-21swapper/123:13:501
1274099220,21cyclictest843-21systemd-network21:19:341
1274499210,19cyclictest14495-21snapd19:10:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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