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2025-12-28 - 08:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 28, 2025 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12645992414,0cyclictest0-21swapper/121:49:231
1264599230,7cyclictest0-21swapper/119:29:511
1264599220,4cyclictest0-21swapper/120:17:251
1264699208,11cyclictest0-21swapper/222:45:192
1264699204,15cyclictest0-21swapper/223:28:182
12646992018,1cyclictest0-21swapper/219:25:512
12646992016,3cyclictest0-21swapper/221:00:022
12646992016,3cyclictest0-21swapper/200:07:272
12646992010,0cyclictest0-21swapper/219:50:172
1264699200,4cyclictest11960-21perf23:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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