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2026-09-23 - 03:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Sep 22, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
579599340,1cyclictest0-21swapper/009:45:140
5802992624,0cyclictest0-21swapper/109:45:141
580299230,5cyclictest0-21swapper/111:07:361
580299220,18cyclictest0-21swapper/109:40:151
579599220,18cyclictest0-21swapper/012:18:470
579599220,18cyclictest0-21swapper/009:38:450
5806992120,0cyclictest0-21swapper/209:15:172
5795992118,2cyclictest4188-21timerandwakeup08:00:220
5806992018,1cyclictest28-21ksoftirqd/211:35:132
5806992017,2cyclictest28686-21cpuspeed_turbos07:50:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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