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2026-01-07 - 11:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 07, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1778699320,31cyclictest0-21swapper/022:30:130
17788992523,1cyclictest1100-21snmpd20:55:042
17788992523,1cyclictest1100-21snmpd20:55:032
1778699236,2cyclictest12033-21cat21:50:010
17788992216,3cyclictest455-21plymouthd20:10:172
1778799220,21cyclictest843-21systemd-network00:18:091
1778699225,16cyclictest24239-21expr22:10:130
1778799210,20cyclictest843-21systemd-network22:02:031
1778699214,3cyclictest18737-21grep23:55:160
1778699214,16cyclictest8281-21expr20:45:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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