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2026-04-12 - 11:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Apr 12, 2026 00:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2719899280,5cyclictest0-21swapper/021:06:540
27198992620,5cyclictest12071-21perf19:40:010
27198992521,3cyclictest0-21swapper/023:40:170
2719899243,1cyclictest0-21swapper/022:30:150
2719899240,4cyclictest0-21swapper/023:50:250
2720899236,16cyclictest1256-21ntp_kernel_pll_20:15:192
2719899231,16cyclictest11226-21nvmesmart_nvme000:20:170
2719899222,2cyclictest4141-21cut00:10:010
2719899220,16cyclictest15438-21tr00:30:150
27208992118,2cyclictest880-21rs:main2
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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