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2026-07-16 - 20:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jul 16, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4203992625,1cyclictest0-21swapper/108:00:151
4202992421,2cyclictest17598-21ntp_kernel_pll_12:15:180
420299240,19cyclictest12018-21latency_hist10:15:010
420499230,18cyclictest0-21swapper/212:35:162
4203992311,11cyclictest22458-21find11:30:101
420299230,5cyclictest0-21swapper/010:58:500
4204992214,4cyclictest0-21swapper/211:05:132
4203992213,5cyclictest0-21swapper/112:20:111
420299222,14cyclictest16295-21python311:20:000
420299210,20cyclictest843-21systemd-network10:42:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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