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2026-07-29 - 21:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 29, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3041499230,18cyclictest0-21swapper/112:33:201
3041399220,5cyclictest0-21swapper/008:05:000
3041399213,10cyclictest0-21swapper/007:40:400
3042099203,2cyclictest2858-21rs:main2
3042099203,16cyclictest5478-21acpi09:15:112
3042099203,16cyclictest5478-21acpi09:15:102
3041399202,11cyclictest6335-21cut10:15:010
3042099194,1cyclictest0-21swapper/209:59:032
30420991916,2cyclictest30347-21nfsd409:00:192
3042099190,1cyclictest0-21swapper/207:51:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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