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2026-06-22 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 22, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
564199220,1cyclictest11599-21kworker/2:212:34:322
564199220,18cyclictest0-21swapper/207:34:072
5636992213,0cyclictest0-21swapper/112:21:381
5641992119,1cyclictest28-21ksoftirqd/210:52:562
5641992119,1cyclictest0-21swapper/211:49:172
563699202,17cyclictest30579-21smtpd08:50:201
563699200,5cyclictest0-21swapper/111:07:311
563699200,5cyclictest0-21swapper/111:07:301
563699200,0cyclictest0-21swapper/108:35:171
5632992020,0cyclictest0-21swapper/011:45:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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