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2025-12-22 - 14:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Dec 22, 2025 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
902099340,31cyclictest0-21swapper/020:59:180
9029992320,2cyclictest31789-21wc00:35:132
902599220,18cyclictest0-21swapper/119:20:261
902599220,18cyclictest0-21swapper/119:20:251
9020992219,2cyclictest31603-21cstates22:40:130
902099220,18cyclictest0-21swapper/021:40:080
902999210,20cyclictest0-21swapper/223:01:552
902099216,14cyclictest0-21swapper/022:54:310
902099216,14cyclictest0-21swapper/022:54:300
902999204,15cyclictest3983-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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