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2026-07-06 - 07:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 06, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12941992726,0cyclictest0-21swapper/200:10:162
1293999263,18cyclictest0-21swapper/019:35:010
1294199230,22cyclictest843-21systemd-network23:29:492
1294099230,18cyclictest30055-21sed19:40:001
12941992212,0cyclictest0-21swapper/220:25:162
1294199220,18cyclictest0-21swapper/221:00:152
1293999220,21cyclictest843-21systemd-network22:51:430
12941992119,1cyclictest4844-21perf00:40:002
12941992117,3cyclictest0-21swapper/222:10:562
12940992117,3cyclictest0-21swapper/122:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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