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2026-04-16 - 15:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 16, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10739992610,1cyclictest21-21ksoftirqd/108:58:251
1073999240,21cyclictest26997-21grep10:30:161
1073999240,19cyclictest17228-21grep11:10:161
1074599236,11cyclictest0-21swapper/211:54:252
1074599214,16cyclictest0-21swapper/208:01:512
1074599212,16cyclictest8828-21fschecks_count10:55:152
1073999212,18cyclictest16076-21perf07:20:011
1073999210,17cyclictest0-21swapper/112:22:021
1073999202,15cyclictest0-21swapper/112:00:491
10739992017,2cyclictest0-21swapper/107:45:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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