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2026-08-24 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Aug 24, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14653993517,17cyclictest0-21swapper/222:10:122
14649993424,10cyclictest0-21swapper/119:19:241
14649993122,9cyclictest21-21ksoftirqd/122:36:341
1464999230,5cyclictest0-21swapper/120:15:481
1464899230,0cyclictest0-21swapper/020:02:110
1464899223,18cyclictest0-21swapper/022:46:200
14648992113,4cyclictest0-21swapper/022:17:370
14653992017,2cyclictest7837-21expr19:50:212
14653992011,5cyclictest0-21swapper/222:20:142
14653992011,5cyclictest0-21swapper/222:20:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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