You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-01 - 23:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Mar 01, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1917699270,22cyclictest0-21swapper/208:52:052
1917699254,20cyclictest0-21swapper/210:15:102
19175992414,0cyclictest0-21swapper/109:03:021
19176992314,5cyclictest0-21swapper/210:59:222
1917699230,2cyclictest31719-21cat12:15:212
1917699230,1cyclictest0-21swapper/208:30:202
19176992215,6cyclictest11016-21sed08:50:012
1917699221,2cyclictest28328-21nfsd412:10:142
1917699221,1cyclictest0-21swapper/210:30:142
1917699220,3cyclictest4255-21cat07:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional