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2025-12-23 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Dec 23, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1006299240,2cyclictest23203-21python308:30:020
1007399230,5cyclictest0-21swapper/212:15:242
1007399230,5cyclictest0-21swapper/211:34:302
1006799237,15cyclictest0-21swapper/109:35:411
1006299230,2cyclictest814-21ntpq11:35:230
1006299230,2cyclictest3976-21H222:10:210
1006299222,2cyclictest14158-21perf09:10:000
10062992222,0cyclictest0-21swapper/007:13:490
1006299222,1cyclictest0-21swapper/007:35:020
1006299220,2cyclictest31466-21ls08:40:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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