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2026-08-15 - 22:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Aug 15, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26063992414,9cyclictest0-21swapper/209:35:232
2606299225,16cyclictest29048-21perf09:10:021
2606299220,18cyclictest0-21swapper/111:47:371
2606199220,21cyclictest843-21systemd-network08:15:050
26062992111,0cyclictest0-21swapper/110:48:481
2606199210,20cyclictest20401-21kernelversion09:50:170
2606199210,18cyclictest0-21swapper/008:00:420
2606399204,15cyclictest0-21swapper/210:30:172
26063992016,3cyclictest0-21swapper/209:02:082
2606199204,15cyclictest0-21swapper/007:39:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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