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2026-05-14 - 07:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu May 14, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2113199262,23cyclictest0-21swapper/223:37:392
2113199262,23cyclictest0-21swapper/220:30:552
21131992517,6cyclictest14230-21sessionclean00:39:012
2113199244,19cyclictest0-21swapper/221:10:582
2113199243,20cyclictest22781-21date23:00:012
2113199242,21cyclictest18888-21cat21:55:132
2113199232,20cyclictest0-21swapper/200:15:122
2113199222,19cyclictest28-21ksoftirqd/220:05:152
2113199222,19cyclictest281362chrt20:16:332
21131992214,7cyclictest3716-21chrt21:29:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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