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2026-09-23 - 20:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 23, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29500992312,1cyclictest0-21swapper/110:25:161
29499992114,6cyclictest0-21swapper/010:26:290
2950199204,15cyclictest0-21swapper/211:15:412
2950199203,1cyclictest12741-21cat10:30:012
2949999200,2cyclictest0-21swapper/008:54:590
2950199192,2cyclictest29812-21proc_pri11:55:192
29501991914,2cyclictest3991-21H222:10:212
2950199190,16cyclictest4035-21H222:10:212
2950099194,1cyclictest0-21swapper/112:34:441
2950099190,16cyclictest4099-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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