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2026-09-16 - 07:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Sep 16, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1764799260,19cyclictest21156-21cut20:10:192
1764799230,5cyclictest0-21swapper/200:14:332
1764699230,7cyclictest0-21swapper/121:10:431
1764599231,18cyclictest0-21swapper/020:25:180
1764699210,7cyclictest843-21systemd-network20:46:011
1764799204,1cyclictest0-21swapper/221:59:142
17647992018,1cyclictest0-21swapper/219:35:182
17647992016,3cyclictest0-21swapper/221:16:052
1764799200,19cyclictest399-20systemd-journal22:32:352
17645992018,1cyclictest0-21swapper/020:40:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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