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2026-08-27 - 14:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Aug 27, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10579992213,5cyclictest0-21swapper/121:10:161
1058599210,6cyclictest1663-21sendmail23:40:012
1058599200,15cyclictest0-21swapper/222:34:592
1058599192,2cyclictest13704-21chrt23:04:572
1058599190,3cyclictest31786-21python320:45:002
1058599190,16cyclictest0-21swapper/200:00:172
1058599190,16cyclictest0-21swapper/200:00:172
10579991917,1cyclictest0-21swapper/119:21:051
10579991913,5cyclictest426-21systemd-udevd21:04:521
1057499193,9cyclictest20301-21python320:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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