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2026-07-10 - 15:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 10, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2422799336,15cyclictest0-21swapper/210:59:552
2422399263,22cyclictest0-21swapper/111:44:151
2422399240,3cyclictest4090-21expr10:20:131
2422399230,2cyclictest26150-21apache_accesses11:00:091
2422399230,2cyclictest10308-21hddtemp_smartct12:25:161
2422399230,1cyclictest3135-21munin-run07:30:011
2422399230,1cyclictest0-21swapper/110:50:201
2421899230,5cyclictest0-21swapper/012:15:010
2422399223,16cyclictest3976-21H222:10:211
24223992214,7cyclictest21789-21awk08:00:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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