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2026-02-04 - 11:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 04, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1493599246,8cyclictest0-21swapper/219:14:392
1492699230,3cyclictest0-21swapper/023:32:510
1492699230,18cyclictest0-21swapper/023:05:190
1493599203,11cyclictest22084-21logrotate00:09:262
14935992016,3cyclictest0-21swapper/223:27:242
14931992012,5cyclictest0-21swapper/119:35:221
14926992014,3cyclictest0-21swapper/019:46:100
1493599195,13cyclictest0-21swapper/219:59:432
1493599193,2cyclictest0-21swapper/219:15:182
14935991917,1cyclictest0-21swapper/223:35:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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