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2026-06-17 - 16:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jun 17, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11095992613,8cyclictest32275-21idleruntime08:40:161
11094992522,2cyclictest1021-21mii-tool12:30:130
1109699243,6cyclictest0-21swapper/211:04:222
11096992414,5cyclictest0-21swapper/208:15:132
1109699240,6cyclictest0-21swapper/210:55:492
1109699240,22cyclictest843-21systemd-network09:01:142
1109699232,1cyclictest0-21swapper/208:54:282
1109699231,1cyclictest0-21swapper/211:30:132
1109699230,3cyclictest28654-21users10:25:212
1109699230,3cyclictest0-21swapper/208:09:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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