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2026-09-08 - 02:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Sep 07, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1599899360,33cyclictest0-21swapper/109:40:191
1599399273,5cyclictest0-21swapper/011:34:590
15998992615,0cyclictest0-21swapper/108:41:041
15998992615,0cyclictest0-21swapper/108:41:041
1599399241,18cyclictest6035-21cat07:50:010
1599399230,8cyclictest0-21swapper/010:54:220
1599399230,8cyclictest0-21swapper/010:54:210
1599399230,5cyclictest0-21swapper/008:10:430
15993992213,0cyclictest0-21swapper/007:40:160
1599399220,21cyclictest843-21systemd-network10:03:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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