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2026-08-25 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 25, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1426299200,1cyclictest0-21swapper/020:50:160
1426299200,19cyclictest870-21systemd-logind23:18:520
1426499192,16cyclictest23917-21cat20:24:562
1426499192,16cyclictest17623-21taskset23:01:502
14264991914,1cyclictest0-21swapper/221:12:292
1426499190,16cyclictest3985-21H222:10:212
1426499190,16cyclictest3983-21H222:10:212
1426399193,15cyclictest32289-21sed22:30:221
1426399192,2cyclictest2612-21grep19:45:161
1426399192,16cyclictest8685-21cpuspeed_turbos21:50:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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