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2026-07-31 - 23:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jul 31, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2150599250,24cyclictest0-21swapper/209:10:132
21505992421,2cyclictest24155-21sort07:15:012
2150599230,22cyclictest0-21swapper/211:30:342
21500992320,2cyclictest21-21ksoftirqd/111:12:471
2150099230,5cyclictest0-21swapper/108:22:191
2149599231,4cyclictest0-21swapper/009:45:010
2150599220,6cyclictest0-21swapper/208:28:292
2149599224,17cyclictest0-21swapper/009:39:070
21505992113,4cyclictest0-21swapper/207:45:202
2150099214,11cyclictest0-21swapper/110:20:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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