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2026-07-04 - 19:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 04, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148499251,20cyclictest25166-21chrt08:49:201
148499250,20cyclictest19979-21chrt10:34:291
148499240,2cyclictest15355-21idleruntime10:25:191
148499240,23cyclictest12619-21cron07:30:011
148899230,18cyclictest0-21swapper/208:10:182
148499232,20cyclictest20315-21cpuspeed_turbos08:40:141
1484992314,8cyclictest13884-21cat11:20:001
148499230,16cyclictest9502-21fgrep09:15:201
148499230,16cyclictest27027-21cat09:50:011
1484992214,7cyclictest5213-21latency_hist11:05:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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