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2026-08-07 - 01:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Aug 06, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
827899252,18cyclictest0-21swapper/010:10:010
827999230,22cyclictest0-21swapper/108:25:111
828099220,18cyclictest0-21swapper/211:36:012
8279992214,5cyclictest25382-21latency10:25:171
8279992214,5cyclictest25382-21latency10:25:171
827999203,16cyclictest6116-21date09:55:001
827999200,19cyclictest870-21systemd-logind10:06:521
8280991913,5cyclictest0-21swapper/211:10:182
828099190,18cyclictest0-21swapper/208:35:092
827999192,16cyclictest30308-21grep09:40:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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