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2026-09-14 - 04:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Sep 14, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11166993130,0cyclictest0-21swapper/100:18:291
11166992522,2cyclictest0-21swapper/121:58:071
11167992323,0cyclictest0-21swapper/221:25:142
11167992114,2cyclictest10221-21kernelversion22:55:172
11167992113,6cyclictest0-21swapper/200:40:002
1116799210,6cyclictest399-20systemd-journal00:07:442
11165992118,2cyclictest0-21swapper/022:30:180
1116799203,16cyclictest9443-21smtpd21:57:352
11167992017,2cyclictest28675-21sshd22:31:252
11166992014,5cyclictest0-21swapper/100:00:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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