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2026-07-20 - 01:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 19, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17306992523,2cyclictest0-21swapper/109:32:521
1730599243,1cyclictest0-21swapper/011:26:330
17305992417,6cyclictest19863-21grep08:10:150
1730599235,14cyclictest0-21swapper/010:26:010
1730599232,15cyclictest25539-21cron12:10:010
17305992313,6cyclictest12438-21expr11:45:140
1730599230,21cyclictest8033-21pzem_current11:35:180
1730599230,1cyclictest0-21swapper/010:05:150
1730599222,1cyclictest0-21swapper/007:30:050
17305992216,5cyclictest0-21swapper/009:50:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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