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2026-09-01 - 12:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Tue Sep 01, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1254999271,25cyclictest0-21swapper/222:10:172
12549992321,1cyclictest0-21swapper/223:40:262
1254999230,18cyclictest0-21swapper/223:46:422
1254999212,5cyclictest0-21swapper/219:25:082
12549992117,3cyclictest0-21swapper/222:50:132
12549992117,3cyclictest0-21swapper/222:50:122
1254799214,2cyclictest3983-21H222:10:210
1254999203,16cyclictest28-21ksoftirqd/219:10:192
1254999202,3cyclictest4035-21H222:10:212
1254999202,16cyclictest3991-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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