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2026-06-15 - 00:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Jun 14, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26109992117,3cyclictest0-21swapper/209:02:412
26108992018,2cyclictest0-21swapper/109:41:171
26107992014,1cyclictest0-21swapper/011:03:150
2610799200,19cyclictest14505-21snapd09:05:360
2610999192,2cyclictest32328-21sendmail_mailtr08:15:202
2610999190,1cyclictest0-21swapper/212:30:112
2610999190,18cyclictest0-21swapper/212:18:232
2610899193,2cyclictest16765-21cupsd08:20:161
2610899193,15cyclictest0-21swapper/107:11:151
26108991917,1cyclictest8601-21awk08:30:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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