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2026-05-18 - 06:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon May 18, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1047299240,5cyclictest19429-21latency_hist23:15:010
1047799230,18cyclictest0-21swapper/222:04:502
10477992017,2cyclictest17096-21iwlist19:20:172
10477992015,4cyclictest0-21swapper/200:25:142
10472992017,2cyclictest3981-21H222:10:210
1047799192,16cyclictest30500-21smtpd23:33:502
10477991917,1cyclictest28-21ksoftirqd/223:06:452
1047799191,17cyclictest0-21swapper/200:00:222
1047799190,18cyclictest0-21swapper/221:40:142
1047799190,16cyclictest4035-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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