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2026-06-12 - 09:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Jun 12, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3144299340,1cyclictest0-21swapper/023:35:130
3144299240,19cyclictest0-21swapper/021:40:130
3144699230,5cyclictest3450-21gsd-color21:17:152
3144699230,5cyclictest3450-21gsd-color21:17:152
3144499228,13cyclictest0-21swapper/121:06:501
31444992217,4cyclictest0-21swapper/120:05:191
31444992118,2cyclictest455-21plymouthd23:35:131
31442992114,3cyclictest0-21swapper/023:24:240
31446992016,3cyclictest0-21swapper/219:25:432
31446992014,3cyclictest0-21swapper/221:00:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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