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2026-07-15 - 16:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 15, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30570992928,1cyclictest0-21swapper/211:20:172
3056699262,20cyclictest0-21swapper/111:50:521
3056699255,5cyclictest17716-21cat10:35:011
3056699236,16cyclictest11936-21awk12:15:181
30566992320,2cyclictest9697-21cpuspeed_turbos10:20:131
30566992318,3cyclictest20410-21sessionclean10:39:011
3056499230,22cyclictest3991-21H222:10:210
3056699225,16cyclictest7397-21fschecks_time10:15:171
3056699225,16cyclictest18809-21ntp_states08:40:201
30566992219,2cyclictest8278-21cron11:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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