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2025-05-09 - 05:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri May 09, 2025 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16671993322,10cyclictest11262-21cat20:55:002
1666999274,18cyclictest0-21swapper/019:35:000
1666999225,14cyclictest0-21swapper/000:27:520
1667099210,20cyclictest823-21systemd-network20:40:291
1667199196,12cyclictest0-21swapper/200:12:512
1667199193,15cyclictest0-21swapper/221:19:002
16671991915,3cyclictest1603-21lxd21:00:552
16670991917,1cyclictest0-21swapper/120:04:341
1667099190,18cyclictest0-21swapper/122:58:541
1667099190,18cyclictest0-21swapper/121:10:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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