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2026-07-27 - 06:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 27, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2460399230,5cyclictest0-21swapper/221:08:002
2459999220,20cyclictest0-21swapper/121:42:351
24594992220,1cyclictest1100-21snmpd19:21:250
2460399214,10cyclictest0-21swapper/219:40:012
24603992114,3cyclictest0-21swapper/220:29:222
2459999210,18cyclictest28592-21fschecks_count21:10:161
2459999201,18cyclictest17495-21grep20:50:151
24594992018,1cyclictest0-21swapper/000:40:010
24594992017,2cyclictest30428-21sessionclean23:09:000
2460399193,15cyclictest3989-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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