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2025-12-18 - 19:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Dec 18, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1605299263,18cyclictest0-21swapper/012:00:000
1605499241,15cyclictest0-21swapper/209:00:142
1605499214,3cyclictest0-21swapper/210:22:502
1605499214,16cyclictest0-21swapper/211:46:512
16054992117,3cyclictest0-21swapper/208:44:232
16054992117,3cyclictest0-21swapper/207:58:502
16054992117,2cyclictest2030-21sessionclean08:39:012
1605499210,19cyclictest399-20systemd-journal08:25:002
16052992117,2cyclictest3981-21H222:10:210
1605299210,4cyclictest0-21swapper/010:55:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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