You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-22 - 13:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 22, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27642993415,13cyclictest3986-21H222:10:210
2764299261,17cyclictest0-21swapper/021:55:110
2764399230,22cyclictest32262-21ntpq23:05:181
2764399220,21cyclictest9238-21sed21:25:231
2764399220,21cyclictest5382-21expr23:15:131
2764399220,21cyclictest5382-21expr23:15:121
2764399220,21cyclictest455-21plymouthd20:25:101
2764399220,21cyclictest32365-21cut21:10:191
2764399220,21cyclictest25687-21ls23:50:171
2764399220,21cyclictest20081-21awk21:45:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional