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2026-05-30 - 10:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot0.osadl.org (updated Sat May 30, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
593992718,0cyclictest0-21swapper/119:25:251
59399257,15cyclictest0-21swapper/123:25:121
59399240,24cyclictest0-21swapper/100:25:161
59299244,10cyclictest0-21swapper/019:25:030
59399239,0cyclictest0-21swapper/121:20:191
593992314,5cyclictest0-21swapper/123:35:201
59299225,2cyclictest14004-21nfsd423:20:160
59299222,17cyclictest0-21swapper/023:11:520
59299222,17cyclictest0-21swapper/023:11:520
59299220,18cyclictest0-21swapper/022:40:180
59399214,6cyclictest0-21swapper/122:50:131
593992113,4cyclictest0-21swapper/122:45:131
593992113,4cyclictest0-21swapper/122:45:131
59399210,20cyclictest1366-21nfsd422:00:181
59399210,18cyclictest399-20systemd-journal21:30:001
59299210,4cyclictest0-21swapper/000:38:180
59499202,2cyclictest4035-21H222:10:212
59499202,2cyclictest4035-21H222:10:212
59499200,4cyclictest0-21swapper/221:50:182
59399203,1cyclictest0-21swapper/123:18:591
592992018,1cyclictest0-21swapper/020:45:140
592992016,3cyclictest0-21swapper/000:28:090
594991916,2cyclictest3976-21H222:10:212
594991915,3cyclictest12150-21grep22:20:142
59499190,2cyclictest3991-21H222:10:212
59499190,2cyclictest3981-21H222:10:212
59499190,18cyclictest0-21swapper/223:44:382
59399190,5cyclictest0-21swapper/123:12:091
59399190,5cyclictest0-21swapper/123:12:091
59399190,18cyclictest0-21swapper/100:08:481
59299192,2cyclictest30106-21cpuspeed_turbos23:50:120
59299192,16cyclictest24185-21expr21:45:140
592991916,2cyclictest878-21in:imuxsock22:35:010
592991916,2cyclictest3981-21H222:10:210
59299190,2cyclictest3985-21H222:10:210
59299190,16cyclictest3989-21H222:10:210
59299190,16cyclictest3985-21H222:10:210
59499182,1cyclictest11025-21switchtime00:10:242
59499182,15cyclictest0-21swapper/223:49:102
59499182,15cyclictest0-21swapper/219:55:012
594991816,1cyclictest28-21ksoftirqd/200:35:562
594991816,1cyclictest21921-21cstates23:35:142
594991816,1cyclictest0-21swapper/221:41:522
594991816,1cyclictest0-21swapper/200:31:482
594991815,2cyclictest3989-21H222:10:212
594991815,2cyclictest2517-21chrt23:56:582
594991815,2cyclictest0-21swapper/221:25:512
594991814,3cyclictest3983-21H222:10:212
594991813,4cyclictest0-21swapper/219:56:342
59499180,2cyclictest3989-21H222:10:212
59499180,2cyclictest3983-21H222:10:212
59499180,2cyclictest3979-21H222:10:212
59499180,17cyclictest7060-21cut23:10:002
59499180,17cyclictest4035-21H222:10:212
59499180,17cyclictest3987-21H222:10:212
59499180,17cyclictest3976-21H222:10:212
59499180,16cyclictest4099-21H222:10:212
59499180,16cyclictest3983-21H222:10:212
59499180,16cyclictest3983-21H222:10:212
59499180,16cyclictest0-21swapper/220:30:162
59399182,15cyclictest9437-21grep22:15:141
59399182,15cyclictest21-21ksoftirqd/121:52:171
59399182,15cyclictest19598-21cat20:40:131
593991815,2cyclictest3979-21H222:10:211
593991815,2cyclictest21296-21cpuspeed_turbos21:40:141
593991814,3cyclictest3991-21H222:10:211
593991814,3cyclictest3987-21H222:10:211
59399181,16cyclictest4035-21H222:10:211
59399181,16cyclictest30510-21cpuspeed_turbos21:00:131
59399180,3cyclictest3985-21H222:10:211
59399180,3cyclictest2835-21awk00:00:001
59399180,2cyclictest3983-21H222:10:211
59399180,2cyclictest3981-21H222:10:211
59399180,1cyclictest19910-21tr22:35:141
59399180,18cyclictest0-21swapper/122:44:481
59399180,17cyclictest5495-21sed22:09:001
59399180,17cyclictest3981-21H222:10:211
59399180,17cyclictest3981-21H222:10:211
59399180,17cyclictest3976-21H222:10:211
59399180,16cyclictest3989-21H222:10:211
59299182,2cyclictest28173-21switchtime19:55:210
59299182,15cyclictest9-21ksoftirqd/021:57:020
59299182,15cyclictest12091-21grep00:15:120
592991816,1cyclictest9-21ksoftirqd/021:41:460
592991816,1cyclictest0-21swapper/020:32:140
592991815,2cyclictest6734-21expr00:05:150
592991815,2cyclictest27594-21missed_timers21:50:170
592991815,2cyclictest19192-21if_lxdbr019:40:150
592991815,2cyclictest10673-21sed22:15:210
59299180,2cyclictest3991-21H222:10:210
59299180,2cyclictest3979-21H222:10:210
59299180,2cyclictest3979-21H222:10:210
59299180,18cyclictest0-21swapper/023:41:410
59299180,17cyclictest3989-21H222:10:210
59299180,16cyclictest0-21swapper/023:47:340
59299180,15cyclictest3983-21H222:10:210
59299180,15cyclictest0-21swapper/021:25:160
594991715,1cyclictest0-21swapper/220:00:172
594991714,2cyclictest8637-21chrt21:15:212
594991714,2cyclictest7745-21processes00:05:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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