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2025-12-18 - 11:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot0.osadl.org (updated Thu Dec 18, 2025 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24208992523,1cyclictest9-21ksoftirqd/022:35:000
2421799240,23cyclictest19787-21perf22:50:012
2420899240,19cyclictest0-21swapper/000:30:000
2420899240,19cyclictest0-21swapper/000:29:590
2421799230,18cyclictest0-21swapper/223:35:142
2421299230,5cyclictest0-21swapper/120:55:111
2421799222,17cyclictest0-21swapper/220:55:202
2421799220,4cyclictest3986-21H222:10:212
2421799210,3cyclictest0-21swapper/221:03:282
2421799202,17cyclictest0-21swapper/220:20:442
2421799200,5cyclictest399-20systemd-journal23:03:022
2421799200,16cyclictest0-21swapper/220:03:462
2421799200,16cyclictest0-21swapper/220:03:462
2421299203,16cyclictest0-21swapper/119:21:321
2420899200,16cyclictest0-21swapper/021:28:340
2421799193,15cyclictest11943-21head20:40:172
2421799193,15cyclictest0-21swapper/223:10:132
2421799192,2cyclictest23920-21cat22:55:172
2421799192,16cyclictest0-21swapper/219:33:592
2421799192,15cyclictest0-21swapper/221:58:392
24217991917,1cyclictest11698-21sed19:45:012
24217991916,2cyclictest28670-21cat20:15:022
24217991916,2cyclictest0-21swapper/223:05:142
24217991916,2cyclictest0-21swapper/223:05:132
2421799191,17cyclictest21502-21nfsd422:50:172
2421799191,17cyclictest0-21swapper/219:19:002
2421799190,18cyclictest0-21swapper/219:54:322
2421799190,17cyclictest981-21cpuspeed_turbos21:20:132
2421799190,17cyclictest981-21cpuspeed_turbos21:20:132
24212991915,3cyclictest0-21swapper/100:11:411
2421299190,16cyclictest4035-21H222:10:211
2421299190,16cyclictest3983-21H222:10:211
2420899193,15cyclictest9251-21grep23:25:210
24208991917,1cyclictest9-21ksoftirqd/020:07:390
24208991917,1cyclictest9-21ksoftirqd/019:27:210
24208991917,1cyclictest3989-21H222:10:210
24208991916,2cyclictest3987-21H222:10:210
24208991916,2cyclictest22876-21needreboot23:50:150
24208991915,2cyclictest31230-21nfsd419:20:180
24208991914,3cyclictest0-21swapper/022:15:140
2420899190,2cyclictest3985-21H222:10:210
2420899190,18cyclictest0-21swapper/019:33:410
2420899190,17cyclictest19614-21turbostat20:00:010
2420899190,16cyclictest3979-21H222:10:210
2421799183,1cyclictest28-21ksoftirqd/219:48:582
2421799182,1cyclictest258962chrt22:03:392
2421799182,1cyclictest14026-21cut20:45:132
2421799182,15cyclictest0-21swapper/200:04:532
24217991816,1cyclictest3983-21H222:10:212
24217991816,1cyclictest0-21swapper/200:37:202
24217991816,1cyclictest0-21swapper/200:30:122
24217991815,2cyclictest23039-21nfsd423:50:162
24217991814,3cyclictest28891-21latency_hist22:10:012
24217991814,3cyclictest11472-21munin-run22:35:012
2421799181,3cyclictest0-21swapper/223:57:552
24217991813,3cyclictest3983-21H222:10:212
2421799181,16cyclictest9058-21pzem_voltage23:25:192
2421799181,16cyclictest4763-21idleruntime-cro20:30:002
2421799181,16cyclictest3992-21H222:10:212
2421799180,2cyclictest4099-21H222:10:212
2421799180,17cyclictest4099-21H222:10:212
2421799180,17cyclictest3985-21H222:10:212
2421799180,17cyclictest18060-21cat21:50:012
2421799180,17cyclictest18060-21cat21:50:002
2421799180,17cyclictest0-21swapper/223:45:232
2421799180,17cyclictest0-21swapper/221:05:222
2421799180,17cyclictest0-21swapper/220:35:192
2421799180,15cyclictest3983-21H222:10:212
2421799180,15cyclictest0-21swapper/219:35:132
2421299182,15cyclictest266822chrt23:59:031
2421299182,15cyclictest21-21ksoftirqd/120:18:101
24212991816,1cyclictest21-21ksoftirqd/119:15:341
24212991816,1cyclictest11869-21missed_timers20:40:181
24212991816,1cyclictest0-21swapper/120:34:001
24212991815,1cyclictest0-21swapper/121:43:321
24212991814,3cyclictest4099-21H222:10:211
24212991814,3cyclictest4099-21H222:10:211
2421299181,2cyclictest9050-21needreboot20:35:191
2421299181,1cyclictest3976-21H222:10:211
2421299180,2cyclictest3976-21H222:10:211
2421299180,16cyclictest8355-21sshd22:30:021
2420899182,15cyclictest0-21swapper/000:30:270
24208991816,1cyclictest0-21swapper/020:30:130
24208991815,2cyclictest3989-21H222:10:210
24208991815,2cyclictest3989-21H222:10:210
24208991815,2cyclictest0-21swapper/000:20:330
24208991815,1cyclictest0-21swapper/023:42:020
24208991814,3cyclictest3981-21H222:10:210
24208991814,3cyclictest0-21swapper/021:03:590
2420899181,3cyclictest0-21swapper/021:56:290
2420899181,16cyclictest0-21swapper/021:41:540
2420899180,17cyclictest3985-21H222:10:210
2420899180,16cyclictest2978-21tail23:15:180
2420899180,16cyclictest15235-21grep20:45:170
24217991714,2cyclictest5001-21latency21:25:172
24217991714,2cyclictest4035-21H222:10:212
24217991714,2cyclictest29798-21expr22:10:132
24217991714,2cyclictest1347-21lxd19:56:242
2421799171,1cyclictest0-21swapper/221:35:212
2421799171,15cyclictest2955-21cat19:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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