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2026-02-22 - 14:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 22, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27642993415,13cyclictest3986-21H222:10:210
2764299261,17cyclictest0-21swapper/021:55:110
2764399230,22cyclictest32262-21ntpq23:05:181
2764399220,21cyclictest9238-21sed21:25:231
2764399220,21cyclictest5382-21expr23:15:131
2764399220,21cyclictest5382-21expr23:15:121
2764399220,21cyclictest455-21plymouthd20:25:101
2764399220,21cyclictest32365-21cut21:10:191
2764399220,21cyclictest25687-21ls23:50:171
2764399220,21cyclictest20081-21awk21:45:181
2764399220,21cyclictest13955-21ps00:25:221
2764399220,21cyclictest0-21swapper/123:40:171
2764399220,21cyclictest0-21swapper/122:45:161
2764399220,21cyclictest0-21swapper/121:21:051
2764399220,21cyclictest0-21swapper/119:20:211
2764299227,14cyclictest0-21swapper/023:10:140
27642992218,3cyclictest11027-21fschecks_count23:25:140
27643992114,6cyclictest31268-21idleruntime00:00:161
27643992114,6cyclictest18559-21cat21:45:011
2764399211,19cyclictest31186-21cut20:10:171
2764399210,6cyclictest31544-21sed22:05:211
2764399210,6cyclictest24344-21cut20:55:211
2764399210,6cyclictest21293-21awk20:50:181
2764399210,20cyclictest29647-21sed19:10:231
2764399210,20cyclictest28656-21awk23:55:151
2764399210,20cyclictest25837-21expr22:55:141
2764399210,20cyclictest22198-21expr23:45:141
2764399210,20cyclictest13868-21sed21:35:181
2764399210,20cyclictest1080-21if_enp1s022:10:171
2764399210,20cyclictest0-21swapper/123:30:191
2764399210,20cyclictest0-21swapper/123:25:211
2764399210,20cyclictest0-21swapper/122:35:141
2764399210,20cyclictest0-21swapper/122:25:141
2764399210,20cyclictest0-21swapper/120:21:191
2764399210,20cyclictest0-21swapper/120:05:151
2764399210,20cyclictest0-21swapper/119:40:171
2764399210,20cyclictest0-21swapper/119:25:121
2764399210,20cyclictest0-21swapper/100:40:001
2764399210,19cyclictest0-21swapper/120:40:191
2764299215,12cyclictest0-21swapper/023:40:140
27643992014,5cyclictest4326-21uname22:15:161
27643992014,5cyclictest28612-21grep22:00:221
27643992014,5cyclictest0-21swapper/122:50:111
27643992014,5cyclictest0-21swapper/122:50:111
27643992014,5cyclictest0-21swapper/120:00:141
27643992013,6cyclictest0-21swapper/100:15:151
2764399201,18cyclictest276292chrt21:02:551
2764399200,5cyclictest30494-21perf23:05:011
2764399200,19cyclictest9647-21cut20:30:161
2764399200,19cyclictest1550-21snapd19:30:091
2764399200,19cyclictest1525-21lxd19:52:481
2764399200,19cyclictest137662sleep120:37:411
2764399200,19cyclictest0-21swapper/123:35:141
2764399200,19cyclictest0-21swapper/123:11:261
2764399200,19cyclictest0-21swapper/122:43:411
2764399200,19cyclictest0-21swapper/122:30:161
2764399200,19cyclictest0-21swapper/122:24:261
2764399200,19cyclictest0-21swapper/121:30:141
2764399200,19cyclictest0-21swapper/121:30:131
2764399200,19cyclictest0-21swapper/121:05:171
2764399200,19cyclictest0-21swapper/119:55:161
2764399200,19cyclictest0-21swapper/119:45:131
2764399200,19cyclictest0-21swapper/100:20:161
2764399200,19cyclictest0-21swapper/100:05:211
27642992019,1cyclictest9-21ksoftirqd/000:25:150
27642992018,1cyclictest0-21swapper/021:08:510
27644991916,2cyclictest30903-21needreboot22:05:182
27644991913,4cyclictest3987-21H222:10:212
2764499190,3cyclictest0-21swapper/200:07:052
27643991914,5cyclictest0-21swapper/121:55:131
27643991912,6cyclictest1359-21latency20:15:171
2764399190,19cyclictest0-21swapper/100:30:171
2764399190,18cyclictest0-21swapper/121:50:161
2764399190,18cyclictest0-21swapper/121:15:141
2764399190,18cyclictest0-21swapper/120:45:131
2764399190,18cyclictest0-21swapper/119:35:151
2764399190,18cyclictest0-21swapper/100:10:181
2764399190,17cyclictest0-21swapper/119:15:141
2764299192,2cyclictest32045-21grep23:05:170
2764499182,15cyclictest28-21ksoftirqd/200:35:092
27644991815,2cyclictest30714-21expr00:00:142
2764399180,17cyclictest0-21swapper/123:20:131
2764299182,1cyclictest3712chrt19:17:550
2764299182,15cyclictest17263-21grep21:40:190
27642991816,1cyclictest9-21ksoftirqd/019:40:180
27642991816,1cyclictest0-21swapper/020:35:210
2764299181,1cyclictest111rcu_preempt20:28:400
2764299181,16cyclictest30419-21grep22:05:150
2764299180,3cyclictest1521-21lxd20:06:480
2764299180,0cyclictest0-21swapper/021:46:070
27644991715,1cyclictest11581-21/usr/sbin/munin22:30:112
27644991715,1cyclictest0-21swapper/221:00:222
27644991715,1cyclictest0-21swapper/219:30:142
27644991714,2cyclictest8603-21cut22:25:002
27644991714,2cyclictest30095-21timerwakeupswit21:05:212
27644991714,2cyclictest29515-21nfsd423:00:172
27644991714,2cyclictest29366-21nvmesmart_nvme019:10:212
27644991714,2cyclictest22795-21cpuspeed_turbos20:55:132
27644991714,2cyclictest18656-21nvmesmart_nvme022:40:212
27644991714,2cyclictest18618-21sessionclean23:39:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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