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2025-12-07 - 11:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 07, 2025 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3080499236,16cyclictest4528-21H212:26:332
3080499230,5cyclictest0-21swapper/219:27:022
3080299234,18cyclictest0-21swapper/122:42:521
3080199231,0cyclictest0-21swapper/022:35:110
3080199230,18cyclictest0-21swapper/023:21:120
30801992214,4cyclictest0-21swapper/021:43:400
3080499210,20cyclictest414-20systemd-journal00:29:552
3080499210,20cyclictest0-21swapper/219:42:082
30801992120,1cyclictest9-21ksoftirqd/023:50:150
30801992112,5cyclictest9-21ksoftirqd/019:58:150
3080199210,1cyclictest0-21swapper/021:50:180
3080499191,2cyclictest4523-21H212:26:332
3080499190,16cyclictest4581-21H212:26:332
3080499190,16cyclictest4534-21H212:26:332
3080499190,15cyclictest0-21swapper/219:10:182
3080299192,16cyclictest0-21swapper/121:43:241
30802991917,1cyclictest0-21swapper/123:23:281
30802991916,2cyclictest4523-21H212:26:331
30802991915,3cyclictest0-21swapper/122:11:061
30802991914,4cyclictest0-21swapper/119:16:351
30802991914,1cyclictest0-21swapper/121:30:201
3080299191,15cyclictest0-21swapper/119:35:021
3080299190,16cyclictest4538-21H212:26:331
30801991917,1cyclictest0-21swapper/023:58:280
30801991917,1cyclictest0-21swapper/023:11:510
30801991917,1cyclictest0-21swapper/023:08:060
30801991914,2cyclictest4526-21H212:26:330
3080199190,18cyclictest823-21systemd-network22:12:400
3080199190,18cyclictest0-21swapper/021:38:360
3080199190,18cyclictest0-21swapper/020:53:180
3080199190,18cyclictest0-21swapper/019:30:050
3080199190,16cyclictest4530-21H212:26:330
3080199190,16cyclictest4528-21H212:26:330
3080499182,1cyclictest0-21swapper/222:51:062
3080499182,15cyclictest0-21swapper/220:35:102
30804991816,1cyclictest4581-21H212:26:332
30804991816,1cyclictest0-21swapper/222:14:182
30804991816,1cyclictest0-21swapper/220:20:192
30804991815,2cyclictest4166-21if_enp1s020:15:182
30804991813,2cyclictest4528-21H212:26:332
3080499181,2cyclictest19310-21sort23:35:002
3080499180,4cyclictest0-21swapper/221:57:122
3080499180,4cyclictest0-21swapper/221:57:122
3080499180,3cyclictest25723-21munin-run20:55:012
3080499180,3cyclictest1304-21lxd19:30:572
3080499180,2cyclictest4534-21H212:26:332
3080499180,2cyclictest4530-21H212:26:332
3080499180,1cyclictest0-21swapper/222:20:162
3080499180,17cyclictest4581-21H212:26:332
3080499180,17cyclictest4536-21H212:26:332
3080499180,17cyclictest2049-21systemd-journal19:49:432
3080499180,17cyclictest0-21swapper/220:10:182
3080499180,16cyclictest4581-21H212:26:332
3080499180,16cyclictest4534-21H212:26:332
3080499180,16cyclictest4534-21H212:26:332
3080499180,15cyclictest4581-21H212:26:332
3080499180,15cyclictest4581-21H212:26:332
3080299182,15cyclictest21-21ksoftirqd/123:19:471
3080299182,15cyclictest0-21swapper/119:50:221
30802991817,0cyclictest21-21ksoftirqd/121:50:181
30802991816,1cyclictest0-21swapper/123:57:401
30802991816,1cyclictest0-21swapper/123:38:571
30802991814,3cyclictest4534-21H212:26:331
30802991814,3cyclictest4532-21H212:26:331
30802991814,2cyclictest4523-21H212:26:331
30802991814,1cyclictest0-21swapper/119:40:191
3080299181,15cyclictest111rcu_preempt19:14:201
3080299180,3cyclictest4523-21H212:26:331
3080299180,3cyclictest1355-21lxd21:04:571
3080299180,2cyclictest4593-21H212:26:331
3080299180,2cyclictest4534-21H212:26:331
3080299180,2cyclictest4528-21H212:26:331
3080299180,1cyclictest0-21swapper/119:46:401
3080299180,1cyclictest0-21swapper/100:15:141
3080299180,17cyclictest4538-21H212:26:331
3080299180,17cyclictest4528-21H212:26:331
3080299180,16cyclictest4532-21H212:26:331
3080299180,16cyclictest4532-21H212:26:331
3080299180,15cyclictest4523-21H212:26:331
3080199182,15cyclictest101rcuc/019:37:570
30801991816,1cyclictest0-21swapper/020:05:410
30801991813,1cyclictest111rcu_preempt19:20:150
30801991813,1cyclictest111rcu_preempt19:20:150
3080199180,3cyclictest4593-21H212:26:330
3080199180,3cyclictest19038-21grep19:45:170
3080199180,2cyclictest4593-21H212:26:330
3080199180,2cyclictest4526-21H212:26:330
3080199180,1cyclictest0-21swapper/023:19:520
3080199180,17cyclictest4536-21H212:26:330
3080199180,17cyclictest4528-21H212:26:330
3080199180,16cyclictest4593-21H212:26:330
3080199180,15cyclictest4534-21H212:26:330
3080199180,15cyclictest4530-21H212:26:330
3080199180,15cyclictest4530-21H212:26:330
30804991715,1cyclictest0-21swapper/223:15:172
30804991714,2cyclictest8414-21cpuspeed_turbos21:20:142
30804991714,2cyclictest4869-21grep00:05:152
30804991714,2cyclictest4593-21H212:26:332
30804991714,2cyclictest4528-21H212:26:332
30804991714,2cyclictest3752-21wc21:10:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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