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2026-09-24 - 20:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot0.osadl.org (updated Thu Sep 24, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1829699234,11cyclictest8335-21munin-run07:50:010
1829899220,19cyclictest18107-21nfsd410:55:182
1829699222,17cyclictest0-21swapper/009:05:170
18298992114,6cyclictest0-21swapper/210:10:212
1829899201,16cyclictest3985-21H222:10:212
1829799204,1cyclictest0-21swapper/107:30:521
18297992017,2cyclictest3989-21H222:10:211
18296992017,2cyclictest28392-21mailstats07:25:210
1829899193,15cyclictest23011-21latency09:10:162
18298991916,2cyclictest31105-21nfsd412:15:162
1829899190,1cyclictest0-21swapper/212:04:052
1829899190,16cyclictest4099-21H222:10:212
1829899190,16cyclictest3989-21H222:10:212
1829799194,1cyclictest0-21swapper/107:17:471
1829799193,15cyclictest0-21swapper/109:24:161
1829799192,3cyclictest0-21swapper/108:45:171
18297991915,2cyclictest415-21cpuspeed_turbos12:20:111
1829799190,18cyclictest0-21swapper/107:36:291
1829799190,16cyclictest3985-21H222:10:211
18296991917,1cyclictest0-21swapper/012:15:230
18296991917,1cyclictest0-21swapper/010:20:060
18296991916,2cyclictest4099-21H222:10:210
18296991916,2cyclictest0-21swapper/007:43:330
18296991913,2cyclictest0-21swapper/012:05:230
18296991913,2cyclictest0-21swapper/012:05:220
1829699190,1cyclictest0-21swapper/010:02:120
1829699190,18cyclictest3983-21H222:10:210
1829699190,18cyclictest0-21swapper/008:24:500
1829699190,16cyclictest3989-21H222:10:210
1829699190,16cyclictest3981-21H222:10:210
1829899182,15cyclictest27480-21ntp_offset08:20:182
18298991816,1cyclictest24719-21grep07:20:162
18298991816,1cyclictest24719-21grep07:20:152
18298991816,1cyclictest0-21swapper/208:30:282
18298991816,1cyclictest0-21swapper/207:12:192
18298991815,2cyclictest21066-21proc_pri11:00:212
18298991814,3cyclictest0-21swapper/210:46:522
1829899181,2cyclictest17922-21proc_pri09:00:222
1829899181,16cyclictest21538-21cut10:05:192
1829899180,2cyclictest3989-21H222:10:212
1829899180,2cyclictest3989-21H222:10:212
1829899180,2cyclictest3989-21H222:10:212
1829899180,2cyclictest3985-21H222:10:212
1829899180,2cyclictest3983-21H222:10:212
1829899180,2cyclictest3976-21H222:10:212
1829899180,2cyclictest3976-21H222:10:212
1829899180,17cyclictest4099-21H222:10:212
1829899180,17cyclictest3991-21H222:10:212
1829899180,17cyclictest3976-21H222:10:212
1829899180,17cyclictest28589-21nvmesmart_nvme012:10:232
1829899180,17cyclictest0-21swapper/211:50:142
1829899180,16cyclictest3985-21H222:10:212
1829899180,16cyclictest3985-21H222:10:212
1829899180,16cyclictest3976-21H222:10:212
1829799182,15cyclictest21-21ksoftirqd/109:45:321
18297991816,1cyclictest8182-21apt-key10:40:011
18297991816,1cyclictest0-21swapper/111:10:151
18297991816,1cyclictest0-21swapper/108:27:541
18297991816,1cyclictest0-21swapper/107:40:291
18297991815,2cyclictest3985-21H222:10:211
18297991815,2cyclictest3985-21H222:10:211
18297991814,3cyclictest3989-21H222:10:211
18297991814,3cyclictest3989-21H222:10:211
18297991814,3cyclictest3976-21H222:10:211
18297991814,3cyclictest3414-21master08:56:311
18297991814,3cyclictest29066-21bounce07:29:341
18297991814,3cyclictest17861-21cstates10:00:141
18297991814,3cyclictest1521-21lxd11:06:421
18297991814,2cyclictest0-21swapper/110:25:191
18297991810,4cyclictest0-21swapper/112:39:191
1829799180,2cyclictest3991-21H222:10:211
1829799180,2cyclictest3991-21H222:10:211
1829799180,2cyclictest3981-21H222:10:211
1829799180,2cyclictest3979-21H222:10:211
1829799180,2cyclictest3979-21H222:10:211
1829799180,2cyclictest3976-21H222:10:211
1829799180,17cyclictest4099-21H222:10:211
1829799180,17cyclictest4099-21H222:10:211
1829799180,17cyclictest21078-21latency_hist07:15:001
1829799180,17cyclictest0-21swapper/109:04:381
1829799180,16cyclictest3989-21H222:10:211
1829799180,16cyclictest3989-21H222:10:211
1829799180,16cyclictest3976-21H222:10:211
18296991816,1cyclictest9-21ksoftirqd/008:56:510
18296991814,3cyclictest25384-21cpuspeed_turbos11:10:150
18296991814,2cyclictest4099-21H222:10:210
18296991813,4cyclictest32762-21latency_hist09:30:000
1829699181,16cyclictest3979-21H222:10:210
1829699180,3cyclictest4099-21H222:10:210
1829699180,3cyclictest4099-21H222:10:210
1829699180,3cyclictest4099-21H222:10:210
1829699180,2cyclictest4099-21H222:10:210
1829699180,2cyclictest4099-21H222:10:210
1829699180,2cyclictest3981-21H222:10:210
1829699180,2cyclictest3979-21H222:10:210
1829699180,1cyclictest0-21swapper/007:15:450
1829699180,17cyclictest4099-21H222:10:210
1829699180,15cyclictest3981-21H222:10:210
1829699180,15cyclictest3981-21H222:10:210
18298991714,2cyclictest5655-21expr10:35:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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