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2026-09-01 - 16:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot0.osadl.org (updated Tue Sep 01, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2391299240,19cyclictest7314-21fschecks_count11:25:140
2391299240,19cyclictest0-21swapper/011:15:000
2392199230,16cyclictest4036-21H222:10:212
2391299230,18cyclictest0-21swapper/011:21:300
2391699220,17cyclictest0-21swapper/111:05:151
23921992117,3cyclictest22671-21smtp09:58:022
23916992116,4cyclictest0-21swapper/108:07:371
2392199203,16cyclictest3989-21H222:10:212
23921992016,3cyclictest0-21swapper/212:13:462
2392199200,3cyclictest0-21swapper/207:46:202
2391699202,3cyclictest3370-21ls11:20:001
23916992017,2cyclictest16438-21nvmesmart_nvme011:40:201
23912992017,2cyclictest3985-21H222:10:210
2391299200,5cyclictest0-21swapper/011:15:050
23921991916,1cyclictest0-21swapper/208:50:142
23921991915,3cyclictest0-21swapper/212:29:472
23921991913,3cyclictest0-21swapper/211:34:252
2392199191,16cyclictest1829-21systemd-journal08:13:222
2392199190,3cyclictest0-21swapper/209:35:152
2392199190,2cyclictest3987-21H222:10:212
2392199190,1cyclictest0-21swapper/212:00:012
2392199190,16cyclictest4099-21H222:10:212
2392199190,16cyclictest3985-21H222:10:212
2391699194,9cyclictest21365-21munin-run10:55:001
2391699192,2cyclictest30361-21ps10:10:211
2391699192,16cyclictest6217-21chrt11:24:481
23916991917,1cyclictest0-21swapper/111:30:171
23916991914,2cyclictest3976-21H222:10:211
2391699191,2cyclictest3981-21H222:10:211
2391699190,2cyclictest3981-21H222:10:211
2391699190,18cyclictest3981-21H222:10:211
2391699190,16cyclictest3983-21H222:10:211
2391699190,16cyclictest3979-21H222:10:211
2391299193,15cyclictest12338-21timerandwakeup10:35:240
2391299193,15cyclictest0-21swapper/007:52:430
23912991916,2cyclictest30972-21php7.012:09:000
2391299191,17cyclictest2196-21cpuspeed_turbos12:15:120
2391299190,2cyclictest3976-21H222:10:210
2391299190,17cyclictest1283-21gzip08:25:010
2391299190,16cyclictest3985-21H222:10:210
2391299190,16cyclictest3983-21H222:10:210
2391299190,16cyclictest3976-21H222:10:210
2392199182,1cyclictest28-21ksoftirqd/211:15:082
23921991816,1cyclictest29037-21expr09:10:212
23921991816,1cyclictest0-21swapper/210:26:312
23921991816,1cyclictest0-21swapper/210:03:372
23921991815,2cyclictest3985-21H222:10:212
23921991814,3cyclictest4099-21H222:10:212
23921991814,3cyclictest4035-21H222:10:212
23921991814,3cyclictest3991-21H222:10:212
2392199181,16cyclictest3989-21H222:10:212
2392199181,16cyclictest0-21swapper/208:30:402
2392199180,2cyclictest3987-21H222:10:212
2392199180,2cyclictest3976-21H222:10:212
2392199180,17cyclictest3981-21H222:10:212
2392199180,17cyclictest1060-21thermald10:47:352
2392199180,16cyclictest3979-21H222:10:212
2392199180,16cyclictest3976-21H222:10:212
2392199180,15cyclictest3985-21H222:10:212
2391699183,1cyclictest0-21swapper/110:25:331
2391699182,15cyclictest4035-21H222:10:211
2391699182,15cyclictest3979-21H222:10:211
2391699182,15cyclictest301702chrt08:16:571
23916991816,1cyclictest7650-21latency11:25:161
23916991816,1cyclictest0-21swapper/112:17:381
23916991816,1cyclictest0-21swapper/108:40:251
23916991815,2cyclictest3979-21H222:10:211
23916991815,2cyclictest31644-21nfsd411:10:191
23916991815,2cyclictest2411-21cat08:25:161
23916991815,1cyclictest0-21swapper/107:55:181
23916991814,3cyclictest3991-21H222:10:211
23916991813,4cyclictest0-21swapper/107:36:021
2391699180,2cyclictest4099-21H222:10:211
2391699180,16cyclictest4099-21H222:10:211
2391699180,16cyclictest3989-21H222:10:211
2391699180,16cyclictest3989-21H222:10:211
2391699180,15cyclictest3985-21H222:10:211
23912991816,1cyclictest0-21swapper/009:53:280
23912991815,2cyclictest17335-21sed08:50:210
2391299181,16cyclictest4100-21H222:10:210
2391299181,16cyclictest27250-21cut09:10:010
2391299180,4cyclictest0-21swapper/012:14:570
2391299180,3cyclictest3985-21H222:10:210
2391299180,2cyclictest3991-21H222:10:210
2391299180,2cyclictest3987-21H222:10:210
2391299180,2cyclictest3979-21H222:10:210
2391299180,2cyclictest3976-21H222:10:210
2391299180,17cyclictest3985-21H222:10:210
2391299180,16cyclictest3983-21H222:10:210
2391299180,15cyclictest3989-21H222:10:210
2391299180,15cyclictest3985-21H222:10:210
23921991716,1cyclictest0-21swapper/209:23:102
23921991715,1cyclictest28-21ksoftirqd/208:25:052
23921991715,1cyclictest0-21swapper/208:15:222
23921991714,2cyclictest29802-21cpuspeed_turbos07:20:152
23921991714,2cyclictest19339-21pzem09:50:222
23921991714,2cyclictest18265-21ls11:45:142
23921991714,2cyclictest16120-21cat07:50:232
23921991713,3cyclictest4099-21H222:10:212
2392199171,15cyclictest0-21swapper/207:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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