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2026-04-16 - 03:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 16, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27298992818,0cyclictest0-21swapper/121:24:371
2729899257,15cyclictest0-21swapper/120:48:001
2729899257,15cyclictest0-21swapper/120:48:001
27300992323,0cyclictest0-21swapper/220:15:162
27298992314,0cyclictest0-21swapper/122:17:341
27298992314,0cyclictest0-21swapper/119:15:051
2729799230,18cyclictest0-21swapper/000:08:590
2730099220,21cyclictest843-21systemd-network19:15:512
2729899224,11cyclictest0-21swapper/120:12:561
27300992017,1cyclictest0-21swapper/223:55:152
2730099200,19cyclictest1522-21lxd19:58:492
2729799201,18cyclictest19600-21idleruntime-cro20:50:010
2729799201,18cyclictest19600-21idleruntime-cro20:50:010
2730099193,9cyclictest14138-21munin-run00:30:012
2730099193,15cyclictest0-21swapper/223:49:282
27300991916,2cyclictest8881-21basename19:35:012
2729899190,17cyclictest26714-21nfsd421:00:181
2729799191,17cyclictest0-21swapper/023:04:250
2729799190,1cyclictest0-21swapper/022:23:240
2730099189,8cyclictest14607-21cut19:45:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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