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2026-06-26 - 14:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jun 26, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16634992726,1cyclictest0-21swapper/123:50:141
16634992523,1cyclictest1100-21snmpd23:08:261
16634992414,5cyclictest0-21swapper/121:14:231
1663499236,16cyclictest0-21swapper/100:12:191
16634992313,0cyclictest0-21swapper/122:25:441
1663499224,10cyclictest0-21swapper/100:32:201
16634992213,0cyclictest0-21swapper/122:20:581
1663399220,18cyclictest0-21swapper/021:42:340
16635992113,6cyclictest30030-21fschecks_count20:30:152
16634992112,0cyclictest0-21swapper/122:46:061
1663399210,20cyclictest843-21systemd-network23:44:270
1663599200,4cyclictest0-21swapper/219:30:012
16634992015,4cyclictest0-21swapper/100:15:111
1663499200,0cyclictest0-21swapper/121:51:501
1663399204,15cyclictest0-21swapper/021:28:250
1663399202,17cyclictest0-21swapper/022:30:140
1663599192,16cyclictest27214-21cpuspeed_turbos22:20:142
16635991917,1cyclictest0-21swapper/223:01:422
1663599190,17cyclictest8805-21fschecks_time23:40:142
1663499192,16cyclictest0-21swapper/121:55:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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