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2026-01-17 - 17:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 17, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13808992312,10cyclictest0-21swapper/107:32:011
13802992112,3cyclictest0-21swapper/010:00:010
1380899204,2cyclictest26061-21needreboot10:20:181
13808992017,2cyclictest15360-21if_enp1s011:55:161
1380899200,4cyclictest4221-21users12:30:211
13802992019,0cyclictest0-21swapper/012:10:170
1381599193,15cyclictest3979-21H222:10:212
13815991916,2cyclictest4099-21H222:10:212
13815991916,2cyclictest4035-21H222:10:212
1381599190,1cyclictest0-21swapper/208:45:012
1381599190,18cyclictest26181-21cron11:17:002
1381599190,16cyclictest3985-21H222:10:212
1381599190,16cyclictest3983-21H222:10:212
1380899193,11cyclictest4581-21gpgv07:50:011
1380899192,16cyclictest20878-21ps10:10:201
1380899192,16cyclictest0-21swapper/111:40:021
1380899192,15cyclictest0-21swapper/110:00:011
1380899190,2cyclictest30289-21cat10:30:001
1380899190,2cyclictest29986-21latency_hist08:35:001
1380899190,18cyclictest0-21swapper/108:10:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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