You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-20 - 00:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Feb 19, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114999265,13cyclictest0-21swapper/009:56:260
1150992515,9cyclictest0-21swapper/112:25:131
114999252,18cyclictest0-21swapper/009:50:010
1150992414,4cyclictest3134-21cut11:55:191
114999233,19cyclictest1496-21latency_hist11:55:000
1150992222,0cyclictest0-21swapper/111:05:161
1150992212,0cyclictest0-21swapper/109:20:461
1150992210,11cyclictest0-21swapper/108:56:191
114999220,19cyclictest0-21swapper/008:02:230
115099210,3cyclictest0-21swapper/109:35:381
114999210,7cyclictest843-21systemd-network07:34:270
115199206,13cyclictest0-21swapper/209:11:222
115199206,13cyclictest0-21swapper/209:11:212
115199202,17cyclictest0-21swapper/211:46:172
115199202,17cyclictest0-21swapper/208:45:342
115199202,17cyclictest0-21swapper/208:45:332
115199200,5cyclictest0-21swapper/212:19:332
115199200,5cyclictest0-21swapper/212:19:332
115199192,16cyclictest0-21swapper/212:32:302
115199192,16cyclictest0-21swapper/211:44:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional