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2026-05-07 - 11:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu May 07, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6039992321,1cyclictest0-21swapper/121:50:201
603899237,15cyclictest0-21swapper/019:47:030
603899230,23cyclictest0-21swapper/021:55:150
604099220,4cyclictest0-21swapper/200:09:572
6040992117,3cyclictest0-21swapper/222:20:322
604099204,15cyclictest0-21swapper/220:20:432
604099201,17cyclictest3058-21rs:main2
604099193,1cyclictest10411-21sessionclean22:08:592
604099192,1cyclictest3987-21H222:10:212
604099192,15cyclictest3987-21H222:10:212
6040991916,2cyclictest21732-21cut21:30:142
604099190,4cyclictest24115-21grep23:30:152
604099190,2cyclictest3987-21H222:10:212
604099190,1cyclictest0-21swapper/220:15:172
604099190,18cyclictest0-21swapper/220:25:132
604099190,16cyclictest3985-21H222:10:212
603999193,15cyclictest21-21ksoftirqd/122:39:131
6039991916,2cyclictest13410-21nfsd421:15:171
6039991915,3cyclictest0-21swapper/121:10:141
603999191,17cyclictest24333-21cat23:30:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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