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2026-05-06 - 09:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed May 06, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9182992514,1cyclictest0-21swapper/121:13:161
918299230,5cyclictest0-21swapper/121:45:401
918299230,5cyclictest0-21swapper/119:11:081
918299230,18cyclictest0-21swapper/119:53:211
9181992314,0cyclictest0-21swapper/021:13:170
918199230,18cyclictest0-21swapper/020:47:410
918399227,14cyclictest0-21swapper/220:50:182
918399227,14cyclictest0-21swapper/220:50:182
918199220,18cyclictest0-21swapper/021:42:120
9183992116,2cyclictest29644-21nvmesmart_nvme022:35:202
9182992120,0cyclictest0-21swapper/121:15:161
9181992118,2cyclictest27289-21fschecks_count21:35:160
918199210,3cyclictest0-21swapper/021:51:160
918399200,2cyclictest9548-21cstates23:55:132
918199203,16cyclictest0-21swapper/023:50:000
9181992018,1cyclictest0-21swapper/023:25:160
918399191,16cyclictest1655-21grep19:50:192
9182991918,0cyclictest0-21swapper/120:06:241
9182991917,1cyclictest6118-21uname20:55:201
9182991917,1cyclictest0-21swapper/123:20:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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