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2026-02-27 - 02:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Feb 26, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11925993028,1cyclictest0-21swapper/210:55:012
1192399220,6cyclictest0-21swapper/109:41:351
1191999220,18cyclictest0-21swapper/008:32:470
11925992019,0cyclictest0-21swapper/208:45:142
11925992018,1cyclictest0-21swapper/209:00:012
11925992018,1cyclictest0-21swapper/209:00:012
11925992016,3cyclictest3991-21H222:10:212
11925992010,7cyclictest17936-21cut10:10:132
1192399203,2cyclictest20323-21grep12:10:121
11925991915,3cyclictest3954-21VM22:10:212
11925991915,3cyclictest19663-21grep09:15:162
11925991914,4cyclictest26180-21cut12:20:132
1192599191,17cyclictest4874-21cut08:50:162
1192599190,18cyclictest0-21swapper/209:10:202
1192599190,18cyclictest0-21swapper/207:10:182
1192599190,17cyclictest21049-21package-data-do07:25:022
1192599183,1cyclictest32628-21nfsd412:30:172
1192599182,1cyclictest0-21swapper/211:05:152
1192599182,15cyclictest28035-21latency_hist10:30:012
1192599182,15cyclictest24990-21cat11:20:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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