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2026-02-03 - 22:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Feb 03, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2200992615,10cyclictest13716-21apache_accesses08:30:101
219999233,1cyclictest0-21swapper/007:59:090
219999230,5cyclictest0-21swapper/012:16:480
219999230,5cyclictest0-21swapper/012:16:480
2200992218,3cyclictest3053-21systemd-logind07:40:521
2200992217,2cyclictest4949-21pzem10:05:231
2201992117,3cyclictest0-21swapper/210:05:482
2201992114,3cyclictest0-21swapper/208:40:172
2201992016,3cyclictest0-21swapper/211:38:142
220199200,17cyclictest0-21swapper/208:26:572
219999204,1cyclictest0-21swapper/009:02:440
220199190,18cyclictest0-21swapper/212:05:052
220199190,18cyclictest0-21swapper/209:36:482
220199190,17cyclictest0-21swapper/208:02:142
220199190,16cyclictest3979-21H222:10:212
2199991915,3cyclictest2885-21iscsid11:35:180
2201991815,2cyclictest15622-21missed_timers10:25:172
2201991814,3cyclictest0-21swapper/212:30:172
2201991813,2cyclictest3983-21H222:10:212
220199180,17cyclictest843-21systemd-network11:48:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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