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2026-08-17 - 01:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Aug 16, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2013199234,13cyclictest0-21swapper/212:34:122
2013199230,6cyclictest0-21swapper/210:45:172
20131992214,5cyclictest0-21swapper/207:18:152
2012799214,2cyclictest17576-21nfsd408:00:181
20126992017,2cyclictest21989-21sort10:00:220
2012699200,19cyclictest0-21swapper/010:25:130
2013199192,16cyclictest498-21needreboot12:15:192
20131991917,1cyclictest0-21swapper/211:54:482
20131991917,1cyclictest0-21swapper/210:52:162
20131991913,3cyclictest0-21swapper/208:09:252
2013199190,1cyclictest0-21swapper/208:34:322
20127991914,3cyclictest9618-21proc_pri07:45:211
2012799190,16cyclictest3981-21H222:10:211
2012799190,16cyclictest3981-21H222:10:211
2012799190,16cyclictest3981-21H222:10:211
2012699192,2cyclictest28664-21chrt09:15:430
2012699192,2cyclictest20112-21chrt11:53:370
2012699192,16cyclictest13713-21grep08:50:190
2012699192,16cyclictest0-21swapper/009:28:120
2012699192,16cyclictest0-21swapper/008:17:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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