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2025-12-09 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Dec 09, 2025 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1953999250,24cyclictest21655-21grep11:55:140
1954099237,15cyclictest4536-21H212:26:331
1954199212,18cyclictest0-21swapper/210:47:232
1954099214,16cyclictest0-21swapper/111:57:061
1953999213,17cyclictest0-21swapper/010:37:280
19540992017,2cyclictest4532-21H212:26:331
1953999203,2cyclictest12410-21sed11:40:000
1953999202,3cyclictest0-21swapper/008:30:010
19539992017,2cyclictest10814-21expr10:40:140
19541991917,1cyclictest28-21ksoftirqd/208:45:192
19541991916,1cyclictest0-21swapper/211:55:422
19541991915,3cyclictest1403-21lxd08:01:052
1954199191,16cyclictest4538-21H212:26:332
1954199190,18cyclictest0-21swapper/211:40:012
1954199190,16cyclictest4538-21H212:26:332
1954199190,16cyclictest4532-21H212:26:332
1954199190,16cyclictest4526-21H212:26:332
1954199190,16cyclictest4523-21H212:26:332
19540991914,2cyclictest4593-21H212:26:331
1954099190,1cyclictest0-21swapper/111:02:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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