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2025-12-27 - 05:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Dec 27, 2025 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3881992414,9cyclictest21-21ksoftirqd/121:08:431
388099241,18cyclictest0-21swapper/000:30:000
3882992118,2cyclictest28630-21sed19:55:012
388099214,16cyclictest0-21swapper/021:09:550
388299202,2cyclictest3987-21H222:10:212
3882992018,1cyclictest0-21swapper/200:30:142
388099203,2cyclictest32272-21apt-key23:50:000
388099203,16cyclictest27190-21latency21:45:170
388099202,16cyclictest0-21swapper/000:24:570
3880992017,2cyclictest9-21ksoftirqd/000:05:000
388299192,16cyclictest30246-21expr19:55:172
388299190,4cyclictest3787-21nfsd420:05:172
388199193,15cyclictest0-21swapper/122:23:241
388199192,16cyclictest29059-21nfsd422:45:211
388199190,18cyclictest20231-21munin-run23:30:001
388199190,18cyclictest0-21swapper/121:25:131
388099192,2cyclictest20004-21chrt21:32:340
388099192,2cyclictest20004-21chrt21:32:330
388099192,16cyclictest8526-21cat21:10:230
388099192,16cyclictest3080-21if_enp1s020:05:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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