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2026-01-09 - 04:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Jan 09, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27610993430,4cyclictest0-21swapper/122:27:161
27610992927,2cyclictest0-21swapper/119:35:011
27610992727,0cyclictest0-21swapper/123:15:141
2760699230,5cyclictest0-21swapper/021:30:130
2761499220,19cyclictest0-21swapper/221:25:012
27610992112,1cyclictest0-21swapper/121:20:211
2760699214,16cyclictest3981-21H222:10:210
27606992118,2cyclictest1105-21php7.223:08:590
27606992114,3cyclictest0-21swapper/000:33:340
27610992016,3cyclictest0-21swapper/122:10:121
2760699203,2cyclictest10766-21expr23:25:140
2760699203,2cyclictest10766-21expr23:25:140
27614991916,2cyclictest29877-21ntp_offset23:00:172
27614991915,3cyclictest0-21swapper/220:59:052
2761499190,3cyclictest0-21swapper/222:40:142
2761499190,2cyclictest4099-21H222:10:212
2761499190,16cyclictest4099-21H222:10:212
2761499190,16cyclictest4035-21H222:10:212
2761099198,0cyclictest0-21swapper/122:05:151
2761099192,16cyclictest863-21avahi-daemon20:55:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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