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2026-07-26 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 26, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9575993017,7cyclictest9-21ksoftirqd/008:25:010
958699240,19cyclictest0-21swapper/211:45:132
9579992422,2cyclictest0-21swapper/110:40:201
958699230,18cyclictest0-21swapper/210:40:192
957999230,18cyclictest0-21swapper/112:07:351
957999230,18cyclictest0-21swapper/112:07:341
957999220,18cyclictest0-21swapper/108:31:191
9586992014,3cyclictest0-21swapper/210:58:492
957999202,14cyclictest0-21swapper/107:58:251
9579992018,1cyclictest21-21ksoftirqd/109:41:381
957599200,19cyclictest426-21systemd-udevd08:10:520
958699192,16cyclictest4035-21H222:10:212
958699192,16cyclictest19153-21grep11:10:202
9586991916,2cyclictest16215-21nfsd411:05:172
9586991916,1cyclictest0-21swapper/211:32:282
9586991915,3cyclictest0-21swapper/207:19:362
958699191,3cyclictest21304-21grep11:15:162
9586991913,5cyclictest0-21swapper/209:40:192
958699190,16cyclictest3976-21H222:10:212
9579991916,1cyclictest0-21swapper/110:02:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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