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2026-07-11 - 16:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jul 11, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30604992826,0cyclictest0-21swapper/109:30:221
30602992415,9cyclictest0-21swapper/011:27:160
30604992312,10cyclictest0-21swapper/111:40:161
3060299220,4cyclictest0-21swapper/011:22:250
3061099210,3cyclictest0-21swapper/210:30:192
30604992112,0cyclictest0-21swapper/111:27:161
3060499210,20cyclictest0-21swapper/112:25:181
30610992015,4cyclictest8044-21tr12:10:132
3061099200,3cyclictest0-21swapper/211:51:112
3060499203,16cyclictest2872-21systemd-logind09:20:521
30604992015,4cyclictest0-21swapper/110:30:141
3060299200,19cyclictest843-21systemd-network11:44:280
3061099190,8cyclictest0-21swapper/208:15:492
30604991916,2cyclictest17063-21plymouth07:40:211
3060499190,16cyclictest0-21swapper/112:15:161
30602991916,2cyclictest12978-21dump-pmu-power12:20:000
30602991914,3cyclictest0-21swapper/010:40:000
3060299190,18cyclictest0-21swapper/007:15:170
3060299190,0cyclictest0-21swapper/008:20:010
3061099183,1cyclictest10101-21cat09:20:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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