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2026-02-23 - 22:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 23, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
706199230,1cyclictest0-21swapper/010:10:000
7062992220,1cyclictest21-21ksoftirqd/110:00:581
706399210,20cyclictest843-21systemd-network08:34:382
706299214,16cyclictest2872-21systemd-logind07:10:521
706299210,3cyclictest0-21swapper/112:34:051
706199210,0cyclictest0-21swapper/011:28:270
706399200,19cyclictest843-21systemd-network09:05:382
706399200,17cyclictest14195-21nvmesmart_nvme010:10:202
706299203,11cyclictest10541-21munin-run09:10:011
706199201,18cyclictest0-21swapper/008:40:100
7063991917,1cyclictest3209-21JS22:10:212
706399190,1cyclictest0-21swapper/210:20:202
706399190,16cyclictest4035-21H222:10:212
706299193,1cyclictest0-21swapper/110:54:261
7062991916,2cyclictest1490-21snapd09:12:101
706299190,16cyclictest3985-21H222:10:211
706299190,16cyclictest3985-21H222:10:211
706299190,15cyclictest0-21swapper/108:20:171
706199193,15cyclictest9-21ksoftirqd/012:40:000
706199193,15cyclictest7389-21cut11:55:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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