You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-07 - 11:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 07, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14241992322,1cyclictest0-21swapper/000:20:170
14242992220,1cyclictest28179-21mii-tool23:25:161
1424299220,21cyclictest843-21systemd-network22:41:041
1424199210,5cyclictest0-21swapper/022:11:040
1424399202,17cyclictest0-21swapper/200:25:002
14243992018,1cyclictest0-21swapper/223:12:412
14242992017,2cyclictest6447-21grep21:45:131
14242992012,4cyclictest0-21swapper/123:36:501
14241992013,3cyclictest111rcu_preempt19:30:190
1424199200,2cyclictest0-21swapper/019:51:520
1424199200,19cyclictest870-21systemd-logind23:36:520
1424399193,2cyclictest22781-21nfsd420:20:192
14243991914,3cyclictest0-21swapper/221:24:372
1424399190,18cyclictest0-21swapper/220:43:292
1424399190,17cyclictest0-21swapper/223:16:412
1424299192,16cyclictest870-21systemd-logind21:26:511
14242991916,2cyclictest23608-21grep00:15:121
14241991915,3cyclictest0-21swapper/021:07:300
14241991913,1cyclictest111rcu_preempt20:05:200
1424399182,1cyclictest152902sleep220:07:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional