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2026-07-08 - 15:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jul 08, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1134799230,5cyclictest0-21swapper/109:28:421
11347992213,0cyclictest0-21swapper/111:30:161
11351992117,3cyclictest0-21swapper/212:18:222
11347992117,1cyclictest0-21swapper/112:25:141
1134299213,15cyclictest0-21swapper/008:30:130
11351992016,1cyclictest0-21swapper/211:32:262
1135199201,2cyclictest0-21swapper/210:15:202
1135199200,19cyclictest0-21swapper/210:36:132
1134799204,15cyclictest0-21swapper/109:17:291
11347992017,2cyclictest11792-21cstates10:00:131
1134799201,3cyclictest32741-21cpuspeed_turbos09:40:131
1134799200,1cyclictest0-21swapper/108:05:451
1134299202,3cyclictest0-21swapper/009:30:180
1135199193,11cyclictest29183-21perf12:25:002
1135199192,2cyclictest12257-21http_loadtime10:00:162
1135199190,2cyclictest3979-21H222:10:212
11347991917,1cyclictest10474-21cat09:55:211
11347991917,1cyclictest0-21swapper/107:50:161
11347991916,2cyclictest9402-21ntp_offset10:50:171
11347991916,2cyclictest27621-21sed07:39:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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