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2026-07-20 - 18:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 20, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2176699290,5cyclictest0-21swapper/111:19:381
2177199230,22cyclictest0-21swapper/210:35:002
2176699230,22cyclictest10152-21munin-run09:40:011
2176699230,16cyclictest6697-21latency08:35:181
2176699223,15cyclictest25901-21missed_timers07:15:201
21766992214,7cyclictest11474-21interrupts09:40:171
21766992214,6cyclictest21419-21http_loadtime08:05:161
21766992214,6cyclictest21419-21http_loadtime08:05:161
21766992214,3cyclictest29851-21which08:20:161
21766992214,2cyclictest2553-21sed12:15:231
2176699221,15cyclictest22757-21cpuspeed_turbos09:05:141
2176699220,2cyclictest27946-21anvil11:08:191
2176699220,2cyclictest10026-21grep08:40:201
2176699220,21cyclictest28943-21nvmesmart_nvme007:20:181
2176699220,17cyclictest843-21systemd-network07:26:361
2176699220,16cyclictest817-21cpuspeed_turbos07:30:141
2176699220,16cyclictest3240-21grep10:25:151
21761992212,5cyclictest18490-21latency_hist09:55:000
21771992114,2cyclictest20780-21if_lxdbr010:55:172
21766992115,5cyclictest8230-21expr12:25:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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