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2026-04-11 - 03:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Apr 11, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2998099310,1cyclictest0-21swapper/123:35:121
29980992826,1cyclictest0-21swapper/119:45:211
2998199260,21cyclictest27921-21chrt20:02:302
2998199240,23cyclictest19430-21cron00:35:002
2998199230,22cyclictest8812-21perf21:25:012
2998199230,22cyclictest2781-21cut22:10:152
2998199230,22cyclictest22239-21sed19:50:212
2998199230,22cyclictest20824-21expr21:45:142
2998199230,22cyclictest16518-21cat00:30:012
2998199230,22cyclictest15234-21sed22:30:222
2998199230,22cyclictest13357-21date20:35:002
29980992320,2cyclictest22455-21munin-plugin-st00:40:001
29980992314,3cyclictest22736-21cron23:45:011
2998199223,18cyclictest0-21swapper/200:02:362
2998199222,5cyclictest7996-21chrt00:13:542
29981992216,5cyclictest1424-21grep23:05:172
2998199221,20cyclictest3991-21H222:10:212
2998199220,7cyclictest18687-21apt22:40:002
2998199220,7cyclictest16432-21plymouth19:40:202
2998199220,2cyclictest32293-21if_err_lxdbr020:10:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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