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2026-04-23 - 18:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 23, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30504992718,0cyclictest0-21swapper/112:10:131
3050499240,0cyclictest0-21swapper/107:45:131
3050999230,5cyclictest0-21swapper/211:02:262
3050099232,4cyclictest0-21swapper/008:20:000
3050099230,5cyclictest0-21swapper/012:05:340
30504992117,3cyclictest0-21swapper/112:33:301
30504992114,3cyclictest0-21swapper/110:10:131
3050499210,19cyclictest843-21systemd-network09:12:521
3050099213,2cyclictest3981-21H222:10:210
3050999204,15cyclictest0-21swapper/209:46:492
3050999200,1cyclictest0-21swapper/210:35:012
3050999200,19cyclictest843-21systemd-network10:47:392
3050499204,15cyclictest0-21swapper/110:20:171
30504992017,2cyclictest7032-21sed11:09:011
30500992016,3cyclictest0-21swapper/011:29:460
3050999192,2cyclictest17258-21chrt12:23:592
3050999192,1cyclictest0-21swapper/209:10:102
30509991917,1cyclictest0-21swapper/208:35:052
3050999190,16cyclictest3979-21H222:10:212
3050499197,11cyclictest0-21swapper/107:16:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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