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2025-12-12 - 19:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Dec 12, 2025 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
612999230,5cyclictest0-21swapper/222:34:342
6120992314,5cyclictest0-21swapper/019:22:580
612699223,11cyclictest4565-21PluginScanner23:14:591
612699220,18cyclictest0-21swapper/119:36:041
6120992117,3cyclictest0-21swapper/000:38:150
612999204,9cyclictest0-21swapper/223:40:252
6129992016,1cyclictest0-21swapper/221:52:462
6120992017,2cyclictest4526-21H212:26:330
612999191,17cyclictest0-21swapper/223:15:182
612999190,2cyclictest4581-21H212:26:332
612999190,2cyclictest4523-21H212:26:332
612999190,18cyclictest0-21swapper/221:02:392
612999190,17cyclictest17701-21nvmesmart_nvme022:15:212
612999190,16cyclictest4536-21H212:26:332
6126991917,1cyclictest21-21ksoftirqd/100:29:331
6126991917,1cyclictest0-21swapper/121:17:051
612699190,2cyclictest4581-21H212:26:331
612699190,2cyclictest4536-21H212:26:331
612699190,16cyclictest21496-21cat21:30:001
612099192,16cyclictest14850-21grep22:10:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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