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2026-03-21 - 11:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Mar 21, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29858992617,0cyclictest0-21swapper/022:15:160
29859992423,0cyclictest0-21swapper/100:25:461
2985899244,19cyclictest0-21swapper/021:15:000
2986099230,20cyclictest0-21swapper/219:43:012
2985899230,22cyclictest0-21swapper/021:47:170
2985899212,16cyclictest0-21swapper/019:51:000
2985899210,17cyclictest0-21swapper/023:37:580
2985899200,2cyclictest5234-21latency_hist20:20:010
2986099192,11cyclictest12808-21sed23:25:002
2985999192,13cyclictest0-21swapper/121:55:151
29859991914,4cyclictest1517-21lxd21:16:491
2985899192,2cyclictest27024-21chrt20:57:030
29858991917,1cyclictest0-21swapper/021:30:300
29858991917,1cyclictest0-21swapper/020:04:540
29858991917,1cyclictest0-21swapper/020:04:530
2985899190,2cyclictest8196-21cat20:25:000
2985899190,2cyclictest25682-21cat22:50:010
2985899190,18cyclictest0-21swapper/022:42:460
2986099182,1cyclictest28-21ksoftirqd/221:00:272
29860991816,1cyclictest0-21swapper/223:33:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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