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2026-04-11 - 19:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Apr 11, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10546992826,2cyclictest0-21swapper/111:00:231
10546992322,0cyclictest0-21swapper/108:44:431
1054799220,18cyclictest0-21swapper/209:15:132
1054799210,20cyclictest843-21systemd-network11:31:262
1054599210,3cyclictest0-21swapper/007:26:350
10547992014,5cyclictest426-21systemd-udevd12:34:522
1054799200,5cyclictest870-21systemd-logind09:58:522
1054699204,15cyclictest0-21swapper/111:38:331
1054799192,2cyclictest30111-21smtpd10:32:292
1054799192,16cyclictest5717-21cpuspeed_turbos09:50:132
10547991918,1cyclictest32646-21kworker/2:008:44:422
10547991917,1cyclictest0-21swapper/208:10:272
1054799190,18cyclictest426-21systemd-udevd09:38:522
10546991916,2cyclictest13750-21uname09:05:201
1054699190,1cyclictest0-21swapper/110:20:001
1054599194,1cyclictest0-21swapper/012:38:140
1054599193,15cyclictest0-21swapper/009:34:020
10545991917,1cyclictest9-21ksoftirqd/008:30:140
10545991917,1cyclictest0-21swapper/011:08:590
10545991917,1cyclictest0-21swapper/009:58:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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