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2026-03-27 - 11:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Mar 27, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1025992214,5cyclictest0-21swapper/221:10:172
102599210,4cyclictest13582-21cstates23:40:142
1019992017,2cyclictest1652-21expr19:10:131
1015992017,2cyclictest3053-21systemd-logind20:08:520
1015992012,4cyclictest0-21swapper/022:50:140
102599192,16cyclictest0-21swapper/223:07:002
1025991914,3cyclictest0-21swapper/200:20:272
102599190,16cyclictest4035-21H222:10:212
101999193,1cyclictest17785-21timerandwakeup23:45:211
101999190,16cyclictest32534-21tr20:05:161
1015991917,1cyclictest0-21swapper/022:58:400
1015991917,1cyclictest0-21swapper/020:02:290
1015991916,2cyclictest426-21systemd-udevd23:24:520
1015991913,3cyclictest0-21swapper/020:50:170
1015991913,3cyclictest0-21swapper/020:50:170
101599190,18cyclictest0-21swapper/021:48:490
101599190,0cyclictest0-21swapper/020:27:040
102599182,1cyclictest0-21swapper/223:04:592
102599182,15cyclictest27974-21latency22:00:162
102599182,15cyclictest0-21swapper/220:10:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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