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2025-12-10 - 13:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Dec 10, 2025 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6598992928,0cyclictest0-21swapper/222:20:152
6598992311,11cyclictest1419-21kworker/2:221:40:002
659699230,18cyclictest0-21swapper/119:25:371
659699230,18cyclictest0-21swapper/119:15:161
659599230,5cyclictest0-21swapper/022:44:300
6598992113,4cyclictest0-21swapper/221:48:422
659899210,0cyclictest0-21swapper/221:30:142
659599213,17cyclictest9-21ksoftirqd/021:50:280
659899204,9cyclictest0-21swapper/221:50:202
659899204,11cyclictest6244-21munin-run23:55:002
659899203,16cyclictest28-21ksoftirqd/222:02:002
6596992019,1cyclictest21-21ksoftirqd/120:50:311
6596992019,1cyclictest21-21ksoftirqd/120:50:311
6598991917,1cyclictest0-21swapper/220:32:332
6598991916,2cyclictest5160-21processes20:00:232
6598991916,2cyclictest4534-21H212:26:332
659899191,12cyclictest0-21swapper/221:05:192
659899190,17cyclictest4538-21H212:26:332
659699192,2cyclictest23651-21chrt21:34:031
659699192,16cyclictest28830-21tr20:45:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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