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2025-05-03 - 01:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri May 02, 2025 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1111199231,19cyclictest24450-21python310:25:011
1111199220,3cyclictest0-21swapper/109:03:281
1111199220,18cyclictest0-21swapper/107:23:401
1111199220,18cyclictest0-21swapper/107:23:401
11110992214,4cyclictest0-21swapper/007:54:230
1111099220,18cyclictest0-21swapper/008:10:250
11112992118,2cyclictest0-21swapper/210:18:572
1111299204,15cyclictest28-21ksoftirqd/211:15:032
11112992018,1cyclictest0-21swapper/207:29:022
11112992013,4cyclictest15558-21dpkg08:15:012
11111992018,1cyclictest0-21swapper/111:46:021
11111992018,1cyclictest0-21swapper/107:58:401
11111992017,2cyclictest970-21dbus-daemon11:10:221
11111992014,2cyclictest27671-21tail09:30:211
1111299192,2cyclictest18924-21perf10:15:002
1111299192,16cyclictest0-21swapper/211:35:182
11112991915,3cyclictest0-21swapper/207:43:112
1111299190,3cyclictest0-21swapper/211:25:162
1111199193,15cyclictest30526-21latency_hist10:35:011
1111199192,16cyclictest6824-21dpkg10:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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