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2026-03-28 - 18:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Mar 28, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
669499270,26cyclictest0-21swapper/211:05:142
669499222,19cyclictest4396-21fschecks_count08:00:162
6694992214,4cyclictest0-21swapper/211:17:042
6689992113,5cyclictest0-21swapper/111:57:311
6685992114,3cyclictest0-21swapper/007:17:310
6694992014,3cyclictest0-21swapper/208:07:392
6694992014,3cyclictest0-21swapper/208:07:382
669499190,1cyclictest0-21swapper/212:04:042
669499190,17cyclictest1523-21lxd10:20:432
6689991915,3cyclictest0-21swapper/110:38:351
668999190,2cyclictest3987-21H222:10:211
668599194,1cyclictest0-21swapper/010:16:470
668599192,16cyclictest21724-21smtpd09:27:220
668599192,16cyclictest21724-21smtpd09:27:220
6685991917,1cyclictest26842-21date12:30:000
668599191,16cyclictest7802-21nfsd408:05:190
668599191,16cyclictest7802-21nfsd408:05:190
6694991815,2cyclictest19897-21expr09:25:112
6694991815,2cyclictest19897-21expr09:25:112
6694991814,3cyclictest0-21swapper/211:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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