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2026-03-04 - 12:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Mar 04, 2026 00:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
688299242,4cyclictest0-21swapper/023:00:000
688299242,4cyclictest0-21swapper/023:00:000
688499230,22cyclictest0-21swapper/200:08:162
688299232,13cyclictest20605-21apt-get22:25:000
688399210,3cyclictest0-21swapper/122:59:261
688399210,3cyclictest0-21swapper/122:59:261
688299214,16cyclictest21662-21wc21:30:140
688299210,20cyclictest843-21systemd-network00:39:480
6884992016,3cyclictest0-21swapper/222:32:202
6884992014,1cyclictest0-21swapper/220:45:452
6884992014,1cyclictest0-21swapper/220:45:442
6882992019,1cyclictest101rcuc/023:40:170
6884991916,2cyclictest2185-21nfsd422:45:172
6884991914,4cyclictest20700-21missed_timers20:30:182
6884991914,1cyclictest0-21swapper/222:10:092
6883991917,1cyclictest0-21swapper/120:43:271
688399190,3cyclictest0-21swapper/123:56:201
688399190,17cyclictest399-20systemd-journal23:20:001
688299193,1cyclictest0-21swapper/021:46:120
688499182,15cyclictest998-21chrt20:54:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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