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2025-12-15 - 00:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 14, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30280992322,0cyclictest0-21swapper/109:05:351
3028099225,11cyclictest0-21swapper/112:10:551
3028099223,14cyclictest677-21perf12:00:011
3028099220,21cyclictest0-21swapper/108:52:151
3028499210,3cyclictest0-21swapper/207:44:392
3027499210,6cyclictest426-21systemd-udevd07:52:500
3028499203,2cyclictest1856-21systemd-udevd09:30:502
30284992017,2cyclictest3985-21H222:02:192
30284992016,3cyclictest0-21swapper/208:30:442
3028499200,18cyclictest18630-21head10:37:152
30280992016,3cyclictest0-21swapper/107:15:241
3027499202,15cyclictest0-21swapper/007:41:260
3028499190,2cyclictest3989-21H222:02:192
3028499190,16cyclictest3989-21H222:02:192
3028099192,2cyclictest30996-21latency_hist09:05:011
30280991914,2cyclictest3976-21H222:02:191
3028099191,3cyclictest0-21swapper/109:34:421
3028099190,4cyclictest23251-21cpuspeed_turbos10:47:101
3028099190,4cyclictest23251-21cpuspeed_turbos10:47:091
3028099190,18cyclictest3976-21H222:02:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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