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2026-03-19 - 04:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Mar 19, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2453399230,22cyclictest843-21systemd-network20:48:331
2453499220,21cyclictest843-21systemd-network22:19:482
24533992210,11cyclictest0-21swapper/100:10:121
2453399220,18cyclictest0-21swapper/100:15:141
2453499216,14cyclictest28-21ksoftirqd/221:39:402
2453499210,1cyclictest28-21ksoftirqd/221:09:312
2453299212,2cyclictest27177-21tr22:05:130
2453299210,20cyclictest870-21systemd-logind22:58:510
2453499200,19cyclictest843-21systemd-network19:56:282
2453499200,19cyclictest0-21swapper/222:12:322
24534991918,1cyclictest28-21ksoftirqd/219:25:552
24534991914,4cyclictest0-21swapper/219:42:422
24534991914,4cyclictest0-21swapper/219:42:422
2453499190,3cyclictest13218-21proc_pri00:30:182
2453499190,16cyclictest30997-21nfsd400:05:162
2453399192,1cyclictest0-21swapper/120:04:361
2453399192,16cyclictest26452-21nfsd419:10:161
2453399192,11cyclictest0-21swapper/121:51:331
2453399192,11cyclictest0-21swapper/121:51:331
24533991916,2cyclictest28580-21expr21:10:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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