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2026-04-02 - 20:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 02, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1653099230,20cyclictest0-21swapper/010:10:180
1653299224,17cyclictest0-21swapper/208:46:402
1653299224,17cyclictest0-21swapper/208:46:402
1653099220,18cyclictest0-21swapper/009:24:350
1653199212,18cyclictest0-21swapper/108:30:171
1653099215,9cyclictest0-21swapper/007:36:140
16530992113,4cyclictest0-21swapper/012:26:390
16532992016,3cyclictest0-21swapper/207:26:392
1653199200,3cyclictest0-21swapper/108:44:231
16532991916,2cyclictest1901-21cut11:50:012
16532991915,1cyclictest0-21swapper/208:03:162
16531991914,2cyclictest0-21swapper/109:13:571
16531991914,2cyclictest0-21swapper/109:13:561
16531991914,1cyclictest0-21swapper/109:00:131
1653099190,18cyclictest870-21systemd-logind10:46:510
1653099190,18cyclictest870-21systemd-logind10:28:520
1653099190,18cyclictest870-21systemd-logind09:06:520
1653299182,1cyclictest0-21swapper/208:37:192
1653299182,15cyclictest0-21swapper/207:17:102
16532991816,1cyclictest28-21ksoftirqd/211:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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