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2026-09-20 - 15:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Sep 20, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
451992610,1cyclictest0-21swapper/221:35:142
451992523,1cyclictest0-21swapper/221:35:002
44699240,23cyclictest31823-21perf20:05:011
451992220,1cyclictest0-21swapper/220:10:172
44699220,18cyclictest0-21swapper/122:15:121
44299220,21cyclictest870-21systemd-logind19:36:520
44699214,16cyclictest19290-21perf20:40:001
44699214,16cyclictest0-21swapper/121:39:231
446992114,3cyclictest0-21swapper/120:55:161
44299214,1cyclictest3991-21H222:10:210
451992017,2cyclictest7485-21switchtime20:15:212
45199200,5cyclictest399-20systemd-journal20:24:552
446992017,2cyclictest15524-21missed_timers22:25:171
44699200,5cyclictest0-21swapper/119:45:181
44699200,18cyclictest0-21swapper/121:41:241
45199192,2cyclictest12399-21cpuspeed_turbos00:15:142
451991917,1cyclictest28438-21cat19:55:232
451991917,1cyclictest0-21swapper/223:45:152
451991917,1cyclictest0-21swapper/221:00:162
451991911,4cyclictest0-21swapper/222:14:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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