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2025-12-12 - 02:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Dec 11, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2272399350,34cyclictest0-21swapper/112:30:131
2272799214,2cyclictest21128-21bounce11:49:542
22722992121,0cyclictest0-21swapper/008:30:160
22727992018,2cyclictest0-21swapper/209:22:202
2272399204,15cyclictest4534-21H212:26:331
2272399200,19cyclictest0-21swapper/112:11:581
2272399200,17cyclictest0-21swapper/111:15:361
2272399200,15cyclictest0-21swapper/112:00:171
2272399200,15cyclictest0-21swapper/112:00:161
2272799192,11cyclictest19637-21gpgv08:00:012
22727991917,1cyclictest0-21swapper/207:30:012
22727991916,2cyclictest29494-21expr11:05:182
22727991914,3cyclictest4523-21H212:26:332
2272799190,3cyclictest2628-21cron10:20:012
2272799190,2cyclictest4530-21H212:26:332
2272799190,2cyclictest4530-21H212:26:332
2272799190,16cyclictest4581-21H212:26:332
2272799190,16cyclictest4534-21H212:26:332
2272799190,16cyclictest4532-21H212:26:332
2272799190,16cyclictest4532-21H212:26:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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