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2026-01-10 - 07:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 10, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
597099220,4cyclictest0-21swapper/219:33:492
596199223,16cyclictest30816-21wc22:45:130
597099213,17cyclictest13433-21sed22:15:012
597099210,3cyclictest0-21swapper/219:21:472
5970992016,3cyclictest0-21swapper/220:01:352
596599209,0cyclictest0-21swapper/122:07:081
596599200,17cyclictest0-21swapper/122:55:061
596199203,2cyclictest14425-21idleruntime20:20:150
5961992016,3cyclictest0-21swapper/019:32:180
5961992015,3cyclictest7505-21dpkg22:05:010
5970991917,1cyclictest0-21swapper/221:30:002
597099190,16cyclictest10105-21latency_hist20:15:012
596599190,17cyclictest16858-21anvil21:25:091
596199192,1cyclictest0-21swapper/022:11:310
596199192,16cyclictest24151-21processes00:25:180
596199192,16cyclictest0-21swapper/023:26:130
5961991913,5cyclictest0-21swapper/021:52:170
597099182,1cyclictest296332sleep220:48:092
597099182,15cyclictest105732sleep200:04:072
5970991816,1cyclictest17555-21expr00:15:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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