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2025-12-05 - 06:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Dec 05, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1330899263,19cyclictest0-21swapper/221:05:102
1330899263,19cyclictest0-21swapper/221:05:102
1330899260,8cyclictest0-21swapper/219:18:092
1330899253,21cyclictest0-21swapper/220:45:482
1330699251,19cyclictest7686-21latency_hist20:55:000
13308992417,6cyclictest0-21swapper/219:34:512
1330899241,22cyclictest0-21swapper/223:17:492
1330899240,23cyclictest17817-21cat22:10:012
1330899232,20cyclictest970-21dbus-daemon19:10:222
1330899231,21cyclictest2907-21cat00:35:012
1330899231,21cyclictest14207-21ntpq23:55:222
1330899230,7cyclictest5672-21mailstats19:50:212
1330899230,22cyclictest2575-21awk23:35:192
1330899223,4cyclictest0-21swapper/223:40:402
1330899223,4cyclictest0-21swapper/223:40:402
1330899222,5cyclictest23204-21chrt21:20:202
1330899222,19cyclictest25652-21cpuspeed_turbos23:20:142
1330899220,21cyclictest9560-21missed_timers22:50:192
1330899220,21cyclictest6146-21cut21:50:002
1330899220,21cyclictest52242chrt20:50:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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