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2026-01-15 - 21:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Jan 15, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2620799263,5cyclictest0-21swapper/010:55:000
2620799252,22cyclictest0-21swapper/009:40:250
2620799240,2cyclictest1177-21apache_accesses11:10:120
2620899230,22cyclictest843-21systemd-network12:03:511
2620799232,20cyclictest19655-21ls09:45:200
2620799230,2cyclictest4585-21cat11:15:120
2620799230,2cyclictest12183-21cpu09:35:100
2620799230,1cyclictest0-21swapper/007:31:000
2620799222,1cyclictest228152sleep011:45:470
26207992216,5cyclictest0-21swapper/010:15:190
26207992214,7cyclictest29997-21ls07:15:150
26207992214,7cyclictest25566-21vmstat09:55:220
26207992214,7cyclictest10556-21perf10:30:000
2620799220,3cyclictest28157-21cat07:10:210
2620799220,2cyclictest8153-21cut10:25:020
2620799220,2cyclictest31721-21ls09:10:190
2620799220,2cyclictest3063-21anvil09:20:160
2620799220,2cyclictest16607-21ntp_states11:35:160
2620799220,2cyclictest0-21swapper/008:27:140
2620799220,21cyclictest2959-21cpu07:25:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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