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2025-12-29 - 17:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Dec 29, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10119992313,5cyclictest0-21swapper/207:20:152
10115992219,2cyclictest19343-21latency_hist09:20:011
10115992219,2cyclictest19343-21latency_hist09:20:001
10110992221,0cyclictest0-21swapper/010:17:540
1011099220,21cyclictest0-21swapper/010:25:140
1011999200,19cyclictest0-21swapper/209:17:242
1011999200,19cyclictest0-21swapper/209:17:232
10110992013,3cyclictest0-21swapper/007:23:020
10115991914,3cyclictest0-21swapper/109:32:381
1011599190,18cyclictest0-21swapper/112:35:001
1011099193,2cyclictest2850-21gmain11:47:200
1011099190,2cyclictest12585-21cat08:10:010
1011099190,18cyclictest843-21systemd-network09:58:330
1011099190,16cyclictest3976-21H222:10:210
1011999182,1cyclictest105812chrt09:03:112
1011999181,16cyclictest0-21swapper/211:54:472
1011999181,16cyclictest0-21swapper/211:54:462
1011999180,2cyclictest3976-21H222:10:212
1011999180,17cyclictest2995-21awk12:40:002
10115991815,2cyclictest24377-21chrt09:28:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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