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2026-02-11 - 15:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 11, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30111992616,0cyclictest0-21swapper/110:44:311
3011699236,15cyclictest0-21swapper/211:46:342
3011199220,21cyclictest843-21systemd-network07:22:341
3010799223,13cyclictest4764-21sed11:10:000
30116992114,3cyclictest0-21swapper/209:27:402
3011199214,6cyclictest0-21swapper/112:06:351
3011699203,16cyclictest0-21swapper/208:27:172
3011699200,19cyclictest843-21systemd-network10:35:092
3010799203,16cyclictest2069-21systemd-udevd12:02:520
30107992015,3cyclictest1197-21grep08:10:190
3011699193,15cyclictest27451-21sendmail09:00:012
30116991917,1cyclictest23238-21nfsd411:40:172
3011199192,16cyclictest16811-21grep09:35:181
3011199190,2cyclictest8145-21cron08:25:011
3011199190,18cyclictest426-21systemd-udevd10:36:511
30107991914,5cyclictest0-21swapper/012:35:010
3010799191,3cyclictest0-21swapper/012:10:590
3011699182,15cyclictest0-21swapper/212:01:322
3011699181,2cyclictest0-21swapper/207:40:152
3011699181,16cyclictest3983-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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