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2026-02-25 - 13:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 25, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2833099213,3cyclictest0-21swapper/223:58:422
2833099212,18cyclictest28-21ksoftirqd/222:46:102
2832699217,13cyclictest0-21swapper/122:09:111
2832499210,20cyclictest843-21systemd-network20:47:040
2832499210,17cyclictest0-21swapper/022:17:560
2833099203,2cyclictest24230-21cron20:55:012
28330992016,3cyclictest3076-21iscsid21:45:162
28330992016,3cyclictest3058-21rs:main2
2832699206,13cyclictest0-21swapper/123:09:171
2832699204,15cyclictest0-21swapper/123:50:241
2832699204,15cyclictest0-21swapper/123:27:091
28326992015,3cyclictest111rcu_preempt19:10:511
2832699200,6cyclictest426-21systemd-udevd22:56:511
2832499202,9cyclictest0-21swapper/019:35:010
2833099192,2cyclictest32338-21switchtime20:10:212
28330991917,1cyclictest0-21swapper/221:15:212
28330991913,5cyclictest426-21systemd-udevd22:36:512
2833099190,18cyclictest0-21swapper/222:33:442
28326991919,0cyclictest0-21swapper/100:15:271
28326991917,1cyclictest201rcuc/121:09:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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