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2026-02-18 - 22:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Feb 18, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4348992512,10cyclictest0-21swapper/108:24:001
4353992312,7cyclictest28-21ksoftirqd/209:15:002
4348992310,13cyclictest0-21swapper/110:45:141
434899230,20cyclictest0-21swapper/108:57:011
434499230,22cyclictest0-21swapper/011:15:170
435399226,15cyclictest28-21ksoftirqd/210:32:582
435399220,20cyclictest870-21systemd-logind10:02:512
434899220,17cyclictest17539-21latency_hist11:20:011
435399210,20cyclictest870-21systemd-logind08:13:522
435399203,11cyclictest10433-21munin-run12:04:592
435399200,19cyclictest426-21systemd-udevd07:32:522
4348992018,1cyclictest0-21swapper/112:10:131
4348992018,1cyclictest0-21swapper/112:10:131
4348992016,3cyclictest0-21swapper/107:47:171
4353991917,1cyclictest0-21swapper/208:05:132
4353991916,2cyclictest552-21nfsd411:45:172
435399190,4cyclictest399-20systemd-journal09:39:012
4348991914,3cyclictest0-21swapper/112:02:591
4348991911,5cyclictest0-21swapper/107:50:131
434899190,3cyclictest31884-21cpuspeed_turbos11:45:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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