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2026-07-14 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jul 14, 2026 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2157992927,1cyclictest0-21swapper/008:30:180
215899258,2cyclictest3981-21H222:10:211
215899250,24cyclictest0-21swapper/111:54:101
215899250,24cyclictest0-21swapper/109:30:061
215899240,0cyclictest0-21swapper/112:13:451
215799240,22cyclictest0-21swapper/010:41:500
215899230,8cyclictest0-21swapper/109:15:151
215899230,5cyclictest0-21swapper/112:26:431
215899230,5cyclictest0-21swapper/109:05:011
215899230,22cyclictest0-21swapper/107:57:411
215899220,20cyclictest870-21systemd-logind09:48:511
215799220,4cyclictest0-21swapper/012:05:000
215799220,21cyclictest0-21swapper/012:34:200
215799220,18cyclictest0-21swapper/010:31:560
2162992118,2cyclictest17946-21sh10:30:012
215899214,3cyclictest0-21swapper/110:37:591
215899214,2cyclictest3976-21H222:10:211
215899211,17cyclictest4023-21PluginScanner10:07:061
215899210,3cyclictest0-21swapper/112:34:211
2157992121,0cyclictest0-21swapper/012:05:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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