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2026-02-20 - 13:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Feb 20, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21425992417,6cyclictest8524-21cat23:35:000
2142599221,14cyclictest0-21swapper/023:37:230
2142799210,18cyclictest0-21swapper/223:50:142
21427992016,3cyclictest0-21swapper/222:57:122
2142799200,5cyclictest399-20systemd-journal19:17:002
2142799200,18cyclictest9149-21nfsd420:40:202
21426992014,3cyclictest0-21swapper/121:47:511
21425992017,2cyclictest15185-21timerwakeupswit22:45:200
2142799193,1cyclictest11517-21pluginstate00:35:192
2142799192,2cyclictest18271-21missed_timers21:55:162
21427991913,3cyclictest0-21swapper/221:06:592
21426991917,1cyclictest0-21swapper/121:20:131
2142699190,4cyclictest399-20systemd-journal22:50:011
21427991815,2cyclictest28391-21nfsd421:15:192
21427991814,3cyclictest0-21swapper/220:10:062
21427991814,2cyclictest31169-21cpuspeed_turbos22:20:142
2142799181,2cyclictest14301-21latency22:45:172
21427991812,1cyclictest0-21swapper/220:10:012
2142799180,3cyclictest24719-21sshd00:02:062
2142799180,17cyclictest23247-21expr22:05:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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