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2026-02-22 - 09:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 22, 2026 00:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27642993415,13cyclictest3986-21H222:10:210
2764299261,17cyclictest0-21swapper/021:55:110
2764399230,22cyclictest32262-21ntpq23:05:181
2764399220,21cyclictest9238-21sed21:25:231
2764399220,21cyclictest5382-21expr23:15:131
2764399220,21cyclictest5382-21expr23:15:121
2764399220,21cyclictest455-21plymouthd20:25:101
2764399220,21cyclictest32365-21cut21:10:191
2764399220,21cyclictest25687-21ls23:50:171
2764399220,21cyclictest20081-21awk21:45:181
2764399220,21cyclictest13955-21ps00:25:221
2764399220,21cyclictest0-21swapper/123:40:171
2764399220,21cyclictest0-21swapper/122:45:161
2764399220,21cyclictest0-21swapper/121:21:051
2764399220,21cyclictest0-21swapper/119:20:211
2764299227,14cyclictest0-21swapper/023:10:140
27642992218,3cyclictest11027-21fschecks_count23:25:140
27643992114,6cyclictest31268-21idleruntime00:00:161
27643992114,6cyclictest18559-21cat21:45:011
2764399211,19cyclictest31186-21cut20:10:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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