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2026-05-03 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun May 03, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1531999293,15cyclictest0-21swapper/108:34:301
15319992827,0cyclictest0-21swapper/108:50:211
15320992218,2cyclictest20963-21sshd12:00:282
15319992213,0cyclictest0-21swapper/107:33:371
1531999220,18cyclictest0-21swapper/108:08:591
1532099212,13cyclictest8636-21mandb08:47:012
1531899203,16cyclictest25754-21cut09:20:010
1532099192,2cyclictest28823-21cut09:25:152
15320991915,3cyclictest25188-21nfsd408:20:182
1532099190,3cyclictest0-21swapper/211:25:382
1532099190,18cyclictest0-21swapper/208:14:202
1532099190,17cyclictest2350-21nvmesmart_nvme012:25:192
1531999190,1cyclictest0-21swapper/109:10:201
1531999190,18cyclictest843-21systemd-network08:14:211
1531899193,15cyclictest0-21swapper/011:34:090
1531899192,16cyclictest14744-21nfsd411:50:180
1531899190,1cyclictest0-21swapper/009:45:010
1531899190,18cyclictest0-21swapper/010:55:010
15320991816,1cyclictest0-21swapper/212:15:182
1532099181,2cyclictest22123-21chrt10:10:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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