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2026-09-17 - 13:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Sep 17, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10980992919,0cyclictest0-21swapper/223:20:142
10971992510,9cyclictest9092-21perf20:05:010
10975992313,0cyclictest0-21swapper/121:33:071
1097599230,5cyclictest0-21swapper/119:31:121
1097199232,4cyclictest0-21swapper/020:10:010
1097199230,5cyclictest0-21swapper/023:40:190
1098099226,13cyclictest0-21swapper/220:49:142
10980992214,4cyclictest0-21swapper/219:52:512
1097599220,18cyclictest0-21swapper/119:50:011
1097199220,5cyclictest0-21swapper/021:24:280
1098099210,3cyclictest0-21swapper/222:15:072
1098099210,16cyclictest1372-21latency_hist00:35:012
1098099204,15cyclictest0-21swapper/219:40:172
1098099202,17cyclictest0-21swapper/219:19:352
1098099202,17cyclictest0-21swapper/219:19:342
1098099200,3cyclictest0-21swapper/200:25:202
1098099200,17cyclictest20058-21perf00:10:002
10975992017,2cyclictest3987-21H222:10:211
1097599201,4cyclictest25813-21if_lxdbr019:35:161
1097599200,19cyclictest399-20systemd-journal21:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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