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2025-09-18 - 09:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Sep 18, 2025 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4426992515,1cyclictest0-21swapper/219:33:402
442499257,17cyclictest454-21plymouthd21:08:530
442699220,18cyclictest0-21swapper/220:33:342
4426992114,3cyclictest0-21swapper/220:49:202
4426992012,7cyclictest4538-21H212:26:332
442599200,18cyclictest4523-21H212:26:331
4424992010,5cyclictest20915-21nfsd421:35:200
442699192,16cyclictest29532-21needreboot20:50:212
4426991915,3cyclictest4581-21H212:26:332
442699190,18cyclictest823-21systemd-network22:05:022
442699190,17cyclictest4536-21H212:26:332
442699190,17cyclictest0-21swapper/222:35:192
442699190,16cyclictest4534-21H212:26:332
4425991916,2cyclictest4593-21H212:26:331
442599190,16cyclictest4581-21H212:26:331
442599190,16cyclictest4536-21H212:26:331
442499193,1cyclictest7698-21cat21:10:180
442499192,11cyclictest2355-21perf00:00:000
442499190,2cyclictest4536-21H212:26:330
442499190,16cyclictest4534-21H212:26:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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