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2025-12-31 - 02:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Dec 30, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1990099225,8cyclictest0-21swapper/211:15:142
1989599212,16cyclictest25684-21needreboot09:10:181
1989599210,3cyclictest0-21swapper/111:53:241
1989099210,3cyclictest0-21swapper/009:18:180
1989599205,15cyclictest21-21ksoftirqd/110:00:141
19890992016,1cyclictest0-21swapper/009:05:160
1990099192,11cyclictest12791-21latency_hist10:45:012
19900991917,1cyclictest0-21swapper/211:53:592
19900991916,1cyclictest0-21swapper/208:28:542
19895991915,3cyclictest0-21swapper/108:58:001
1989099192,2cyclictest17672-21smartctl10:50:190
1990099182,2cyclictest3289-21chrt09:30:092
1990099182,15cyclictest2573-21nfsd411:20:182
1990099182,15cyclictest0-21swapper/207:49:462
19900991815,1cyclictest0-21swapper/211:08:322
1990099181,2cyclictest13183-21timerandwakeup07:50:212
1990099181,16cyclictest0-21swapper/211:58:132
1990099180,16cyclictest3979-21H222:10:212
19895991818,0cyclictest0-21swapper/109:30:191
19895991814,3cyclictest0-21swapper/108:41:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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