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2026-02-22 - 22:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 22, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10335992518,6cyclictest0-21swapper/008:10:010
10335992414,5cyclictest0-21swapper/012:13:020
1033599230,17cyclictest31459-21latency_hist09:40:010
10336992214,4cyclictest0-21swapper/107:30:001
1033599222,16cyclictest30460-21cut12:30:000
10335992214,7cyclictest17476-21grep10:10:180
1033599221,2cyclictest18771-21grep08:20:140
1033599220,2cyclictest6029-21if_lxdbr009:50:180
1033599220,2cyclictest31664-21ls07:45:150
1033599220,21cyclictest20268-21grep09:20:130
1033599220,21cyclictest0-21swapper/012:30:290
1033599220,1cyclictest0-21swapper/011:59:290
1033599220,1cyclictest0-21swapper/008:35:160
1033599220,16cyclictest4623-21sed11:40:220
1033599220,15cyclictest0-21swapper/009:34:380
10335992114,6cyclictest3876-21ls10:45:140
10335992114,6cyclictest13583-21expr08:10:140
10335992113,7cyclictest24242-21chrt12:18:310
10335992112,5cyclictest14707-21expr11:05:130
1033599210,3cyclictest4035-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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