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2026-04-09 - 03:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Apr 09, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22312992417,6cyclictest25902-21ntp_kernel_pll_20:10:182
22303992424,0cyclictest0-21swapper/023:40:140
2231299231,17cyclictest0-21swapper/222:20:002
2231299230,22cyclictest0-21swapper/220:05:212
2231299230,17cyclictest25753-21fschecks_count22:05:142
2231299230,16cyclictest6111-21cat23:25:132
2231299222,1cyclictest246252chrt19:11:382
2231299222,19cyclictest0-21swapper/222:25:242
22312992215,6cyclictest507-21fschecks_time23:15:132
2231299220,2cyclictest7042-21perf00:25:012
2231299220,2cyclictest32017-21expr19:25:182
2231299220,2cyclictest30007-21apache_volume20:20:112
2231299220,21cyclictest29557-21tr00:05:172
2231299220,21cyclictest11050-21apache_volume21:40:122
2231299220,21cyclictest0-21swapper/223:40:162
2231299220,21cyclictest0-21swapper/221:30:182
2231299220,1cyclictest0-21swapper/222:35:152
2231299220,16cyclictest8132-21fschecks_time00:25:152
2231299220,15cyclictest0-21swapper/219:40:132
22308992213,0cyclictest0-21swapper/121:10:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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