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2026-02-06 - 15:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Feb 06, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27624993735,1cyclictest26552-21lspci11:45:562
2762499230,18cyclictest0-21swapper/207:55:142
2761299212,18cyclictest0-21swapper/007:10:130
2762499199,5cyclictest0-21swapper/210:37:222
2762499199,5cyclictest0-21swapper/210:37:212
27624991915,3cyclictest17224-21apt-config12:25:002
2762499191,3cyclictest29720-21python310:05:012
2762499190,5cyclictest0-21swapper/208:21:472
2762499190,4cyclictest7748-21ntp_kernel_err11:15:162
2762499190,18cyclictest26351-21fschecks_count09:00:152
2762499190,18cyclictest0-21swapper/207:35:022
27615991917,1cyclictest0-21swapper/111:15:181
2761599190,15cyclictest0-21swapper/108:25:141
2761299193,15cyclictest18339-21awk08:45:150
2761299192,16cyclictest6151-21munin-run11:15:010
2761299192,11cyclictest12342-21munin-run10:30:010
2762499183,11cyclictest7289-21munin-run09:25:002
27624991814,3cyclictest993-21dbus-daemon09:38:592
2762499181,16cyclictest23273-21/usr/sbin/munin12:35:192
2762499180,17cyclictest17875-21python307:50:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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