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2026-01-20 - 21:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jan 20, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48399260,22cyclictest843-21systemd-network08:15:371
48799251,23cyclictest9421-21munin-run07:25:012
47699250,1cyclictest9-21ksoftirqd/009:55:150
48399243,1cyclictest0-21swapper/109:58:271
48399241,1cyclictest0-21swapper/109:42:401
48399240,16cyclictest0-21swapper/107:53:091
48399230,18cyclictest880-21rs:main1
48399230,18cyclictest0-21swapper/107:25:011
48799225,16cyclictest3987-21H222:10:212
48799220,21cyclictest843-21systemd-network08:18:122
483992214,7cyclictest0-21swapper/110:12:441
483992214,3cyclictest3976-21H222:10:211
48399220,17cyclictest843-21systemd-network08:45:321
476992214,4cyclictest0-21swapper/008:20:150
483992116,3cyclictest0-21swapper/107:39:061
48399210,2cyclictest4099-21H222:10:211
48399210,17cyclictest3983-21H222:10:211
48399210,16cyclictest4912-21cut07:15:161
487992014,5cyclictest0-21swapper/212:00:172
48399206,13cyclictest0-21swapper/111:31:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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