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2026-07-05 - 15:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jul 05, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3071599225,11cyclictest0-21swapper/207:22:162
3071599212,12cyclictest3978-21H222:10:212
30715992117,3cyclictest3987-21H222:10:212
30715992114,3cyclictest0-21swapper/208:23:282
30715992112,5cyclictest0-21swapper/208:55:172
30715992018,1cyclictest0-21swapper/212:22:312
3071599200,17cyclictest3989-21H222:10:212
30710992018,1cyclictest13033-21ntp_kernel_pll_11:20:180
30710992015,4cyclictest13866-21fschecks_time12:20:140
30710992014,5cyclictest0-21swapper/009:20:170
30715991917,1cyclictest28-21ksoftirqd/207:34:522
30715991917,1cyclictest0-21swapper/207:40:192
3071599190,2cyclictest3979-21H222:10:212
3071599190,16cyclictest4035-21H222:10:212
3071599190,16cyclictest3991-21H222:10:212
3071599190,16cyclictest3985-21H222:10:212
3071599190,16cyclictest3981-21H222:10:212
30711991917,1cyclictest0-21swapper/108:52:481
3071199190,17cyclictest22620-21nvmesmart_nvme010:40:201
3071199190,16cyclictest3991-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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