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2026-01-18 - 07:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jan 18, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
555999270,2cyclictest21101-21grep21:35:131
555999270,2cyclictest21101-21grep21:35:131
556499262,19cyclictest0-21swapper/223:10:122
555999263,5cyclictest0-21swapper/122:29:351
5564992516,5cyclictest0-21swapper/221:38:262
5564992516,5cyclictest0-21swapper/221:38:262
5559992522,2cyclictest31896-21munin-plugin-st23:50:011
555999243,6cyclictest0-21swapper/120:45:311
5559992417,6cyclictest31952-21ntp_offset22:50:181
556499230,9cyclictest5903-21tr22:05:122
556499230,22cyclictest26280-21basename23:40:002
556499230,22cyclictest22471-21ls22:35:122
556499230,22cyclictest18024-21awk22:25:182
556499230,22cyclictest14315-21cstates22:20:132
556499230,20cyclictest0-21swapper/221:34:102
555999230,22cyclictest0-21swapper/120:50:281
555999230,1cyclictest149212chrt20:21:001
555499232,14cyclictest0-21swapper/000:26:430
556499221,20cyclictest14196-21date00:15:002
556499221,20cyclictest0-21swapper/223:45:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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