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2025-12-08 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Dec 08, 2025 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1869992314,5cyclictest0-21swapper/200:03:082
186999230,1cyclictest0-21swapper/223:56:262
186799230,5cyclictest0-21swapper/022:14:040
186799230,5cyclictest0-21swapper/019:16:080
186999222,17cyclictest0-21swapper/222:25:002
1868992119,1cyclictest4581-21H212:26:331
1867992115,5cyclictest0-21swapper/000:25:000
186999204,15cyclictest0-21swapper/221:31:132
186899200,18cyclictest414-20systemd-journal21:03:241
1869991917,1cyclictest0-21swapper/222:02:212
186999190,18cyclictest823-21systemd-network19:34:122
186999190,16cyclictest4530-21H212:26:332
186999190,16cyclictest4528-21H212:26:332
1868991918,1cyclictest21-21ksoftirqd/121:28:581
1868991917,1cyclictest4530-21H212:26:331
1868991915,3cyclictest4523-21H212:26:331
186899191,1cyclictest111rcu_preempt19:55:421
1867991917,1cyclictest0-21swapper/021:13:100
1867991916,2cyclictest13531-21rm00:15:020
1867991914,3cyclictest31131-21grep20:00:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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