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2026-01-21 - 10:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 21, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2145699230,8cyclictest870-21systemd-logind00:08:511
2145699230,22cyclictest870-21systemd-logind22:58:511
2145799210,20cyclictest0-21swapper/220:05:182
21456992120,1cyclictest21-21ksoftirqd/121:00:151
2145699210,20cyclictest201rcuc/100:10:201
2145799209,6cyclictest6326-21munin-run19:40:012
2145799209,6cyclictest6326-21munin-run19:40:002
21457992016,3cyclictest0-21swapper/221:07:572
2145699200,5cyclictest870-21systemd-logind21:48:521
2145699200,19cyclictest870-21systemd-logind19:41:521
2145699200,19cyclictest870-21systemd-logind00:03:511
2145799192,16cyclictest9304-21date22:35:002
21457991916,2cyclictest4683-21nfsd420:30:162
21457991915,3cyclictest14082-21cpuspeed_turbos21:45:122
2145799190,16cyclictest0-21swapper/200:10:022
2145699193,15cyclictest21-21ksoftirqd/121:34:161
21456991918,1cyclictest21-21ksoftirqd/119:56:431
2145699191,1cyclictest111rcu_preempt23:43:271
2145699190,2cyclictest21-21ksoftirqd/121:59:561
2145699190,1cyclictest0-21swapper/122:30:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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