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2026-01-26 - 23:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Jan 26, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3097499220,21cyclictest843-21systemd-network10:56:252
3097299222,17cyclictest0-21swapper/107:28:021
30974992117,3cyclictest1578-21cron09:09:002
30974992013,3cyclictest0-21swapper/209:23:362
30972992016,3cyclictest0-21swapper/111:49:191
3097299200,18cyclictest4035-21H222:10:211
3097199202,1cyclictest0-21swapper/010:54:240
3097199200,17cyclictest0-21swapper/011:15:580
3097499192,16cyclictest4035-21H222:10:212
30974991914,3cyclictest2739-21sort10:09:002
3097499190,2cyclictest3981-21H222:10:212
3097499190,18cyclictest0-21swapper/210:25:132
3097499190,16cyclictest3989-21H222:10:212
30972991917,1cyclictest0-21swapper/110:35:011
30972991915,3cyclictest0-21swapper/110:03:071
30972991915,2cyclictest3991-21H222:10:211
3097299190,2cyclictest3989-21H222:10:211
3097299190,16cyclictest3991-21H222:10:211
3097199197,11cyclictest0-21swapper/010:29:480
30971991917,1cyclictest9-21ksoftirqd/009:05:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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