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2025-12-21 - 15:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Dec 21, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1857599270,1cyclictest0-21swapper/011:55:140
1857799236,16cyclictest25675-21taskset11:10:112
1857799235,16cyclictest30516-21grep08:25:172
1857799234,18cyclictest3987-21H222:10:212
18577992319,3cyclictest21250-21sendmail12:00:002
1857799231,19cyclictest0-21swapper/210:00:592
1857799225,16cyclictest4900-21cat11:30:002
1857799225,16cyclictest4795-21sed08:37:112
1857799225,16cyclictest3704-21expr10:30:152
1857799225,16cyclictest17942-21cat08:05:012
18577992219,2cyclictest28983-21df_inode11:15:152
18577992219,2cyclictest23443-21awk12:00:192
18577992219,2cyclictest11778-21awk07:50:222
18577992218,3cyclictest6764-21http_loadtime08:40:162
18577992218,3cyclictest6258-21missed_timers11:30:192
18577992218,3cyclictest30040-21sshd07:28:202
18577992218,3cyclictest16570-21sshd10:50:592
18577992218,3cyclictest15401-21cut09:55:012
18577992218,3cyclictest11221-21/usr/sbin/munin12:35:192
18576992218,3cyclictest0-21swapper/111:20:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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