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2026-02-02 - 10:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Feb 02, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24274993533,2cyclictest0-21swapper/119:10:151
24274992422,2cyclictest0-21swapper/120:51:321
24274992415,9cyclictest21-21ksoftirqd/123:31:281
2427399240,23cyclictest0-21swapper/019:10:160
2427399231,1cyclictest8552-21kworker/0:020:51:320
24273992219,2cyclictest7017-21if_enp1s021:30:160
2427399220,4cyclictest0-21swapper/022:42:270
24275992113,6cyclictest0-21swapper/222:55:172
2427499214,11cyclictest0-21swapper/121:09:531
2427599206,13cyclictest0-21swapper/200:25:112
24275992017,2cyclictest6485-21cpuspeed_turbos23:30:132
24275992017,2cyclictest28-21ksoftirqd/220:15:002
24275992016,3cyclictest0-21swapper/219:19:022
2427399206,12cyclictest0-21swapper/000:35:120
24273992013,6cyclictest11476-21latency_hist19:45:010
2427599192,1cyclictest11928-21nfsd420:40:182
24275991918,0cyclictest0-21swapper/222:03:562
24275991917,1cyclictest28-21ksoftirqd/221:07:232
24275991915,3cyclictest0-21swapper/223:47:572
24274991916,2cyclictest22493-21nfsd423:00:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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