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2025-11-24 - 04:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Nov 24, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1014299330,33cyclictest0-21swapper/019:20:170
1014299210,20cyclictest0-21swapper/021:25:050
10151992014,4cyclictest2049-21systemd-journal23:00:502
1014699200,17cyclictest0-21swapper/120:40:141
10151991917,1cyclictest0-21swapper/220:47:332
10151991916,2cyclictest4530-21H212:26:332
1015199190,2cyclictest4526-21H212:26:332
1015199190,2cyclictest21618-21nfsd423:15:172
1015199190,16cyclictest4538-21H212:26:332
1014699193,15cyclictest0-21swapper/121:23:531
10146991915,3cyclictest4523-21H212:26:331
10146991914,2cyclictest4532-21H212:26:331
1014699190,2cyclictest4593-21H212:26:331
1014699190,16cyclictest4530-21H212:26:331
1014299192,16cyclictest4526-21H212:26:330
10142991916,2cyclictest4532-21H212:26:330
1014299191,17cyclictest2410-21nfsd421:45:180
1014299190,18cyclictest0-21swapper/020:34:180
1015199182,15cyclictest4532-21H212:26:332
1015199182,15cyclictest4532-21H212:26:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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