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2026-03-26 - 05:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Mar 26, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2998699250,4cyclictest0-21swapper/000:05:010
29990992413,10cyclictest0-21swapper/123:25:001
2998699221,20cyclictest9-21ksoftirqd/022:24:310
2999599210,20cyclictest843-21systemd-network23:08:432
29990992117,3cyclictest0-21swapper/100:34:261
29986992117,3cyclictest0-21swapper/019:56:180
2999599200,17cyclictest0-21swapper/219:56:202
2999099203,11cyclictest32274-21munin-run21:10:001
2999099200,5cyclictest0-21swapper/120:45:031
2999099200,18cyclictest0-21swapper/120:09:241
2998699203,16cyclictest10839-21cpuspeed_turbos22:25:120
29986992017,2cyclictest6903-21wc23:15:120
29986992017,2cyclictest21290-21ls21:45:160
29986992016,3cyclictest375-21plymouth22:05:200
29986992016,3cyclictest10887-21dpkg00:20:000
2999599192,16cyclictest0-21swapper/223:43:492
2999599190,17cyclictest0-21swapper/220:21:592
29990991917,1cyclictest6982-21cat22:15:211
2999099191,3cyclictest0-21swapper/122:00:131
2998699192,2cyclictest22595-21sed20:50:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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