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2025-12-26 - 02:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Thu Dec 25, 2025 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3190399263,22cyclictest0-21swapper/012:09:010
3190399240,2cyclictest17200-21grep07:40:120
3190899232,17cyclictest0-21swapper/107:29:351
3190399230,2cyclictest4229-21latency_hist08:15:020
3190399230,2cyclictest24829-21perf11:45:000
3190399230,2cyclictest21941-21nfsd412:35:170
3190399230,21cyclictest10779-21postgres09:21:210
3190399230,16cyclictest8286-21grep12:10:170
3190899220,21cyclictest0-21swapper/111:35:161
3190399223,18cyclictest0-21swapper/011:30:000
3190399221,4cyclictest0-21swapper/009:40:000
31903992213,8cyclictest2007-21systemd-journal09:15:510
3190399221,2cyclictest30295-21latency_hist11:55:000
3190399220,2cyclictest5623-21latency_hist07:20:020
3190399220,2cyclictest26751-21smartctl07:55:160
3190399220,2cyclictest21747-21expr08:45:140
3190399220,1cyclictest10938-21latency08:25:160
3190399220,1cyclictest0-21swapper/012:30:190
3190399220,1cyclictest0-21swapper/010:00:140
3190399220,1cyclictest0-21swapper/008:04:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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