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2025-11-25 - 06:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Nov 25, 2025 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1207299258,16cyclictest3612-21perf20:50:012
12070992017,2cyclictest19649-21latency_hist00:10:000
12070992014,3cyclictest0-21swapper/022:55:530
1207299192,16cyclictest0-21swapper/220:34:582
12072991917,1cyclictest4244-21expr20:50:142
12072991917,1cyclictest0-21swapper/221:05:182
12072991916,2cyclictest23546-21cpuspeed_turbos21:25:142
12072991916,2cyclictest10624-21timerandwakeup23:50:212
1207299190,2cyclictest4530-21H212:26:332
1207299190,16cyclictest4593-21H212:26:332
1207299190,16cyclictest4534-21H212:26:332
1207199190,2cyclictest4532-21H212:26:331
1207199190,2cyclictest4528-21H212:26:331
1207199190,16cyclictest4532-21H212:26:331
1207199190,16cyclictest4526-21H212:26:331
12070991917,1cyclictest0-21swapper/023:57:520
12070991913,5cyclictest0-21swapper/000:35:000
1207099191,16cyclictest27480-21nfsd421:30:200
1207099190,2cyclictest4538-21H212:26:330
1207099190,16cyclictest4536-21H212:26:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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