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2026-03-24 - 16:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Mar 24, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1580199258,16cyclictest18321-21perf12:00:000
1580299230,19cyclictest0-21swapper/108:34:531
1580199220,4cyclictest0-21swapper/008:26:280
1580399215,15cyclictest0-21swapper/209:55:332
1580399210,18cyclictest0-21swapper/208:08:442
1580199210,3cyclictest0-21swapper/009:21:060
1580199210,3cyclictest0-21swapper/009:21:060
1580199210,19cyclictest0-21swapper/011:20:010
15803992018,1cyclictest28-21ksoftirqd/207:20:442
1580399201,18cyclictest3986-21H222:10:212
1580399201,18cyclictest3986-21H222:10:212
1580399201,17cyclictest30858-21fschecks_count07:35:142
15802992013,3cyclictest0-21swapper/112:06:201
1580199203,16cyclictest0-21swapper/010:05:180
1580199200,3cyclictest1829-21systemd-journal10:38:590
1580399192,1cyclictest0-21swapper/211:49:562
1580399192,16cyclictest11953-21smtpd07:58:122
1580399191,2cyclictest3851-21latency_hist07:45:012
1580399190,18cyclictest15765-21nfsd410:55:192
1580299190,16cyclictest12283-21cat08:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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