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2026-08-04 - 23:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Aug 04, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32650993430,1cyclictest0-21swapper/008:25:000
3265099230,22cyclictest17234-21python307:40:010
3265599220,18cyclictest0-21swapper/112:33:551
3265099220,4cyclictest0-21swapper/009:50:080
3265099220,21cyclictest0-21swapper/011:31:070
32659992119,1cyclictest1100-21snmpd10:25:122
32659992014,3cyclictest0-21swapper/210:49:042
3265999201,18cyclictest26157-21nfsd408:50:192
3265099200,17cyclictest0-21swapper/008:09:560
3265999192,15cyclictest0-21swapper/210:44:492
32659991916,2cyclictest3976-21H222:10:212
32659991914,3cyclictest0-21swapper/209:26:472
3265999191,17cyclictest7763-21fschecks_time12:05:152
3265999190,4cyclictest24560-21perf11:39:592
3265999190,16cyclictest3991-21H222:10:212
3265599194,1cyclictest0-21swapper/108:20:171
32655991916,2cyclictest24298-21tr09:45:131
3265599190,2cyclictest3979-21H222:10:211
3265099193,15cyclictest9-21ksoftirqd/009:38:280
3265099193,15cyclictest9-21ksoftirqd/009:38:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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