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2026-04-13 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 13, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7524993323,10cyclictest0-21swapper/112:38:121
7525992515,10cyclictest0-21swapper/212:38:122
752499223,5cyclictest21-21ksoftirqd/110:24:071
752499210,20cyclictest843-21systemd-network09:11:271
752399214,16cyclictest7288-21grep10:55:230
752399214,16cyclictest27127-21grep09:40:000
7523992116,4cyclictest24596-21fschecks_time10:30:170
752399210,20cyclictest0-21swapper/008:34:340
7525992020,0cyclictest0-21swapper/208:40:012
7525992016,1cyclictest0-21swapper/208:30:202
752499200,2cyclictest32573-21iwlist08:50:171
752399204,2cyclictest2470-21ntpq11:45:190
752399203,2cyclictest32167-21expr08:50:160
752399203,2cyclictest23258-21grep11:25:170
752399203,2cyclictest23167-21python310:30:000
752399203,2cyclictest23167-21python310:30:000
752399203,16cyclictest9387-21awk07:10:200
752399203,16cyclictest30294-21sed11:40:000
752399202,17cyclictest0-21swapper/009:50:200
7523992017,2cyclictest4574-21run-parts10:50:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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