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2026-01-25 - 10:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Jan 25, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1013799263,22cyclictest0-21swapper/219:13:102
1013799263,22cyclictest0-21swapper/219:13:102
1013799240,23cyclictest24612-21cat19:35:012
1013599242,18cyclictest0-21swapper/022:55:010
1013799230,22cyclictest7053-21ls22:50:172
1013799230,22cyclictest399-20systemd-journal00:16:092
1013799230,22cyclictest21332-21cut22:20:012
1013799230,22cyclictest20764-21master20:22:222
1013799220,7cyclictest25758-21processes00:20:202
1013799220,21cyclictest7262-21date23:50:012
1013799220,21cyclictest30039-21expr00:30:132
1013799220,21cyclictest28235-21sed23:29:592
1013799220,21cyclictest20783-21sed21:20:152
1013799220,21cyclictest18193-21sed00:09:012
1013799220,21cyclictest17613-21nfsd419:20:182
1013799220,21cyclictest17324-21nvmesmart_nvme020:15:202
1013799220,21cyclictest13094-21swap23:00:202
1013799220,21cyclictest11303-21munin-run23:00:002
1013799220,21cyclictest0-21swapper/222:40:152
1013799220,21cyclictest0-21swapper/221:35:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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