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2026-03-01 - 06:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sun Mar 01, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3245899236,11cyclictest0-21swapper/022:14:420
3245899230,8cyclictest0-21swapper/020:25:420
3246799224,13cyclictest4136-21sort23:05:002
32467992218,3cyclictest0-21swapper/220:45:382
3246799203,16cyclictest22750-21expr23:35:182
3246799202,2cyclictest2094-21perf22:05:012
32467992019,1cyclictest0-21swapper/222:55:132
32467992016,3cyclictest0-21swapper/222:15:142
32467992016,3cyclictest0-21swapper/221:25:422
3246799193,15cyclictest19029-21gpgv20:15:012
3246799192,2cyclictest0-21swapper/220:30:182
3246799192,16cyclictest20282-21expr22:35:142
3246799192,16cyclictest0-21swapper/200:14:492
3246799192,15cyclictest0-21swapper/220:59:152
32467991917,1cyclictest0-21swapper/221:11:172
32467991917,1cyclictest0-21swapper/200:05:132
32467991916,2cyclictest7736-21ls21:15:132
32467991916,2cyclictest20007-21cut00:30:002
32467991916,2cyclictest1449-21if_lxdbr021:00:172
32467991915,3cyclictest0-21swapper/221:40:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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