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2026-04-13 - 09:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Apr 13, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2325899230,5cyclictest0-21swapper/223:44:022
2324599221,4cyclictest0-21swapper/021:55:010
23258992118,2cyclictest6193-21nfsd423:20:182
2325899210,5cyclictest0-21swapper/200:10:162
2324599210,17cyclictest13912-21nvmesmart_nvme021:40:190
2324599204,15cyclictest0-21swapper/022:39:280
23258991917,1cyclictest0-21swapper/220:56:392
23258991917,1cyclictest0-21swapper/220:30:192
23258991917,1cyclictest0-21swapper/219:20:212
2325199193,15cyclictest28204-21nfsd400:00:181
23251991917,1cyclictest0-21swapper/121:57:401
23251991916,2cyclictest1100-21snmpd19:10:221
23251991914,3cyclictest28976-21ls22:10:011
2324599192,16cyclictest26296-21egrep19:15:140
23245991917,1cyclictest0-21swapper/023:01:390
23245991915,3cyclictest3053-21systemd-logind23:18:520
23245991915,2cyclictest0-21swapper/021:00:150
2325899182,2cyclictest22786-21expr23:50:192
2325899182,15cyclictest4994-21cat21:25:162
23258991815,2cyclictest20963-21fschecks_count20:00:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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