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2026-01-27 - 18:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Tue Jan 27, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3234699292,16cyclictest0-21swapper/109:55:521
3235199240,3cyclictest0-21swapper/210:45:202
3235199240,23cyclictest28000-21fschecks_count08:55:162
3235199240,23cyclictest28000-21fschecks_count08:55:152
3234699240,23cyclictest0-21swapper/107:45:191
3235199230,22cyclictest9002-21ls12:10:152
3235199230,22cyclictest19202-21cat07:40:222
3235199230,22cyclictest13310-21latency_hist12:20:002
3235199230,21cyclictest19720-21sed09:39:002
3235199230,21cyclictest10685-21latency_hist10:20:012
3234699230,5cyclictest0-21swapper/111:25:061
3234699230,5cyclictest0-21swapper/108:13:571
32351992215,6cyclictest4587-21wc11:05:162
3235199220,7cyclictest13569-21grep09:25:212
3235199220,21cyclictest7961-21processes09:15:202
3235199220,21cyclictest754-21expr07:10:142
3235199220,21cyclictest6791-21expr11:10:132
3235199220,21cyclictest32554-21cat11:00:012
3235199220,21cyclictest2816-21ls10:05:172
3235199220,21cyclictest24299-21awk07:50:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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