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2026-02-28 - 04:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Sat Feb 28, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20742993432,2cyclictest16477-21kworker/1:220:54:581
20742992927,2cyclictest0-21swapper/119:54:341
20742992819,9cyclictest0-21swapper/120:58:021
20747992727,0cyclictest0-21swapper/219:45:162
20742992516,0cyclictest0-21swapper/100:25:501
2074799230,5cyclictest0-21swapper/222:45:242
2074199230,18cyclictest1403-21latency_hist20:30:010
2074199230,0cyclictest0-21swapper/000:28:050
2074799220,18cyclictest0-21swapper/219:20:142
2074799220,16cyclictest4203-21fschecks_count23:25:152
20742992221,1cyclictest0-21swapper/100:05:021
2074199220,21cyclictest843-21systemd-network19:58:450
2074199220,18cyclictest0-21swapper/023:33:280
2074799215,15cyclictest7097-21sed20:39:002
20747992117,3cyclictest26455-21grep22:10:152
20747992117,3cyclictest0-21swapper/200:14:392
2074799210,3cyclictest0-21swapper/222:07:362
2074799210,18cyclictest0-21swapper/222:19:132
2074199212,16cyclictest0-21swapper/021:10:080
2074799202,17cyclictest0-21swapper/200:22:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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