You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-30 - 20:23
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Mon Mar 30, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270599230,5cyclictest0-21swapper/108:05:471
269899230,19cyclictest3741-21latency_hist11:00:000
2705992221,1cyclictest0-21swapper/110:10:561
269899212,17cyclictest0-21swapper/007:45:010
270599208,11cyclictest0-21swapper/110:01:251
269899203,16cyclictest0-21swapper/012:21:350
2709991917,1cyclictest0-21swapper/209:50:402
2709991914,3cyclictest16455-21nvmesmart_nvme009:25:202
270599192,3cyclictest13147-21munin-run08:25:011
2705991916,2cyclictest9672-21awk12:05:191
270599190,18cyclictest0-21swapper/111:57:571
270599190,18cyclictest0-21swapper/111:57:571
270599190,17cyclictest16749-21snapd12:25:181
270999183,1cyclictest28-21ksoftirqd/208:22:422
2709991816,1cyclictest190592sleep210:29:362
2709991815,2cyclictest9781-21smartctl12:05:212
270999180,17cyclictest16745-21snapd09:45:482
270599183,1cyclictest0-21swapper/107:35:121
270599182,2cyclictest30216-21cat07:55:231
270599182,15cyclictest71402chrt08:14:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional