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2026-01-14 - 09:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 14, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29322992624,1cyclictest7758-21mii-tool21:20:171
29317992626,0cyclictest0-21swapper/019:20:010
29317992424,0cyclictest0-21swapper/000:15:140
2932999230,18cyclictest0-21swapper/200:00:132
29317992317,5cyclictest9-21ksoftirqd/020:30:120
2932999220,18cyclictest0-21swapper/220:37:292
2931799220,5cyclictest0-21swapper/019:51:220
29322992117,3cyclictest3987-21H222:10:211
2932299210,20cyclictest0-21swapper/121:13:081
29329992018,1cyclictest0-21swapper/220:08:552
2932999200,3cyclictest0-21swapper/220:45:222
2932299203,11cyclictest9110-21gpgv22:20:011
2932299201,1cyclictest0-21swapper/120:50:131
2931799204,15cyclictest16958-21expr20:40:130
2931799200,17cyclictest0-21swapper/021:55:200
2932999190,16cyclictest3989-21H222:10:212
2932299193,15cyclictest3983-21H222:10:211
29322991916,2cyclictest1217-21nfsd419:15:181
29322991915,3cyclictest16026-21php7.020:39:001
29322991914,3cyclictest0-21swapper/123:27:231
2932299191,17cyclictest0-21swapper/100:39:231
2932299190,2cyclictest4035-21H222:10:211
2932299190,1cyclictest0-21swapper/123:45:421
2932299190,18cyclictest3991-21H222:10:211
2932299190,16cyclictest3989-21H222:10:211
2931799193,15cyclictest3985-21H222:10:210
2931799192,2cyclictest31116-21expr22:00:190
2931799192,16cyclictest3007-21cat20:15:180
2931799192,16cyclictest0-21swapper/022:24:440
2931799192,16cyclictest0-21swapper/022:24:430
2931799192,16cyclictest0-21swapper/000:35:140
29317991917,1cyclictest20122-21expr22:35:190
29317991917,1cyclictest0-21swapper/023:05:000
29317991916,2cyclictest5620-21grep00:05:130
29317991916,2cyclictest4688-21switchtime23:05:200
29317991914,2cyclictest3976-21H222:10:210
2931799190,18cyclictest29035-21basename23:50:140
2931799190,18cyclictest18007-21latency_hist21:40:010
2931799190,18cyclictest0-21swapper/023:42:440
2931799190,18cyclictest0-21swapper/020:45:170
2931799190,16cyclictest4035-21H222:10:210
2932999182,15cyclictest30586-21chrt23:54:592
2932999182,15cyclictest0-21swapper/220:22:322
29329991817,1cyclictest28-21ksoftirqd/223:45:222
29329991816,1cyclictest28-21ksoftirqd/221:40:292
29329991814,3cyclictest3976-21H222:10:212
29329991814,3cyclictest3976-21H222:10:212
29329991813,2cyclictest3991-21H222:10:212
2932999180,3cyclictest472-21find21:09:002
2932999180,2cyclictest3987-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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