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2026-02-01 - 11:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Sun Feb 01, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2649899230,22cyclictest0-21swapper/119:40:141
2649799230,5cyclictest9803-21cat20:35:010
26499992212,5cyclictest0-21swapper/221:30:162
2649899220,21cyclictest870-21systemd-logind19:48:511
26497992216,5cyclictest0-21swapper/019:15:010
2649799220,18cyclictest0-21swapper/021:28:510
2649799214,13cyclictest16694-21gpgv22:40:000
26499992016,3cyclictest0-21swapper/221:20:432
26498992012,7cyclictest843-21systemd-network22:57:451
2649899200,16cyclictest0-21swapper/120:53:591
2649799203,2cyclictest27759-21latency_hist23:55:010
2649799202,15cyclictest0-21swapper/023:41:370
26497992013,4cyclictest6404-21fschecks_count19:30:140
26499991916,2cyclictest30999-21processes19:15:212
26499991915,3cyclictest0-21swapper/223:32:502
2649999190,18cyclictest0-21swapper/221:59:352
2649899192,16cyclictest9093-21cpuspeed_turbos21:30:161
26498991917,1cyclictest0-21swapper/122:39:401
2649899190,17cyclictest3976-21H222:10:211
2649899190,17cyclictest3976-21H222:10:211
2649899190,16cyclictest4035-21H222:10:211
2649899190,16cyclictest3985-21H222:10:211
2649799193,1cyclictest0-21swapper/021:43:240
2649799190,2cyclictest3989-21H222:10:210
2649799190,18cyclictest0-21swapper/019:59:130
2649999182,1cyclictest21134-21latency22:45:162
2649999182,15cyclictest136322chrt21:35:532
26499991815,2cyclictest31726-21wc21:10:232
26499991814,3cyclictest3981-21H222:10:212
26499991814,3cyclictest3450-21gsd-color22:05:012
26499991814,3cyclictest12778-21grep22:30:192
26499991814,3cyclictest10189-21perf23:25:012
26499991814,2cyclictest6349-21nfsd423:15:162
26499991813,4cyclictest28-21ksoftirqd/219:30:332
2649999181,16cyclictest3979-21H222:10:212
2649999180,2cyclictest3981-21H222:10:212
2649999180,17cyclictest3991-21H222:10:212
2649999180,17cyclictest3989-21H222:10:212
2649999180,17cyclictest3989-21H222:10:212
2649999180,17cyclictest3985-21H222:10:212
2649899183,1cyclictest0-21swapper/123:26:411
2649899182,15cyclictest7124-21chrt23:16:191
2649899182,15cyclictest3985-21H222:10:211
26498991815,2cyclictest3988-21H222:10:211
26498991814,3cyclictest3991-21H222:10:211
26498991814,3cyclictest3987-21H222:10:211
26498991814,3cyclictest1550-21snapd00:37:391
2649899181,16cyclictest29529-21chrt19:15:131
2649899181,16cyclictest13060-21nvmesmart_nvme021:35:191
2649899180,2cyclictest3987-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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