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2026-05-29 - 17:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Fri May 29, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
116099242,4cyclictest0-21swapper/008:20:010
116199230,22cyclictest0-21swapper/111:52:331
116299213,2cyclictest24707-21timerwakeupswit12:00:212
1162992016,3cyclictest0-21swapper/207:12:522
116199202,17cyclictest0-21swapper/110:00:131
1161992017,2cyclictest3985-21H222:10:211
1161992017,2cyclictest0-21swapper/111:00:191
1161992017,2cyclictest0-21swapper/108:15:011
116099204,15cyclictest0-21swapper/010:40:140
116099203,11cyclictest0-21swapper/007:33:230
1162991916,2cyclictest993-21dbus-daemon11:25:202
1162991916,2cyclictest28-21ksoftirqd/209:38:322
1162991916,2cyclictest25099-21grep11:10:162
1162991915,3cyclictest3976-21H222:10:212
1162991915,3cyclictest0-21swapper/208:46:222
116299190,17cyclictest0-21swapper/209:48:222
116299190,16cyclictest3989-21H222:10:212
1161991917,1cyclictest0-21swapper/112:10:121
1161991917,1cyclictest0-21swapper/108:04:481
1161991916,2cyclictest3991-21H222:10:211
1161991916,2cyclictest3991-21H222:10:211
1161991916,1cyclictest0-21swapper/108:17:551
1161991915,3cyclictest0-21swapper/111:38:011
1161991914,4cyclictest0-21swapper/110:13:351
1161991914,2cyclictest3981-21H222:10:211
116199191,16cyclictest2007-21systemd-journal09:50:321
116199191,16cyclictest0-21swapper/112:10:011
116199190,16cyclictest3981-21H222:10:211
1160991917,1cyclictest0-21swapper/011:35:040
1160991917,1cyclictest0-21swapper/009:58:530
1160991917,1cyclictest0-21swapper/009:21:370
1160991916,2cyclictest4983-21expr12:25:120
116099190,18cyclictest0-21swapper/011:01:550
116099190,16cyclictest3976-21H222:10:210
1162991817,1cyclictest28-21ksoftirqd/210:14:512
1162991816,1cyclictest0-21swapper/211:57:592
1162991816,1cyclictest0-21swapper/211:48:512
1162991816,1cyclictest0-21swapper/211:10:012
1162991816,1cyclictest0-21swapper/208:34:042
1162991815,2cyclictest0-21swapper/207:20:132
1162991814,3cyclictest6056-21cat10:40:012
1162991813,2cyclictest3991-21H222:10:212
116299181,2cyclictest0-21swapper/212:25:132
116299180,3cyclictest31651-21anvil10:28:532
116299180,2cyclictest5261-21latency_hist07:20:012
116299180,2cyclictest4035-21H222:10:212
116299180,2cyclictest3989-21H222:10:212
116299180,2cyclictest3976-21H222:10:212
116299180,17cyclictest993-21dbus-daemon11:52:102
116299180,17cyclictest10623-21latency_hist08:55:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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