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2026-09-18 - 10:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Fri Sep 18, 2026 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
712599220,4cyclictest0-21swapper/020:48:170
712799212,18cyclictest9275-21cron00:00:002
7127992116,3cyclictest31753-21proc_pri23:40:212
712599212,18cyclictest0-21swapper/000:00:300
712799209,10cyclictest0-21swapper/220:45:162
712799204,15cyclictest0-21swapper/223:30:132
712799200,18cyclictest0-21swapper/221:32:322
712799192,2cyclictest28348-21nfsd419:45:182
712799192,2cyclictest1622-21nfsd419:55:172
7126991917,1cyclictest0-21swapper/123:41:181
712699190,1cyclictest0-21swapper/122:30:211
712699190,1cyclictest0-21swapper/100:31:151
712599193,15cyclictest16329-21timerwakeupswit22:15:220
712599193,15cyclictest16329-21timerwakeupswit22:15:210
7125991917,1cyclictest0-21swapper/023:48:380
7125991916,2cyclictest23324-21cpuspeed_turbos22:30:170
712799183,1cyclictest0-21swapper/220:17:182
712799182,15cyclictest0-21swapper/222:10:192
7127991816,1cyclictest0-21swapper/223:25:222
7127991816,1cyclictest0-21swapper/221:24:292
7127991815,2cyclictest11912-21ntp_offset21:10:202
7127991815,2cyclictest0-21swapper/220:10:182
7127991814,3cyclictest30940-21sshd22:43:442
7127991814,3cyclictest30940-21sshd22:43:432
7127991814,3cyclictest0-21swapper/222:25:002
7127991814,2cyclictest11482-21nfsd419:15:182
712799181,16cyclictest26372-21/usr/sbin/munin00:30:142
712799181,16cyclictest23357-21find19:39:002
712799181,16cyclictest15854-21date23:15:002
712799181,16cyclictest0-21swapper/220:30:142
712799181,16cyclictest0-21swapper/220:30:132
712799180,17cyclictest6463-21pzem_energy22:55:212
712799180,17cyclictest5912-21nvmesmart_nvme021:00:202
712799180,17cyclictest25355-21ls00:25:222
712799180,17cyclictest25355-21ls00:25:212
712799180,17cyclictest0-21swapper/222:49:292
712699182,15cyclictest0-21swapper/119:10:471
7126991815,2cyclictest3976-21H222:10:211
7126991815,2cyclictest1696-21smartctl19:55:191
7126991814,3cyclictest0-21swapper/120:53:211
712699181,2cyclictest19424-21tune2fs21:25:131
712699181,16cyclictest18806-21mailstats22:20:211
712699180,3cyclictest12568-21sshd21:11:431
712699180,1cyclictest0-21swapper/121:20:211
712699180,1cyclictest0-21swapper/119:20:131
712699180,17cyclictest16798-21perf22:20:011
712699180,17cyclictest16798-21perf22:20:001
712699180,16cyclictest3983-21H222:10:211
712699180,16cyclictest1564-21cut20:55:131
712699180,15cyclictest3976-21H222:10:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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