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2026-06-20 - 17:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Sat Jun 20, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7447992927,1cyclictest0-21swapper/010:25:020
745699230,5cyclictest271rcuc/207:16:162
744799230,5cyclictest0-21swapper/008:11:570
744799220,18cyclictest0-21swapper/007:44:580
7456992119,1cyclictest28-21ksoftirqd/208:50:012
745199210,17cyclictest0-21swapper/112:37:171
744799214,16cyclictest14417-21gpgconf08:20:010
744799210,3cyclictest0-21swapper/009:43:190
744799210,18cyclictest0-21swapper/010:18:030
745699203,11cyclictest17378-21updatedb.mlocat08:25:012
745699203,11cyclictest17378-21updatedb.mlocat08:25:002
745699202,17cyclictest0-21swapper/211:30:142
745699200,19cyclictest399-20systemd-journal12:02:422
745199204,15cyclictest0-21swapper/110:21:181
744799204,15cyclictest0-21swapper/008:35:030
744799203,16cyclictest14193-21sh11:09:000
744799203,16cyclictest0-21swapper/010:24:040
744799202,17cyclictest0-21swapper/012:09:130
744799202,17cyclictest0-21swapper/011:15:140
7447992017,2cyclictest8119-21cpuspeed_turbos10:00:130
7447992016,1cyclictest0-21swapper/011:20:200
7456991916,2cyclictest10896-21cpuspeed_turbos10:05:142
745699190,1cyclictest0-21swapper/209:55:182
745199192,16cyclictest16596-21cstates10:15:141
744799192,2cyclictest7067-21grep10:55:160
744799192,2cyclictest22666-21expr12:20:140
744799192,16cyclictest32628-21expr11:40:180
744799192,16cyclictest11568-21interrupts12:00:160
744799192,16cyclictest0-21swapper/010:06:430
7447991916,2cyclictest21195-21cpuspeed_turbos08:30:120
7447991913,1cyclictest0-21swapper/009:20:160
744799191,17cyclictest0-21swapper/009:47:050
744799190,1cyclictest0-21swapper/010:33:500
744799190,18cyclictest522-21latency_hist12:40:010
744799190,18cyclictest4272-21fschecks_count08:55:160
744799190,17cyclictest0-21swapper/011:01:290
744799190,16cyclictest28174-21latency_hist09:40:010
7456991818,0cyclictest0-21swapper/210:15:122
7456991816,1cyclictest28-21ksoftirqd/209:14:262
7456991816,1cyclictest271rcuc/210:10:192
7456991816,1cyclictest0-21swapper/211:45:492
7456991815,2cyclictest28-21ksoftirqd/207:40:012
7456991815,2cyclictest28-21ksoftirqd/207:40:012
745699181,2cyclictest16659-21expr12:10:132
745699180,15cyclictest0-21swapper/208:40:212
745199182,15cyclictest21-21ksoftirqd/111:15:131
7451991816,1cyclictest23762-21cron07:39:021
7451991816,1cyclictest23762-21cron07:39:011
7451991815,2cyclictest2904-21fschecks_count09:50:141
7451991815,2cyclictest1321-21perf11:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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