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2026-01-18 - 15:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Sun Jan 18, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19020992610,15cyclictest12653-21ls10:00:011
1901699252,1cyclictest0-21swapper/011:15:310
19016992517,2cyclictest1765-21cat10:35:220
1902699230,5cyclictest0-21swapper/212:10:012
1902099230,5cyclictest0-21swapper/109:13:021
1902699210,18cyclictest0-21swapper/208:05:112
1902099212,18cyclictest0-21swapper/112:10:181
1902099211,17cyclictest0-21swapper/107:44:441
1901699210,2cyclictest3985-21H222:10:210
1902699202,17cyclictest13749-21perf09:05:002
1902699202,15cyclictest0-21swapper/210:30:072
1902699201,3cyclictest0-21swapper/210:10:302
1902099203,13cyclictest0-21swapper/110:27:421
1902099200,3cyclictest3985-21H222:10:211
1902099200,19cyclictest0-21swapper/108:08:161
19016992017,2cyclictest1416-21php7.208:38:590
1902699192,16cyclictest0-21swapper/207:35:162
19026991916,1cyclictest0-21swapper/212:00:512
1902699191,17cyclictest3987-21H222:10:212
1902699190,2cyclictest4035-21H222:10:212
1902699190,16cyclictest3991-21H222:10:212
1902099190,17cyclictest8887-21cpuspeed_turbos10:50:121
19016991914,4cyclictest14541-21cron08:05:000
1902699182,15cyclictest292142chrt12:21:292
1902699182,15cyclictest161222sleep211:00:402
1902699182,15cyclictest0-21swapper/207:33:002
19026991817,1cyclictest29148-21nfsd407:25:182
19026991816,1cyclictest0-21swapper/210:05:152
19026991815,2cyclictest455-21plymouthd09:24:562
19026991815,2cyclictest21971-21chrt11:13:532
1902699181,2cyclictest0-21swapper/211:20:202
1902699181,16cyclictest8206-21chrt08:54:342
1902699180,2cyclictest4099-21H222:10:212
1902699180,2cyclictest4099-21H222:10:212
1902699180,17cyclictest23409-21anvil10:20:022
1902699180,17cyclictest23409-21anvil10:20:012
1902699180,15cyclictest4035-21H222:10:212
19020991815,2cyclictest3985-21H222:10:211
19020991815,2cyclictest0-21swapper/111:25:361
19020991815,1cyclictest0-21swapper/111:59:451
19020991814,3cyclictest3976-21H222:10:211
1902099181,1cyclictest0-21swapper/107:10:481
1902099180,2cyclictest3985-21H222:10:211
1902099180,17cyclictest3979-21H222:10:211
1902099180,15cyclictest3983-21H222:10:211
1901699183,15cyclictest9-21ksoftirqd/012:39:090
1901699183,15cyclictest0-21swapper/007:40:010
1901699182,1cyclictest0-21swapper/008:10:230
1901699182,15cyclictest9-21ksoftirqd/012:09:550
19016991816,1cyclictest0-21swapper/009:17:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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