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2026-01-17 - 14:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Sat Jan 17, 2026 00:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2757999234,17cyclictest14644-21cat00:30:122
2757999225,16cyclictest15644-21expr23:35:142
27579992219,2cyclictest21104-21cut22:45:162
27579992219,2cyclictest18498-21ntpq22:40:172
27579992218,3cyclictest26978-21tr23:55:122
27579992218,3cyclictest26686-21cut20:05:132
27578992213,0cyclictest0-21swapper/100:25:181
2757799220,4cyclictest0-21swapper/022:52:360
2757799220,21cyclictest843-21systemd-network20:30:160
2757999214,2cyclictest3802-21expr00:10:112
2757999214,16cyclictest32551-21cut00:05:132
2757999214,16cyclictest32551-21cut00:05:132
2757999214,16cyclictest16045-21if_lxdbr021:40:142
2757999213,17cyclictest9658-21grep23:25:012
2757999213,15cyclictest0-21swapper/200:27:442
27579992118,2cyclictest1961-21sort21:15:172
27579992118,2cyclictest16935-21expr20:45:122
27579992117,3cyclictest26051-21basename22:55:162
2757999203,2cyclictest533-21munin-run19:20:012
2757999203,2cyclictest0-21swapper/222:20:202
2757999203,2cyclictest0-21swapper/222:20:192
2757999203,2cyclictest0-21swapper/220:40:172
2757999203,16cyclictest29985-21expr00:00:132
2757999203,16cyclictest0-21swapper/223:45:132
2757999203,16cyclictest0-21swapper/221:08:342
2757999202,17cyclictest386-21sed22:10:142
2757999202,17cyclictest0-21swapper/220:51:052
27579992017,2cyclictest675-21sessionclean23:09:012
27579992017,2cyclictest4672-21expr23:15:112
27579992017,2cyclictest3991-21H222:10:212
27579992017,2cyclictest30252-21mii-tool20:10:152
27579992017,2cyclictest30252-21mii-tool20:10:152
27579992017,2cyclictest18229-21sed00:35:162
27579992017,2cyclictest0-21swapper/223:40:162
27579992016,3cyclictest0-21swapper/221:12:432
27579992016,3cyclictest0-21swapper/221:00:122
27579992013,3cyclictest0-21swapper/221:45:022
2757899202,16cyclictest0-21swapper/100:03:251
27578992017,2cyclictest21525-21cpuspeed_turbos23:45:131
27577992011,5cyclictest0-21swapper/022:35:190
2757999192,2cyclictest21551-21expr21:50:132
2757999192,16cyclictest7540-21date21:25:152
2757999192,16cyclictest0-21swapper/223:03:262
2757999192,16cyclictest0-21swapper/222:05:112
2757999192,16cyclictest0-21swapper/221:55:142
2757999192,16cyclictest0-21swapper/221:55:142
2757999192,16cyclictest0-21swapper/221:24:072
2757999192,16cyclictest0-21swapper/220:35:172
27579991917,1cyclictest14375-21sendmail-mta21:37:522
27579991917,1cyclictest0-21swapper/222:25:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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