You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-28 - 06:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Wed Jan 28, 2026 00:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1823399253,18cyclictest29173-21sed22:20:000
18235992320,2cyclictest8392-21ntp_kernel_err00:30:192
18235992320,2cyclictest8392-21ntp_kernel_err00:30:192
1823499230,5cyclictest0-21swapper/120:30:131
1823599220,21cyclictest0-21swapper/219:40:412
1823499220,19cyclictest0-21swapper/121:36:571
18234992118,2cyclictest29201-21cut21:20:171
18235992017,1cyclictest0-21swapper/222:43:062
18234992016,3cyclictest0-21swapper/123:00:011
1823499200,1cyclictest0-21swapper/119:55:211
1823499200,19cyclictest0-21swapper/123:25:111
18233992018,1cyclictest9-21ksoftirqd/019:40:420
18235991917,1cyclictest28-21ksoftirqd/221:50:362
18235991917,1cyclictest28-21ksoftirqd/219:34:562
18235991917,1cyclictest0-21swapper/220:55:142
18235991916,1cyclictest0-21swapper/200:22:132
18235991915,3cyclictest0-21swapper/220:12:012
18235991915,3cyclictest0-21swapper/200:04:432
18235991914,2cyclictest4035-21H222:10:212
1823599190,2cyclictest3987-21H222:10:212
1823599190,1cyclictest0-21swapper/223:30:172
1823599190,16cyclictest4035-21H222:10:212
1823599190,16cyclictest3991-21H222:10:212
1823599190,16cyclictest3983-21H222:10:212
1823499193,1cyclictest25148-21sed19:20:151
1823499193,1cyclictest25148-21sed19:20:151
1823499193,15cyclictest19633-21grep23:00:131
1823499191,17cyclictest3404-21grep22:30:151
1823499190,1cyclictest12251-21perf00:40:001
1823499190,17cyclictest3991-21H222:10:211
1823499190,16cyclictest3976-21H222:10:211
1823399192,2cyclictest18178-21chrt23:52:520
1823399192,16cyclictest866-21seq23:24:000
18233991917,1cyclictest0-21swapper/000:09:050
18233991914,3cyclictest3989-21H222:10:210
1823399190,18cyclictest0-21swapper/020:23:120
1823399190,15cyclictest0-21swapper/023:30:160
18235991816,1cyclictest28-21ksoftirqd/222:26:122
18235991816,1cyclictest28-21ksoftirqd/200:06:522
18235991816,1cyclictest0-21swapper/222:00:522
18235991814,3cyclictest1485-21snapd23:22:382
18235991814,3cyclictest1348-21lxd20:28:482
1823599181,16cyclictest993-21dbus-daemon22:50:192
1823599181,16cyclictest3981-21H222:10:212
18235991811,6cyclictest30957-21ps22:20:192
1823599180,2cyclictest3985-21H222:10:212
1823599180,2cyclictest3983-21H222:10:212
1823599180,2cyclictest3983-21H222:10:212
1823599180,2cyclictest3976-21H222:10:212
1823599180,2cyclictest3976-21H222:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional