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2026-01-30 - 23:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot0.osadl.org (updated Fri Jan 30, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
847699242,18cyclictest11962-21sed12:00:010
848599213,16cyclictest29021-21chmod09:40:002
848599212,16cyclictest0-21swapper/208:14:072
848599203,11cyclictest32069-21cat09:45:012
8480992010,0cyclictest0-21swapper/112:31:261
847699203,1cyclictest0-21swapper/007:59:390
8485991916,2cyclictest3987-21H222:10:212
8485991916,2cyclictest21632-21sshd08:30:112
8485991915,3cyclictest0-21swapper/209:10:302
8485991912,5cyclictest0-21swapper/212:39:422
848599191,17cyclictest0-21swapper/212:30:132
848099193,1cyclictest10828-21expr08:10:121
848099192,16cyclictest0-21swapper/109:49:211
8480991916,2cyclictest6113-21if_lxdbr010:50:151
8480991915,3cyclictest0-21swapper/110:02:181
8480991914,4cyclictest482-21cat08:50:001
848099191,3cyclictest0-21swapper/108:15:131
847699193,1cyclictest0-21swapper/012:04:310
847699192,1cyclictest0-21swapper/008:20:180
847699192,1cyclictest0-21swapper/008:20:170
847699192,16cyclictest863-21avahi-daemon09:20:210
8476991914,3cyclictest0-21swapper/010:17:070
847699190,16cyclictest3989-21H222:10:210
847699190,16cyclictest3989-21H222:10:210
848599182,15cyclictest29139-21expr07:45:132
848599182,15cyclictest28489-21nfsd408:40:172
848599182,15cyclictest0-21swapper/212:20:172
8485991815,2cyclictest3732-21munin-plugin-st08:55:022
8485991815,2cyclictest2339-21expr10:45:152
848599181,2cyclictest15475-21chrt08:16:362
848599181,16cyclictest993-21dbus-daemon09:05:212
848599181,16cyclictest0-21swapper/208:45:172
848599180,3cyclictest19024-21sh11:15:012
848599180,17cyclictest0-21swapper/211:26:212
848599180,17cyclictest0-21swapper/211:26:212
848599180,16cyclictest0-21swapper/207:57:262
848599180,16cyclictest0-21swapper/207:21:542
8480991816,1cyclictest17716-21uname08:20:191
8480991816,1cyclictest17716-21uname08:20:191
8480991815,2cyclictest12751-21expr12:00:141
8480991814,3cyclictest20997-21grep09:25:131
8480991814,3cyclictest1351-21lxd11:34:451
848099180,3cyclictest3987-21H222:10:211
848099180,17cyclictest3987-21H222:10:211
848099180,17cyclictest0-21swapper/108:03:501
848099180,16cyclictest0-21swapper/110:37:511
8476991814,3cyclictest4036-21H222:10:210
847699180,2cyclictest3987-21H222:10:210
847699180,16cyclictest7980-21nfsd411:50:170
847699180,16cyclictest3991-21H222:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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