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2026-03-07 - 13:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Mar 06, 2026 12:45:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
982121700,6sleep02191699cyclictest11:20:210
2268621430,4sleep32191999cyclictest10:40:123
3177921420,7sleep22191899cyclictest08:40:172
2141021180,4sleep22191899cyclictest10:35:262
119042760,5sleep10-21swapper/110:15:191
134491630,5ptp4l0-21swapper/010:20:270
134491620,3ptp4l0-21swapper/212:25:302
21919996137,4cyclictest41-21ksoftirqd/312:33:093
21918996128,4cyclictest33-21ksoftirqd/209:40:002
158202610,5sleep10-21swapper/109:15:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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