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2025-12-30 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Dec 30, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2622621770,5sleep01116999cyclictest12:20:010
1263721450,3sleep31117299cyclictest08:20:193
185112780,7sleep11117099cyclictest07:25:131
11171997033,8cyclictest33-21ksoftirqd/210:00:002
11171997033,8cyclictest33-21ksoftirqd/209:59:592
11171996731,6cyclictest33-21ksoftirqd/208:55:262
11171996633,9cyclictest33-21ksoftirqd/208:14:592
11171996532,5cyclictest33-21ksoftirqd/208:04:592
11171996528,8cyclictest33-21ksoftirqd/211:15:012
11171996434,7cyclictest33-21ksoftirqd/209:24:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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