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2026-06-13 - 05:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jun 13, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491730,10ptp4l26579-21hddtemp_smartct19:05:150
28487997028,5cyclictest41-21ksoftirqd/323:11:323
28485996733,8cyclictest25-21ksoftirqd/120:03:241
28485996732,9cyclictest25-21ksoftirqd/122:40:011
28487996336,3cyclictest41-21ksoftirqd/300:35:003
28487996331,5cyclictest41-21ksoftirqd/320:54:533
28487996326,5cyclictest41-21ksoftirqd/319:39:153
28485996332,8cyclictest25-21ksoftirqd/121:50:141
28485996332,5cyclictest25-21ksoftirqd/123:15:181
28485996328,7cyclictest25-21ksoftirqd/123:40:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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