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2026-07-24 - 16:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jul 24, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
424521960,39sleep2321ktimersoftd/207:10:002
313721640,6sleep2432399cyclictest08:15:202
409021360,5sleep1432299cyclictest09:25:271
1460921340,6sleep0432199cyclictest11:00:180
1460921340,6sleep0432199cyclictest11:00:180
109992820,5sleep20-21swapper/208:30:282
134491620,6ptp4l1863-21/usr/sbin/munin07:05:223
134491600,4ptp4l0-21swapper/011:46:010
134491590,5ptp4l0-21swapper/208:39:262
134491590,4ptp4l0-21swapper/010:17:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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