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2026-09-08 - 01:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Sep 07, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2377421180,4sleep00-21swapper/008:05:200
2975699749,22cyclictest12391-21df_abs12:20:153
134491690,4ptp4l0-21swapper/207:20:212
134491640,5ptp4l11496-21df_abs07:40:140
134491640,5ptp4l11496-21df_abs07:40:140
92842610,7sleep02975399cyclictest09:55:000
134491590,4ptp4l0-21swapper/112:00:261
134491580,5ptp4l0-21swapper/011:09:150
134491580,4ptp4l0-21swapper/010:25:200
134491580,3ptp4l0-21swapper/009:00:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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