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2026-06-04 - 21:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jun 04, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6484996332,4cyclictest41-21ksoftirqd/310:58:023
6484996332,4cyclictest41-21ksoftirqd/310:58:023
134491630,21ptp4l26406-21sed11:20:140
6484996229,7cyclictest41-21ksoftirqd/307:30:003
6484996229,4cyclictest41-21ksoftirqd/309:56:163
6484996229,4cyclictest41-21ksoftirqd/309:56:153
3151926229,8sleep233-21ksoftirqd/208:00:272
6484996132,4cyclictest41-21ksoftirqd/310:55:003
6484996129,4cyclictest41-21ksoftirqd/309:41:123
6484996027,8cyclictest41-21ksoftirqd/307:59:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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