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2026-08-19 - 21:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 19, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3043721550,5sleep31734499cyclictest08:45:273
17343997513,60cyclictest0-21swapper/208:55:282
134491700,23ptp4l21975-21/usr/sbin/munin07:20:263
17344996812,54cyclictest0-21swapper/311:12:293
134491660,5ptp4l0-21swapper/107:45:281
1734499651,62cyclictest0-21swapper/309:56:493
17343996430,3cyclictest33-21ksoftirqd/209:20:182
17343996329,4cyclictest33-21ksoftirqd/210:50:002
17344996215,45cyclictest0-21swapper/311:19:293
17343995926,4cyclictest33-21ksoftirqd/207:18:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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