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2026-01-30 - 02:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jan 29, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1249499697,19cyclictest21545-21phc2sys-jitter08:35:243
12492996733,7cyclictest25-21ksoftirqd/110:45:001
12492996630,9cyclictest25-21ksoftirqd/112:10:141
12492996630,9cyclictest25-21ksoftirqd/112:10:141
1249499653,18cyclictest0-21swapper/309:10:163
1249499653,18cyclictest0-21swapper/309:10:163
12492996531,6cyclictest25-21ksoftirqd/107:45:001
76632640,6sleep01249199cyclictest11:35:160
76632640,6sleep01249199cyclictest11:35:160
1249499647,18cyclictest0-21swapper/308:55:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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