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2026-02-19 - 05:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 19, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2043421770,3sleep22834299cyclictest22:20:182
2043421770,3sleep22834299cyclictest22:20:182
287432680,4sleep20-21swapper/219:10:142
134491650,4ptp4l0-21swapper/119:55:211
2834399645,11cyclictest0-21swapper/319:30:243
2834399645,11cyclictest0-21swapper/319:30:243
28343996122,6cyclictest41-21ksoftirqd/300:15:003
134491610,5ptp4l0-21swapper/119:30:231
134491610,5ptp4l0-21swapper/119:30:231
28343996029,4cyclictest41-21ksoftirqd/320:50:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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