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2026-02-11 - 09:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Feb 11, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2634399782,74cyclictest0-21swapper/221:20:292
2634399762,72cyclictest0-21swapper/221:05:292
134491720,3ptp4l121rcu_preempt20:05:142
321912680,5sleep30-21swapper/322:50:183
321912680,5sleep30-21swapper/322:50:183
26342996812,11cyclictest28362-21taskset19:14:161
26342996312,11cyclictest31301-21seq22:48:331
26342996312,11cyclictest2755-21seq19:26:491
26342996310,12cyclictest16787-21taskset19:55:561
26342996212,11cyclictest19466-21taskset21:12:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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