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2026-08-19 - 09:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 19, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36521710,6sleep12683899cyclictest00:00:151
2683999801,77cyclictest0-21swapper/221:05:292
26839998015,63cyclictest0-21swapper/220:20:292
2683999672,63cyclictest0-21swapper/222:30:282
134491610,4ptp4l0-21swapper/023:20:150
2683999602,56cyclictest0-21swapper/223:47:082
2683999602,56cyclictest0-21swapper/219:13:492
134491580,3ptp4l30820-21wc21:35:200
134491580,3ptp4l0-21swapper/319:20:163
134491570,5ptp4l0-21swapper/220:25:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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