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2026-06-23 - 07:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 23, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1340799698,17cyclictest24579-21sshd00:10:221
1340799655,17cyclictest13089-21cat23:45:261
134491640,3ptp4l30983-21irqstats22:05:203
1340799648,11cyclictest8476-21grep21:15:271
1340799634,17cyclictest21705-21cut00:05:191
134491610,4ptp4l0-21swapper/000:00:270
134491610,18ptp4l12021-21fw_packets22:35:170
1340799617,16cyclictest32141-21chrt00:26:231
134491600,3ptp4l0-21swapper/100:00:291
1340799609,9cyclictest15578-21unixbench_singl22:40:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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