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2026-06-13 - 17:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jun 13, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
569521380,5sleep22121099cyclictest12:20:262
2121199702,6cyclictest0-21swapper/311:56:113
21210996830,4cyclictest33-21ksoftirqd/210:00:002
21210996534,5cyclictest33-21ksoftirqd/207:15:292
21210996533,5cyclictest33-21ksoftirqd/209:55:002
21210996532,4cyclictest33-21ksoftirqd/211:25:002
21210996531,6cyclictest33-21ksoftirqd/210:10:242
21210996431,4cyclictest33-21ksoftirqd/212:05:262
21210996325,4cyclictest33-21ksoftirqd/212:40:002
21210996324,16cyclictest33-21ksoftirqd/212:15:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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