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2025-12-31 - 08:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Dec 31, 2025 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2379321720,6sleep01078899cyclictest23:05:200
1031921610,5sleep31079199cyclictest20:15:293
314221460,7sleep31079199cyclictest23:30:183
1881921390,5sleep01078899cyclictest20:35:210
1079199690,3cyclictest25649-21tr23:10:123
1079199682,1cyclictest0-21swapper/321:45:143
10788996830,9cyclictest9-21ksoftirqd/023:00:160
134491640,20ptp4l0-21swapper/219:15:132
10788996428,11cyclictest9-21ksoftirqd/023:45:150
134491620,5ptp4l0-21swapper/221:20:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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