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2026-09-24 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Sep 23, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2687121700,3sleep23203099cyclictest11:35:272
3187521390,3sleep03202699cyclictest11:45:280
32028997227,4cyclictest25-21ksoftirqd/111:35:001
32028997026,6cyclictest25-21ksoftirqd/108:45:191
134491690,4ptp4l0-21swapper/212:34:492
32028996833,6cyclictest25-21ksoftirqd/110:34:591
32028996828,7cyclictest25-21ksoftirqd/111:35:281
32028996827,7cyclictest25-21ksoftirqd/108:10:161
32028996729,7cyclictest25-21ksoftirqd/108:25:131
32028996619,3cyclictest25-21ksoftirqd/107:10:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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