You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-25 - 09:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jan 25, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316372760,6sleep143199cyclictest22:35:141
319852720,4sleep00-21swapper/022:35:160
134491630,4ptp4l0-21swapper/000:35:230
134491600,5ptp4l22666-21iostat_ios22:15:190
134491600,4ptp4l0-21swapper/123:05:171
134491600,4ptp4l0-21swapper/100:26:091
134491590,4ptp4l0-21swapper/021:21:480
134491590,4ptp4l0-21swapper/021:21:480
134491580,4ptp4l0-21swapper/221:40:192
134491580,3ptp4l10963-21apt-get23:00:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional