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2026-05-23 - 20:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat May 23, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
197021630,3sleep22137899cyclictest07:35:382
2248221610,7sleep22137899cyclictest10:40:012
21378997915,61cyclictest30395-21ls08:35:292
21378996930,7cyclictest33-21ksoftirqd/211:45:262
21378996533,4cyclictest33-21ksoftirqd/211:15:162
21378996526,3cyclictest33-21ksoftirqd/209:05:002
21378996332,3cyclictest33-21ksoftirqd/211:25:592
21378996326,6cyclictest33-21ksoftirqd/207:25:002
21378996326,4cyclictest33-21ksoftirqd/211:44:592
134491630,5ptp4l0-21swapper/312:10:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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