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2026-07-08 - 03:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 08, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2721521590,6sleep3571599cyclictest23:25:123
571599802,32cyclictest0-21swapper/319:10:213
274242670,7sleep1571399cyclictest22:15:181
5712996527,4cyclictest9-21ksoftirqd/022:45:240
5715996433,7cyclictest41-21ksoftirqd/322:10:003
5712996426,3cyclictest9-21ksoftirqd/020:20:010
134491640,4ptp4l0-21swapper/219:08:032
5715996324,7cyclictest41-21ksoftirqd/319:30:143
5712996330,4cyclictest9-21ksoftirqd/020:48:000
5712996330,4cyclictest9-21ksoftirqd/019:31:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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