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2026-02-12 - 07:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 12, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491660,3ptp4l0-21swapper/221:30:242
134491650,4ptp4l0-21swapper/121:50:001
539899614,15cyclictest0-21swapper/323:35:003
134491610,3ptp4l7739-21ls23:50:260
134491600,4ptp4l22671-21fschecks_time23:15:130
134491600,3ptp4l0-21swapper/320:51:223
134491590,4ptp4l0-21swapper/100:15:211
134491580,3ptp4l0-21swapper/300:05:183
134491580,17ptp4l10268-21df19:20:160
134491580,17ptp4l10268-21df19:20:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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