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2026-02-19 - 17:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 19, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1360321690,7sleep32880999cyclictest11:15:123
727321530,2sleep32880999cyclictest08:40:243
727321530,2sleep32880999cyclictest08:40:243
2880899743,69cyclictest0-21swapper/208:40:282
2880899743,69cyclictest0-21swapper/208:40:282
2880899651,31cyclictest21878-21taskset09:11:532
28806996530,6cyclictest9-21ksoftirqd/011:40:250
28806996330,6cyclictest9-21ksoftirqd/008:50:260
2880899621,29cyclictest16117-21date12:30:002
28806996228,5cyclictest9-21ksoftirqd/007:25:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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