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2026-08-27 - 11:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Aug 27, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1149621580,7sleep11165899cyclictest21:25:281
1165999665,12cyclictest2113-21latency_hist20:00:012
47922650,3sleep14791-21rt-features23:30:251
134491650,5ptp4l10086-21irqrtprio19:05:173
134491650,4ptp4l0-21swapper/321:00:213
1165999627,9cyclictest9782-21unixbench_multi22:30:272
1165999626,11cyclictest30735-21ps00:25:252
1165999626,10cyclictest8562-21perl23:40:162
134491590,3ptp4l0-21swapper/319:44:423
1165999597,11cyclictest17895-21unixbench_multi19:20:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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