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2026-07-06 - 00:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jul 05, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
105962690,6sleep210598-21latency_hist07:55:012
22320996713,16cyclictest24153-21chrt08:22:001
22320996713,16cyclictest24153-21chrt08:22:001
22320996614,16cyclictest15176-21chrt09:13:151
22320996614,15cyclictest31768-21chrt09:48:491
22320996613,16cyclictest6567-21chrt12:22:331
22320996514,16cyclictest5750-21chrt07:43:321
134491650,4ptp4l0-21swapper/308:25:013
22320996413,15cyclictest24642-21chrt09:30:591
22320996413,15cyclictest10911-21taskset09:05:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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