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2026-04-25 - 17:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Apr 25, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
476921200,6sleep32751399cyclictest09:50:163
27511996832,5cyclictest25-21ksoftirqd/107:50:001
27511996831,8cyclictest25-21ksoftirqd/108:30:011
27511996427,7cyclictest25-21ksoftirqd/108:40:281
27511996423,4cyclictest25-21ksoftirqd/109:05:181
27511996332,4cyclictest25-21ksoftirqd/107:35:201
27511996328,4cyclictest25-21ksoftirqd/111:40:011
27511996328,4cyclictest25-21ksoftirqd/111:40:011
27511996326,7cyclictest25-21ksoftirqd/110:55:161
27511996321,13cyclictest25-21ksoftirqd/112:04:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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