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2025-12-26 - 00:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Dec 25, 2025 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1562621780,5sleep11022499cyclictest10:50:131
134491700,4ptp4l23161-21irqstats11:05:191
1022799617,7cyclictest0-21swapper/311:40:233
134491600,4ptp4l0-21swapper/112:00:011
88802590,3sleep38881-21irqrtprio08:15:193
134491590,4ptp4l0-21swapper/207:44:272
134491590,3ptp4l0-21swapper/209:46:342
134491590,3ptp4l0-21swapper/010:35:270
134491580,4ptp4l0-21swapper/012:15:140
134491580,3ptp4l10575-21/usr/sbin/munin09:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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