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2026-04-27 - 21:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Apr 27, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124152730,5sleep00-21swapper/009:18:440
134491670,3ptp4l9-21ksoftirqd/007:05:200
134491620,4ptp4l0-21swapper/308:15:003
134491620,4ptp4l0-21swapper/210:00:202
134491620,20ptp4l0-21swapper/009:10:150
134491610,4ptp4l20762-21ls09:35:222
17098996024,3cyclictest33-21ksoftirqd/211:00:002
17098996024,3cyclictest33-21ksoftirqd/211:00:002
17098995821,4cyclictest33-21ksoftirqd/211:31:472
134491580,4ptp4l0-21swapper/312:15:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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