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2026-01-27 - 01:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jan 26, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2628121590,6sleep31935199cyclictest12:00:233
2530821410,5sleep30-21swapper/308:30:213
6712630,5sleep10-21swapper/107:40:011
319962620,4sleep30-21swapper/307:35:223
134491600,5ptp4l0-21swapper/007:05:000
134491570,6ptp4l11271-21latency09:10:183
134491560,4ptp4l0-21swapper/310:53:073
134491560,4ptp4l0-21swapper/011:45:140
134491560,4ptp4l0-21swapper/011:45:140
134491560,3ptp4l0-21swapper/311:10:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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