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2026-05-10 - 08:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun May 10, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2940221640,6sleep33007699cyclictest20:15:283
30076997829,12cyclictest41-21ksoftirqd/321:35:023
30076996740,3cyclictest41-21ksoftirqd/322:50:253
66162650,3sleep30-21swapper/322:55:233
30076996339,3cyclictest41-21ksoftirqd/322:20:283
123292630,4sleep00-21swapper/000:15:270
123292630,4sleep00-21swapper/000:15:260
30076996230,4cyclictest41-21ksoftirqd/322:15:163
30076996226,8cyclictest41-21ksoftirqd/323:43:163
30076996136,3cyclictest41-21ksoftirqd/300:00:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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