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2026-07-31 - 18:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jul 31, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3033021540,2sleep03105599cyclictest10:35:240
2497521510,6sleep23105799cyclictest10:25:152
1106621430,3sleep23105799cyclictest08:45:182
1477621410,3sleep33105899cyclictest07:45:013
3008621380,7sleep03105599cyclictest09:25:190
134491700,3ptp4l121rcu_preempt07:15:132
31056996832,4cyclictest25-21ksoftirqd/112:35:001
31058996624,6cyclictest41-21ksoftirqd/309:30:273
134491660,4ptp4l6927-21ntp_states08:35:243
31056996429,4cyclictest25-21ksoftirqd/109:05:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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