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2026-08-10 - 08:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Aug 10, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1413221450,6sleep2900299cyclictest22:47:332
900299822,78cyclictest0-21swapper/220:35:292
900299812,77cyclictest0-21swapper/223:50:292
900299781,2cyclictest0-21swapper/219:45:492
900299691,4cyclictest855-21meminfo20:00:292
112072680,3sleep341-21ksoftirqd/320:20:273
134491620,4ptp4l0-21swapper/020:50:190
89042610,5sleep10-21swapper/119:10:021
900299602,56cyclictest0-21swapper/221:55:292
134491600,4ptp4l20857-21users23:00:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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