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2026-02-11 - 16:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Feb 11, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2143521520,7sleep1155299cyclictest11:20:211
282262750,1sleep328227-21/usr/sbin/munin11:35:163
134691690,1getstats13020-1kworker/2:0H10:30:292
134491680,23ptp4l4867-21cut08:25:180
155499660,3cyclictest17962-21cat07:45:113
134491650,3ptp4l0-21swapper/007:25:280
134491610,3ptp4l0-21swapper/009:40:190
134491590,4ptp4l0-21swapper/008:50:240
134491590,3ptp4l0-21swapper/111:30:071
324652580,3sleep10-21swapper/107:05:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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