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2026-02-14 - 00:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Feb 13, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1824421750,5sleep10-21swapper/107:05:141
20126997217,12cyclictest29834-21chrt10:56:222
20126997016,10cyclictest5373-21seq12:22:212
20125996733,8cyclictest25-21ksoftirqd/111:20:001
20126996619,13cyclictest16077-21cat09:20:012
20125996631,9cyclictest25-21ksoftirqd/107:40:001
20125996629,7cyclictest25-21ksoftirqd/112:30:171
20125996433,4cyclictest25-21ksoftirqd/112:15:001
20125996421,4cyclictest25-21ksoftirqd/108:52:561
20125996227,10cyclictest25-21ksoftirqd/107:25:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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