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2026-02-20 - 18:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Feb 20, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491770,30ptp4l29400-21mailstats07:05:232
30407997212,19cyclictest21396-21latency_hist08:00:001
134491700,5ptp4l0-21swapper/110:19:591
3040799671,27cyclictest2318-21gnome-shell11:15:591
3040799670,23cyclictest11082-21phc2sys-jitter07:35:231
3040799660,29cyclictest7679-21df_inode07:30:141
3040799660,24cyclictest22282-21cut08:00:191
134491610,6ptp4l6000-21/usr/sbin/munin09:45:122
134491610,5ptp4l0-21swapper/210:30:202
3040799600,21cyclictest6581-21timerandwakeup07:25:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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