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2026-08-03 - 23:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Aug 03, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1128599791,75cyclictest0-21swapper/210:05:292
145912650,3sleep114597-21irqrtprio08:25:181
46198640,2rtkit-daemon460-21rtkit-daemon09:43:561
268262620,7sleep11128499cyclictest10:00:231
134491600,16ptp4l0-21swapper/008:45:260
134491600,10ptp4l0-21swapper/108:20:021
140932580,5sleep00-21swapper/008:25:140
134491580,4ptp4l0-21swapper/009:35:230
134491580,4ptp4l0-21swapper/009:00:250
134491570,4ptp4l0-21swapper/312:25:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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