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2025-11-21 - 21:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Nov 21, 2025 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2569221310,2sleep0842999cyclictest07:45:170
2847191680,4ptp4l0-21swapper/208:05:092
268172670,7sleep2843199cyclictest11:15:202
2847191600,4ptp4l0-21swapper/311:24:393
2847191600,3ptp4l3340-21iostat_ios11:35:181
2847191600,3ptp4l14671-21ntp_states08:30:241
2847191600,3ptp4l0-21swapper/012:05:250
2847191590,4ptp4l0-21swapper/012:12:110
2847191590,4ptp4l0-21swapper/012:12:110
2847191590,3ptp4l17007-21hddtemp_smartct10:55:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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