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2026-03-05 - 16:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Mar 05, 2026 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
152921630,6sleep12637699cyclictest10:55:001
134491710,28ptp4l15069-21awk12:30:272
134491670,4ptp4l24947-21df_inode09:25:151
134491670,3ptp4l0-21swapper/111:30:241
26378996230,6cyclictest41-21ksoftirqd/308:40:153
26378996228,4cyclictest41-21ksoftirqd/308:00:123
134491620,19ptp4l20784-21hddtemp_smartct11:35:171
2637899617,12cyclictest0-21swapper/309:41:003
26378996025,6cyclictest41-21ksoftirqd/307:20:213
134491600,3ptp4l6638-21df_inode11:05:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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