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2026-05-28 - 04:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 28, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299462800,5sleep00-21swapper/021:15:260
55432690,5sleep00-21swapper/022:45:000
2596996728,4cyclictest41-21ksoftirqd/321:55:013
259699632,42cyclictest0-21swapper/322:15:273
2595996233,4cyclictest33-21ksoftirqd/222:07:592
2596996016,9cyclictest41-21ksoftirqd/321:40:003
165552600,3sleep216559-21cpuspeed19:40:122
259699592,34cyclictest0-21swapper/321:57:483
2595995927,3cyclictest33-21ksoftirqd/223:30:262
134491590,4ptp4l0-21swapper/222:00:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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