You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-28 - 14:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 28, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
258122680,4sleep30-21swapper/322:45:213
134491650,23ptp4l20540-21/usr/sbin/munin23:45:102
298442640,5sleep125-21ksoftirqd/122:55:141
134491630,4ptp4l0-21swapper/220:15:272
134491600,4ptp4l0-21swapper/321:37:113
134491590,4ptp4l0-21swapper/222:57:452
134491590,4ptp4l0-21swapper/222:19:282
134491590,4ptp4l0-21swapper/121:40:131
2147699587,5cyclictest25-21ksoftirqd/100:20:011
134491580,3ptp4l0-21swapper/221:27:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional