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2026-01-17 - 23:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jan 17, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1378221670,4sleep2487899cyclictest09:45:302
313521500,8sleep00-21swapper/007:05:170
1745821500,7sleep0487699cyclictest09:55:180
168582690,4sleep20-21swapper/211:05:002
4878996433,3cyclictest33-21ksoftirqd/210:50:132
134491630,3ptp4l0-21swapper/108:00:141
4878996128,5cyclictest33-21ksoftirqd/210:55:132
4878996127,6cyclictest33-21ksoftirqd/211:30:142
4878996127,6cyclictest33-21ksoftirqd/208:10:282
4878996127,4cyclictest33-21ksoftirqd/209:14:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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