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2026-05-29 - 21:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri May 29, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6086998424,14cyclictest33-21ksoftirqd/208:45:132
6084998335,4cyclictest9-21ksoftirqd/011:53:030
134491830,4ptp4l0-21swapper/111:52:411
608699754,4cyclictest448-21dbus-daemon11:52:412
6086997530,15cyclictest33-21ksoftirqd/211:40:002
6086997530,15cyclictest33-21ksoftirqd/211:39:592
6086997238,4cyclictest33-21ksoftirqd/210:18:252
6086996930,10cyclictest33-21ksoftirqd/209:20:182
6087996633,8cyclictest41-21ksoftirqd/307:55:003
6086996628,4cyclictest33-21ksoftirqd/207:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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