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2026-01-14 - 02:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jan 13, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3008099842,2cyclictest0-21swapper/310:50:273
3008099762,2cyclictest0-21swapper/307:10:203
3007999640,19cyclictest23321-21phc2sys09:15:222
134491640,3ptp4l0-21swapper/007:30:060
3007999633,58cyclictest0-21swapper/210:30:092
3008099590,18cyclictest134491ptp4l08:40:273
134491590,4ptp4l0-21swapper/010:40:280
134491590,4ptp4l0-21swapper/010:40:280
3007999582,15cyclictest0-21swapper/208:20:222
3007999582,15cyclictest0-21swapper/208:20:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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