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2026-07-29 - 01:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jul 28, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
510021630,3sleep20-21swapper/209:30:182
2409121530,7sleep1358799cyclictest11:20:221
567021510,5sleep1358799cyclictest08:20:251
3589998014,64cyclictest0-21swapper/310:35:483
3589997114,55cyclictest0-21swapper/309:55:493
134491680,4ptp4l2988-21taskset07:06:081
358999673,62cyclictest0-21swapper/312:32:303
358999638,53cyclictest0-21swapper/309:54:293
134491590,3ptp4l0-21swapper/210:11:222
134491580,5ptp4l0-21swapper/008:35:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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