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2026-05-12 - 04:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue May 12, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
820921480,5sleep12699299cyclictest23:05:201
134491700,7ptp4l33-21ksoftirqd/222:15:132
137402660,6sleep00-21swapper/000:25:260
137402660,6sleep00-21swapper/000:25:260
134491660,4ptp4l32093-21ls23:55:281
2699499616,11cyclictest32065-21df_abs19:20:133
134491600,3ptp4l19639-21timerwakeupswit20:00:272
134491600,10ptp4l0-21swapper/100:00:331
134491570,4ptp4l0-21swapper/100:09:381
134491570,3ptp4l0-21swapper/123:30:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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