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2026-04-26 - 15:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Apr 26, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1476221590,7sleep11520499cyclictest10:35:241
3000721240,4sleep31520699cyclictest07:40:223
15204996822,6cyclictest25-21ksoftirqd/111:20:001
15204996722,6cyclictest25-21ksoftirqd/108:50:011
15204996722,6cyclictest25-21ksoftirqd/108:50:011
15204996532,7cyclictest25-21ksoftirqd/110:55:261
15204996531,7cyclictest25-21ksoftirqd/108:00:191
15205996422,10cyclictest33-21ksoftirqd/211:45:252
15205996416,5cyclictest33-21ksoftirqd/209:50:002
15205996416,5cyclictest33-21ksoftirqd/209:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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