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2026-08-24 - 18:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Aug 24, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1410721760,2sleep01186399cyclictest09:30:280
1186499710,27cyclictest21462-21chrt09:47:541
1186499690,30cyclictest21912-21tr08:40:131
1186499690,27cyclictest29950-21timerwakeupswit07:45:281
1186499690,27cyclictest23963-21seq11:00:431
1186499690,25cyclictest27705-21ls07:40:251
1186499681,22cyclictest6955-21cat11:35:201
323272670,6sleep31186699cyclictest12:30:193
1186499670,29cyclictest14949-21chrt11:53:591
1186499670,28cyclictest17145-21taskset10:46:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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