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2026-08-28 - 11:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Aug 28, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1378917668,3phc2sys0-21swapper/319:09:593
78252660,4sleep00-21swapper/022:05:160
134491650,4ptp4l5122-21chrt23:06:191
23473996430,5cyclictest33-21ksoftirqd/222:45:132
23471996432,4cyclictest9-21ksoftirqd/023:00:150
134491620,19ptp4l0-21swapper/323:30:143
23473996024,5cyclictest33-21ksoftirqd/223:55:162
134491600,4ptp4l0-21swapper/000:21:100
134491600,3ptp4l20269-21meminfo22:30:203
23473995927,3cyclictest33-21ksoftirqd/222:35:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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