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2026-06-10 - 23:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jun 10, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1103621530,7sleep03066499cyclictest11:05:160
3066699747,21cyclictest3302-21date10:50:012
30665996824,4cyclictest25-21ksoftirqd/109:20:231
30665996628,10cyclictest25-21ksoftirqd/109:05:001
240052650,5sleep20-21swapper/208:05:132
3066699642,29cyclictest12489-21taskset12:16:272
30665996432,3cyclictest25-21ksoftirqd/111:25:001
30664996420,4cyclictest9-21ksoftirqd/012:20:010
30665996333,4cyclictest25-21ksoftirqd/110:10:191
30665996331,4cyclictest25-21ksoftirqd/109:05:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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