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2026-08-15 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Aug 15, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491670,3ptp4l21251-21/usr/sbin/munin20:10:280
134491600,4ptp4l0-21swapper/220:27:422
134491600,3ptp4l0-21swapper/223:09:562
134491580,5ptp4l0-21swapper/119:09:141
134491580,4ptp4l0-21swapper/120:25:161
134491580,4ptp4l0-21swapper/120:05:151
134491580,4ptp4l0-21swapper/023:45:150
134491580,3ptp4l0-21swapper/100:39:521
134491570,4ptp4l0-21swapper/222:50:042
134491550,3ptp4l0-21swapper/221:38:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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