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2026-02-16 - 16:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 16, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2234722480,4sleep322345-21od07:09:383
436221870,5sleep04360-21tee07:08:550
1863521850,4sleep2311rcuc/207:08:082
2619121840,7sleep126182-21sh07:07:471
1022399822,78cyclictest21633-21kworker/1:110:15:091
10932730,4sleep21099-21od07:12:532
1022399728,62cyclictest21633-21kworker/1:108:50:491
10225996930,8cyclictest41-21ksoftirqd/307:10:393
134491670,15ptp4l0-21swapper/208:24:092
10225996731,8cyclictest41-21ksoftirqd/311:50:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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