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2026-01-21 - 07:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jan 21, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31626997320,5cyclictest33-21ksoftirqd/221:25:002
31625997134,8cyclictest25-21ksoftirqd/122:55:011
31624997130,8cyclictest9-21ksoftirqd/023:35:000
31625997034,5cyclictest25-21ksoftirqd/120:14:591
31625996837,9cyclictest25-21ksoftirqd/123:10:011
31625996633,7cyclictest25-21ksoftirqd/119:55:141
31625996630,8cyclictest25-21ksoftirqd/123:40:141
31625996630,8cyclictest25-21ksoftirqd/121:20:161
31625996630,8cyclictest25-21ksoftirqd/119:15:001
31626996412,8cyclictest33-21ksoftirqd/221:10:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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