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2026-01-07 - 13:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jan 07, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11255996711,54cyclictest10249-21kworker/1:121:05:491
134491660,24ptp4l18619-21grep19:25:162
11254996232,6cyclictest9-21ksoftirqd/022:41:200
11255996114,45cyclictest23545-21kworker/1:100:15:481
134491600,5ptp4l0-21swapper/121:30:171
134491600,4ptp4l0-21swapper/121:15:201
134491600,4ptp4l0-21swapper/119:05:201
296222590,3sleep129628-21latency23:15:191
134491590,4ptp4l0-21swapper/200:25:042
134491580,5ptp4l0-21swapper/323:27:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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