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2026-07-13 - 01:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jul 12, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1798021580,6sleep12867299cyclictest12:34:521
28673997034,6cyclictest33-21ksoftirqd/207:45:002
28673996933,5cyclictest33-21ksoftirqd/212:35:012
28673996834,4cyclictest33-21ksoftirqd/210:50:002
28673996720,5cyclictest33-21ksoftirqd/209:10:012
28673996629,9cyclictest33-21ksoftirqd/210:44:102
28673996331,6cyclictest33-21ksoftirqd/210:35:212
28673996327,8cyclictest33-21ksoftirqd/211:03:432
28672996333,3cyclictest25-21ksoftirqd/109:35:181
28673996232,7cyclictest33-21ksoftirqd/209:22:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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