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2026-01-16 - 08:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jan 16, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
787221540,3sleep01086499cyclictest21:20:230
10866996659,5cyclictest0-21swapper/200:33:242
48712650,5sleep24875-21hwlatdetect21:15:162
134491610,27ptp4l9-21ksoftirqd/000:35:270
10866996154,5cyclictest0-21swapper/200:15:132
134491590,4ptp4l0-21swapper/322:40:103
134491590,4ptp4l0-21swapper/322:08:213
1086699598,7cyclictest0-21swapper/222:50:162
1086699598,6cyclictest0-21swapper/220:35:252
134491580,3ptp4l0-21swapper/223:25:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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