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2026-05-21 - 17:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu May 21, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245742760,3sleep30-21swapper/312:10:003
1440499740,3cyclictest14191-21phc2sys10:35:240
14406997034,6cyclictest33-21ksoftirqd/207:20:002
92332670,6sleep30-21swapper/309:15:263
14406996733,7cyclictest33-21ksoftirqd/208:50:002
14406996635,5cyclictest33-21ksoftirqd/211:15:212
14406996634,4cyclictest33-21ksoftirqd/208:35:132
14406996531,4cyclictest33-21ksoftirqd/211:05:152
14406996529,6cyclictest33-21ksoftirqd/208:30:002
14406996432,6cyclictest33-21ksoftirqd/211:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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