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2026-08-30 - 03:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 30, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
639821410,3sleep1508599cyclictest22:40:171
508699687,59cyclictest0-21swapper/222:10:292
134491680,4ptp4l0-21swapper/119:40:131
508799618,11cyclictest30533-21taskset21:14:433
508699602,7cyclictest19256-21sendmail21:59:592
134491590,4ptp4l0-21swapper/219:40:192
134491590,4ptp4l0-21swapper/219:08:132
134491590,3ptp4l0-21swapper/121:57:061
508799589,10cyclictest9436-21taskset19:19:423
508799580,17cyclictest19903-21hddtemp_smartct22:00:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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