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2026-02-17 - 16:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 17, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1314421470,5sleep12930799cyclictest08:50:261
485021400,5sleep22930899cyclictest08:35:162
2165621380,4sleep02930699cyclictest08:00:200
2930899762,2cyclictest0-21swapper/209:35:292
29309996635,6cyclictest41-21ksoftirqd/312:20:003
29309996633,3cyclictest41-21ksoftirqd/311:20:013
29309996632,8cyclictest41-21ksoftirqd/312:20:133
134491650,4ptp4l0-21swapper/011:30:280
134491650,2ptp4l0-21swapper/112:30:231
29309996431,6cyclictest41-21ksoftirqd/309:50:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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