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2025-11-24 - 22:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Nov 24, 2025 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2125821520,6sleep22797399cyclictest10:20:222
252092700,6sleep02797199cyclictest11:40:140
2847191680,3ptp4l0-21swapper/209:30:202
2847191640,5ptp4l0-21swapper/210:50:122
183852630,2sleep218390-21needreboot09:05:242
2797499626,18cyclictest2847191ptp4l10:00:203
2797499626,18cyclictest2847191ptp4l10:00:203
2847191610,5ptp4l0-21swapper/107:06:171
2847191610,4ptp4l0-21swapper/208:28:372
2847191610,4ptp4l0-21swapper/012:35:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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