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2025-11-17 - 16:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Nov 17, 2025 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
835121200,6sleep21461999cyclictest22:20:262
2847191830,16ptp4l0-21swapper/020:40:330
26392640,4sleep10-21swapper/123:20:141
2847191620,4ptp4l0-21swapper/219:15:292
2847191610,5ptp4l0-21swapper/200:30:172
2847191600,4ptp4l0-21swapper/322:50:173
2847191590,9ptp4l0-21swapper/220:49:212
2847191590,4ptp4l18832-21apt-get23:55:152
2847191590,3ptp4l0-21swapper/321:39:163
2847191580,4ptp4l0-21swapper/322:07:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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