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2025-08-21 - 21:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Aug 21, 2025 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84892720,5sleep0313499cyclictest10:50:000
84892720,5sleep0313499cyclictest10:50:000
9852680,5sleep00-21swapper/008:15:150
2847191680,31ptp4l25-21ksoftirqd/109:35:011
2847191680,31ptp4l25-21ksoftirqd/109:35:011
3135996727,9cyclictest25-21ksoftirqd/112:30:291
2847191670,4ptp4l20429-21dump-pmu-power12:25:000
313799661,25cyclictest7931-21cpuspeed_turbos07:20:143
313799661,25cyclictest7931-21cpuspeed_turbos07:20:143
3135996630,10cyclictest25-21ksoftirqd/110:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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