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2026-04-15 - 20:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Apr 15, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1605721830,5sleep016059-21sh07:08:380
2497321810,5sleep224977-21sort07:09:452
708221640,3sleep30-21swapper/307:09:023
319512940,3sleep231908-21sh07:13:582
110322850,3sleep311040-21sort07:13:303
126282730,5sleep112625-21sort07:13:321
165122620,5sleep10-21swapper/111:00:271
134491620,4ptp4l8492-21timerandwakeup07:15:251
134491590,4ptp4l14527-21cat09:50:011
134491590,4ptp4l0-21swapper/110:20:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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