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2026-02-27 - 18:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Feb 27, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18931996733,3cyclictest25-21ksoftirqd/109:00:001
134491620,5ptp4l0-21swapper/309:45:193
18931996132,8cyclictest25-21ksoftirqd/108:10:191
134491600,4ptp4l0-21swapper/011:25:180
18931995928,3cyclictest25-21ksoftirqd/111:50:181
18931995927,7cyclictest25-21ksoftirqd/108:55:001
134491590,4ptp4l0-21swapper/209:20:122
134491590,4ptp4l0-21swapper/111:35:171
134491590,3ptp4l121rcu_preempt11:45:143
134491590,25ptp4l9-21ksoftirqd/008:50:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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