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2026-01-24 - 07:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jan 24, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1344911010,4ptp4l0-21swapper/223:42:572
134491700,4ptp4l0-21swapper/021:20:280
134491650,22ptp4l0-21swapper/323:05:433
134491630,4ptp4l0-21swapper/123:25:271
183342620,4sleep00-21swapper/019:40:210
134491620,19ptp4l16697-21iostat_ios23:05:170
134491600,5ptp4l25415-21ls23:25:130
134491600,4ptp4l0-21swapper/021:30:520
134491600,3ptp4l0-21swapper/223:50:262
134491600,3ptp4l0-21swapper/023:20:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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