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2026-07-23 - 14:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 23, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1223221470,3sleep3732599cyclictest19:20:133
1223221470,3sleep3732599cyclictest19:20:133
134491660,5ptp4l0-21swapper/022:45:200
7325996427,9cyclictest41-21ksoftirqd/323:40:443
7323996424,4cyclictest25-21ksoftirqd/123:50:211
7325996332,3cyclictest41-21ksoftirqd/300:00:003
7325996328,8cyclictest41-21ksoftirqd/322:46:083
7323996229,8cyclictest25-21ksoftirqd/119:10:241
7323996229,4cyclictest25-21ksoftirqd/121:35:161
134491620,4ptp4l0-21swapper/020:40:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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