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2026-06-10 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 09, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41032700,3sleep24107-21cpuspeed_turbos11:20:142
134491650,5ptp4l0-21swapper/109:25:171
202002640,4sleep220204-21fschecks_time09:35:162
134491640,5ptp4l0-21swapper/112:00:211
134491600,4ptp4l0-21swapper/109:00:251
1650999599,22cyclictest27319-21unixbench_multi07:30:272
134491590,4ptp4l0-21swapper/107:30:271
1650999582,21cyclictest0-21swapper/211:25:292
134491580,4ptp4l0-21swapper/108:00:291
134491580,4ptp4l0-21swapper/107:41:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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