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2026-09-01 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Sep 01, 2026 12:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491640,4ptp4l0-21swapper/109:20:401
134491640,4ptp4l0-21swapper/109:20:401
134782630,6sleep30-21swapper/311:40:003
134491600,3ptp4l24629-21grep07:25:151
134491600,10ptp4l0-21swapper/207:34:552
134491580,4ptp4l0-21swapper/110:15:161
134491580,4ptp4l0-21swapper/109:55:241
134491580,3ptp4l0-21swapper/209:50:012
134491580,3ptp4l0-21swapper/007:50:310
134491570,4ptp4l0-21swapper/109:40:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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