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2026-09-23 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Sep 22, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491730,4ptp4l0-21swapper/107:09:141
31440997014,11cyclictest1317-21runrttasks09:44:330
31440996913,11cyclictest7181-21ntpq07:25:220
31440996911,16cyclictest1293-21sed07:15:010
31440996911,16cyclictest1276-21cat11:50:230
31440996811,18cyclictest1301-21snmpd11:08:020
31440996711,15cyclictest29077-21cat10:30:230
31440996514,11cyclictest18711-21taskset12:28:400
31440996513,10cyclictest1317-21runrttasks10:02:060
134491650,5ptp4l12612-21sed09:55:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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