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2026-01-15 - 03:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jan 14, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2628421760,7sleep00-21swapper/007:05:240
134491700,3ptp4l15994-21iostat_ios11:25:180
134491670,5ptp4l0-21swapper/008:25:120
134491650,3ptp4l6522-21iostat_ios09:55:170
134491640,3ptp4l22411-21diskstats10:30:140
80162620,6sleep38001-21cron10:00:003
134491620,4ptp4l15522-21users07:50:370
134491610,4ptp4l28347-21ntpq07:10:230
134491610,4ptp4l23063-21apt-get08:10:120
134491610,4ptp4l0-21swapper/109:20:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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