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2026-08-24 - 05:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Aug 24, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126521690,7sleep12315499cyclictest23:00:161
23154997033,8cyclictest25-21ksoftirqd/100:10:001
23153997023,6cyclictest9-21ksoftirqd/022:45:200
23154996732,4cyclictest25-21ksoftirqd/100:15:001
23154996731,4cyclictest25-21ksoftirqd/122:50:011
215292660,8sleep1231rcuc/120:15:171
215292660,8sleep1231rcuc/120:15:161
23154996531,5cyclictest25-21ksoftirqd/120:00:141
23153996532,4cyclictest9-21ksoftirqd/023:30:000
23153996530,4cyclictest9-21ksoftirqd/022:55:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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