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2026-06-09 - 13:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 09, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48072690,5sleep30-21swapper/319:05:283
134491600,6ptp4l33-21ksoftirqd/223:10:252
134491600,5ptp4l25115-21ps21:00:173
134491600,4ptp4l0-21swapper/221:20:592
134491600,19ptp4l11300-21sed20:30:181
134491600,16ptp4l0-21swapper/221:50:272
134491580,4ptp4l0-21swapper/222:25:072
134491580,19ptp4l25-21ksoftirqd/119:49:141
134491570,9ptp4l0-21swapper/221:15:422
134491570,5ptp4l0-21swapper/200:10:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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