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2026-07-10 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jul 10, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308642750,5sleep10-21swapper/107:05:261
31695997411,61cyclictest0-21swapper/211:15:282
31694996912,16cyclictest24566-21chrt10:21:401
3169599680,6cyclictest29528-21turbostat09:25:002
31694996713,16cyclictest22355-21chrt11:25:511
31694996513,10cyclictest29396-21chrt11:42:351
31695996433,4cyclictest33-21ksoftirqd/208:35:242
31695996430,7cyclictest33-21ksoftirqd/209:00:282
31694996413,10cyclictest29117-21chrt10:31:071
31694996412,16cyclictest1491-21chrt09:32:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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