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2026-08-22 - 02:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Aug 21, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6807996637,3cyclictest41-21ksoftirqd/308:28:553
6807996634,7cyclictest41-21ksoftirqd/310:45:243
6807996633,4cyclictest41-21ksoftirqd/311:47:213
6807996533,8cyclictest41-21ksoftirqd/307:40:223
6807996533,4cyclictest41-21ksoftirqd/307:55:013
6807996533,4cyclictest41-21ksoftirqd/307:55:013
6807996532,7cyclictest41-21ksoftirqd/309:50:013
6807996530,4cyclictest41-21ksoftirqd/311:18:003
6807996529,8cyclictest41-21ksoftirqd/309:10:173
6807996432,7cyclictest41-21ksoftirqd/308:30:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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