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2026-04-18 - 03:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Apr 18, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
514899730,31cyclictest31417-21cat22:25:002
514799711,68cyclictest22266-21kworker/1:119:48:481
514899700,27cyclictest32612-1kworker/2:1H19:20:002
130492680,5sleep20-21swapper/220:35:182
5146996325,4cyclictest9-21ksoftirqd/023:00:240
41272620,3sleep20-21swapper/219:05:232
229272620,4sleep30-21swapper/323:15:123
229272620,4sleep30-21swapper/323:15:123
5146996157,2cyclictest111rcuc/021:10:240
5146996131,5cyclictest9-21ksoftirqd/019:10:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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