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2026-03-04 - 15:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Mar 04, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2751122040,5sleep20-21swapper/207:05:252
443321770,5sleep12822699cyclictest12:05:191
844521710,6sleep12822699cyclictest12:15:131
844521710,6sleep12822699cyclictest12:15:131
2822699741,3cyclictest9287-21/usr/sbin/munin09:55:241
134491670,25ptp4l1016-21iostat07:20:153
2822699660,62cyclictest15551-21meminfo07:50:201
2822699620,3cyclictest30109-21/usr/sbin/munin10:40:261
134491620,4ptp4l10277-21apt-get11:10:123
134491610,4ptp4l0-21swapper/008:15:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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