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2026-06-03 - 05:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jun 03, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24027997415,12cyclictest3332-21chrt00:21:082
24027997315,12cyclictest26526-21chrt00:04:272
24027997216,11cyclictest10014-21chrt23:27:162
24027997115,12cyclictest14661-21taskset23:37:522
24027997115,11cyclictest12043-21chrt21:10:382
24027997115,10cyclictest21556-21taskset21:34:272
24027997114,11cyclictest5569-21taskset23:19:182
24027997016,11cyclictest5085-21taskset20:58:252
24027997015,12cyclictest14676-21chrt21:19:522
24027997015,11cyclictest9380-21chrt19:58:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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