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2026-02-15 - 19:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Feb 15, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2890121640,5sleep12718199cyclictest07:10:301
27183997713,62cyclictest0-21swapper/310:51:093
134491640,5ptp4l0-21swapper/010:25:210
134491640,3ptp4l1799migration/008:35:170
134491640,3ptp4l0-21swapper/211:58:052
134491620,4ptp4l0-21swapper/110:55:281
134491610,4ptp4l0-21swapper/007:45:200
309332600,5sleep20-21swapper/210:45:002
134491600,4ptp4l0-21swapper/212:05:232
134491600,3ptp4l212-21systemd-journal07:55:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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