You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-26 - 13:36
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jul 26, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1279321430,5sleep02277099cyclictest00:35:180
134491870,5ptp4l0-21swapper/023:20:240
22772996813,52cyclictest22621-21unixbench_singl22:35:292
46582610,4sleep10-21swapper/119:40:291
134491610,4ptp4l0-21swapper/020:10:180
134491600,3ptp4l0-21swapper/222:50:142
134491590,4ptp4l0-21swapper/322:20:153
134491590,3ptp4l0-21swapper/221:18:442
134491580,4ptp4l0-21swapper/322:25:273
134491580,4ptp4l0-21swapper/023:10:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional