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2026-08-01 - 19:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Aug 01, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1135521510,6sleep01205099cyclictest08:15:210
134491760,7ptp4l0-21swapper/107:05:211
134491740,4ptp4l0-21swapper/108:10:271
134491610,5ptp4l0-21swapper/112:00:181
134491590,4ptp4l0-21swapper/107:45:201
134491580,4ptp4l0-21swapper/107:50:191
134491570,5ptp4l0-21swapper/111:50:261
134491570,4ptp4l0-21swapper/207:20:032
134491570,4ptp4l0-21swapper/010:20:240
134491560,5ptp4l0-21swapper/111:00:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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