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2026-08-14 - 05:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Aug 14, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2838421370,3sleep01729599cyclictest21:50:310
134491750,3ptp4l0-21swapper/019:20:170
17296997131,4cyclictest25-21ksoftirqd/122:10:171
17296996727,8cyclictest25-21ksoftirqd/121:45:291
1729899666,15cyclictest30198-21/usr/sbin/munin00:15:163
1729899666,10cyclictest20727-21sed21:35:203
1729899666,10cyclictest20727-21sed21:35:203
17296996528,7cyclictest25-21ksoftirqd/100:15:211
1729899649,10cyclictest26672-21latency_hist20:40:003
17298996410,10cyclictest17336-21sed20:20:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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