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2026-08-29 - 15:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Aug 29, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
252021640,4sleep22483299cyclictest21:50:132
280582790,5sleep233-21ksoftirqd/222:45:172
134491750,5ptp4l2483399cyclictest21:35:283
2483299651,62cyclictest0-21swapper/223:25:292
134491610,7ptp4l0-21swapper/319:05:223
134491610,4ptp4l0-21swapper/100:10:131
134491600,4ptp4l0-21swapper/222:25:592
134491600,3ptp4l14186-21acpi23:25:121
134491590,4ptp4l0-21swapper/219:39:282
134491590,4ptp4l0-21swapper/219:39:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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