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2026-02-15 - 01:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 14, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3171121890,4sleep30-21swapper/307:05:133
134491680,4ptp4l0-21swapper/208:10:202
134491660,5ptp4l0-21swapper/307:45:003
134491650,3ptp4l3583-21runrttasks07:13:483
154199635,17cyclictest9271-21df_abs08:35:150
154199623,16cyclictest4687-21df_inode08:25:140
134491620,3ptp4l0-21swapper/210:37:182
134491620,16ptp4l7832-21ls07:20:253
134491590,4ptp4l0-21swapper/211:50:202
134491590,4ptp4l0-21swapper/208:57:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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