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2026-02-27 - 06:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Feb 27, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
210882760,4sleep20-21swapper/223:45:152
134491750,4ptp4l2318-21gnome-shell23:36:591
22130997231,4cyclictest33-21ksoftirqd/220:05:182
2213199695,62cyclictest0-21swapper/321:25:273
22130996829,3cyclictest33-21ksoftirqd/219:55:002
22131996712,51cyclictest1003-21chrt20:41:073
22131996710,11cyclictest27906-21grep22:50:123
22130996732,7cyclictest33-21ksoftirqd/221:20:272
2213199668,12cyclictest22140-21sed22:35:283
2213199668,12cyclictest22140-21sed22:35:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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