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2026-07-02 - 21:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 02, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1781421330,3sleep2943699cyclictest09:45:242
145382730,5sleep10-21swapper/109:40:141
251212720,4sleep3401ktimersoftd/310:00:253
134491660,4ptp4l0-21swapper/109:53:381
134491650,3ptp4l0-21swapper/011:00:010
9435996435,4cyclictest25-21ksoftirqd/109:20:231
134491640,24ptp4l10724-21irqrtprio10:40:192
9435996328,4cyclictest25-21ksoftirqd/112:20:221
134491630,4ptp4l0-21swapper/311:05:013
9437996125,4cyclictest41-21ksoftirqd/308:17:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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