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2026-04-12 - 17:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Apr 12, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491620,3ptp4l28850-21/usr/sbin/munin11:10:203
134491610,4ptp4l0-21swapper/012:15:030
134491600,4ptp4l0-21swapper/107:55:231
134491590,5ptp4l25161-21ps08:40:240
134491590,19ptp4l0-21swapper/008:55:210
134491580,4ptp4l0-21swapper/211:47:402
134491580,3ptp4l8560-21memory08:05:210
134491580,2ptp4l0-21swapper/009:55:290
134491570,5ptp4l0-21swapper/207:07:192
134491560,3ptp4l0-21swapper/108:50:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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