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2026-01-11 - 08:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jan 11, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34521520,5sleep31030699cyclictest22:15:183
3050321380,4sleep11030499cyclictest23:20:151
188362620,3sleep318840-21cpuspeed_turbos00:05:143
134491590,4ptp4l0-21swapper/220:25:142
134491590,3ptp4l28715-21/usr/sbin/munin20:55:241
134491590,3ptp4l0-21swapper/223:15:062
134491580,5ptp4l0-21swapper/219:24:412
134491580,4ptp4l0-21swapper/322:05:213
134491570,3ptp4l7182-21ls20:10:232
134491570,3ptp4l0-21swapper/222:00:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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