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2026-09-10 - 16:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 10, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491740,6ptp4l0-21swapper/009:55:130
134491680,3ptp4l26733-21/usr/sbin/munin11:20:270
134491670,2ptp4l121rcu_preempt11:30:192
580799661,2cyclictest0-21swapper/212:35:282
580799661,2cyclictest0-21swapper/212:35:282
134491640,4ptp4l0-21swapper/310:35:523
134491580,21ptp4l0-21swapper/311:02:563
580799571,54cyclictest0-21swapper/208:55:292
134491560,3ptp4l0-21swapper/208:44:592
134491550,3ptp4l0-21swapper/208:22:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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