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2026-09-17 - 22:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 17, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491680,4ptp4l0-21swapper/209:47:032
134491660,25ptp4l12786-21ls10:05:283
134491600,4ptp4l18336-21diskstats09:10:152
134491590,4ptp4l0-21swapper/208:05:132
134491590,4ptp4l0-21swapper/012:20:180
134491580,5ptp4l2213-21iostat_ios08:35:182
134491580,4ptp4l16826-21awk11:20:281
134491580,4ptp4l0-21swapper/309:55:013
134491580,3ptp4l0-21swapper/312:32:413
134491580,3ptp4l0-21swapper/309:35:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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