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2026-02-10 - 06:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 10, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491760,32ptp4l28950-21apt-get19:05:131
134491720,24ptp4l9034-21ps21:50:190
132932710,4sleep30-21swapper/322:00:143
134491670,4ptp4l9530-21apt-get00:10:130
31288996430,6cyclictest41-21ksoftirqd/320:37:123
31288996425,8cyclictest41-21ksoftirqd/320:20:003
31288996425,8cyclictest41-21ksoftirqd/320:20:003
31288996331,4cyclictest41-21ksoftirqd/321:35:153
31288996331,4cyclictest41-21ksoftirqd/319:30:003
31288996329,8cyclictest41-21ksoftirqd/320:45:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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