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2026-08-06 - 15:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Aug 06, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491630,11ptp4l0-21swapper/223:59:542
134491610,4ptp4l0-21swapper/122:20:551
134491590,4ptp4l0-21swapper/021:35:170
134491590,19ptp4l11922-21apt23:20:111
134491590,18ptp4l0-21swapper/120:15:151
248512580,4sleep20-21swapper/223:45:222
134491580,4ptp4l0-21swapper/121:45:311
134491570,4ptp4l0-21swapper/121:20:231
134491570,3ptp4l24946-21apt-get21:30:142
134491570,3ptp4l0-21swapper/223:09:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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