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2026-06-14 - 20:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jun 14, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2478621630,3sleep31389799cyclictest08:40:233
1389699771,2cyclictest0-21swapper/210:45:302
1389699771,2cyclictest0-21swapper/210:45:302
1389699702,3cyclictest0-21swapper/210:15:292
1389699701,67cyclictest0-21swapper/211:10:292
280162680,4sleep10-21swapper/109:55:281
1389699622,3cyclictest0-21swapper/209:00:282
134491600,5ptp4l5561-21apt-get11:30:033
134491580,20ptp4l0-21swapper/109:50:201
1389699571,54cyclictest0-21swapper/211:22:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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