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2026-03-28 - 08:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Mar 28, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2248521670,5sleep01487399cyclictest21:45:130
2826121620,3sleep21487599cyclictest00:15:142
1487399712,26cyclictest22281-21sed20:35:150
14873997113,19cyclictest1317-21runrttasks00:36:420
14874996927,8cyclictest25-21ksoftirqd/100:37:431
1487399686,22cyclictest26335-21timerandwakeup23:00:260
14874996635,3cyclictest25-21ksoftirqd/123:20:011
134491660,4ptp4l0-21swapper/119:24:071
14874996435,7cyclictest25-21ksoftirqd/120:25:001
14874996333,8cyclictest25-21ksoftirqd/122:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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