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2026-06-17 - 10:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jun 17, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
963999780,33cyclictest9821-21sshd22:36:322
963999750,35cyclictest11925-21chrt21:31:012
963999750,34cyclictest408-21chrt23:26:072
963999741,34cyclictest19356-21chrt00:08:382
963999741,34cyclictest19356-21chrt00:08:382
963999730,33cyclictest18754-21chrt20:37:012
963999720,36cyclictest31618-21chrt00:35:112
963999720,33cyclictest3268-21chrt23:34:052
963999720,32cyclictest23799-21taskset21:57:172
963999720,32cyclictest16885-21chrt22:53:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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