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2026-08-18 - 21:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Aug 18, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246521580,2sleep23145699cyclictest07:15:212
1330021510,6sleep33145799cyclictest12:15:223
290821370,4sleep33145799cyclictest09:35:243
3145599711,67cyclictest9358-21memory07:30:221
3145599710,29cyclictest1317-21runrttasks12:34:121
3145599710,28cyclictest14098-21chrt12:17:481
3145699682,64cyclictest0-21swapper/210:05:092
3145599671,63cyclictest6773-21diskstats09:45:151
3145599660,29cyclictest3763-21chrt10:46:551
3145599660,29cyclictest10338-21chrt08:40:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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