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2026-07-29 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 29, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134691730,5getstats0-21swapper/319:45:243
22447996634,4cyclictest41-21ksoftirqd/300:00:003
22446996531,3cyclictest33-21ksoftirqd/222:18:162
22446996431,4cyclictest33-21ksoftirqd/222:04:212
22446996430,3cyclictest33-21ksoftirqd/220:24:502
22446996333,4cyclictest33-21ksoftirqd/221:44:232
22446996333,3cyclictest33-21ksoftirqd/200:00:162
22446996328,4cyclictest33-21ksoftirqd/220:09:482
134491620,5ptp4l0-21swapper/323:35:193
134491620,5ptp4l0-21swapper/323:35:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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