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2026-09-03 - 07:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 03, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
868899822,78cyclictest0-21swapper/222:15:292
8688997614,60cyclictest0-21swapper/219:15:292
134491650,4ptp4l0-21swapper/300:30:253
134491650,26ptp4l0-21swapper/019:44:000
868899633,58cyclictest0-21swapper/220:05:292
134491630,4ptp4l0-21swapper/300:17:523
134491610,3ptp4l28328-21ntp_states00:25:253
134491600,4ptp4l0-21swapper/319:42:453
134491590,4ptp4l0-21swapper/219:31:252
134491590,4ptp4l0-21swapper/219:31:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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