You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-14 - 14:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jan 14, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
967221580,6sleep32787599cyclictest19:39:593
2586521360,6sleep12787399cyclictest20:15:001
134491660,4ptp4l9328-21taskset20:45:260
27875996533,3cyclictest41-21ksoftirqd/322:40:173
2787499652,61cyclictest0-21swapper/221:00:282
2787499635,16cyclictest7017-21cat20:40:302
2787499634,10cyclictest212-21systemd-journal22:35:012
2787499626,17cyclictest3250-21grep21:45:142
2787499626,10cyclictest8575-21cut21:55:192
2787499608,11cyclictest12633-21grep20:55:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional