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2026-02-10 - 18:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 10, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1562521510,4sleep02401699cyclictest09:10:170
2401699691,26cyclictest8648-21cpuspeed11:15:130
2401699680,25cyclictest4930-21cut12:15:180
2401699670,31cyclictest26186-21taskset08:23:110
2401699670,31cyclictest21790-21seq09:23:010
2401699670,30cyclictest21859-21seq10:31:090
2401699660,31cyclictest26023-21seq07:14:030
2401699660,30cyclictest4811-21sh08:45:220
2401699660,30cyclictest30477-21seq07:21:580
2401699651,61cyclictest4894-21memory11:05:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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