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2026-01-15 - 09:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jan 15, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1571521750,5sleep12294999cyclictest22:20:171
297802640,5sleep00-21swapper/000:00:170
134491640,4ptp4l0-21swapper/300:15:153
2295099631,16cyclictest0-21swapper/223:30:002
2295099624,15cyclictest212-21systemd-journal22:44:372
2295099624,15cyclictest212-21systemd-journal21:34:222
134491620,5ptp4l25-21ksoftirqd/123:30:161
134491610,3ptp4l0-21swapper/123:15:171
2295099608,9cyclictest8819-21latency_hist00:25:002
2295099603,15cyclictest212-21systemd-journal21:29:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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