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2026-11-15 - 05:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Nov 15, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20912997713,62cyclictest656-21kworker/1:022:43:501
263382660,3sleep126337-21cpuspeed00:00:151
20913996629,3cyclictest33-21ksoftirqd/219:59:592
20913995929,3cyclictest33-21ksoftirqd/220:10:212
134491590,4ptp4l0-21swapper/220:49:572
20913995825,5cyclictest33-21ksoftirqd/220:35:222
20913995825,5cyclictest33-21ksoftirqd/220:35:222
134491580,9ptp4l0-21swapper/219:39:192
134491580,4ptp4l0-21swapper/221:54:102
134491580,4ptp4l0-21swapper/119:16:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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