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2026-03-13 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Mar 13, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1344914760,1ptp4l7076-21ls19:05:210
1344914760,1ptp4l7076-21ls19:05:210
8396997830,6cyclictest25-21ksoftirqd/100:05:001
7842660,3sleep2321ktimersoftd/220:00:252
8396996428,6cyclictest25-21ksoftirqd/100:15:131
8396996329,7cyclictest25-21ksoftirqd/100:30:011
8396996328,4cyclictest25-21ksoftirqd/119:15:251
8395996223,6cyclictest9-21ksoftirqd/020:20:070
8396996133,4cyclictest25-21ksoftirqd/121:17:321
8396996131,4cyclictest25-21ksoftirqd/119:10:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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