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2026-04-16 - 03:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Apr 16, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3047921640,7sleep1704999cyclictest21:10:121
134491670,4ptp4l7649-21iostat_ios19:10:180
134491640,2ptp4l121rcu_preempt23:05:253
134491640,2ptp4l121rcu_preempt23:05:253
134491630,3ptp4l17090-21/usr/sbin/munin00:10:261
134491630,3ptp4l0-21swapper/223:57:232
134491620,4ptp4l0-21swapper/021:25:220
134491620,3ptp4l0-21swapper/123:15:041
134491590,3ptp4l0-21swapper/323:57:143
134491590,3ptp4l0-21swapper/223:35:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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