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2026-06-16 - 09:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 16, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2905121600,6sleep01383299cyclictest19:40:210
2248121410,5sleep30-21swapper/320:35:243
134491640,3ptp4l14626-21/usr/sbin/munin22:40:161
134491630,4ptp4l0-21swapper/220:42:072
122722620,1sleep112274-21sh22:35:011
134491610,3ptp4l7928-21hddtemp_smartct21:15:170
203162600,5sleep10-21swapper/122:50:221
134491600,5ptp4l0-21swapper/020:15:220
134491600,4ptp4l0-21swapper/019:08:180
134491590,4ptp4l0-21swapper/022:10:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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