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2026-05-02 - 13:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat May 02, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
208112740,5sleep10-21swapper/122:15:241
29802997331,8cyclictest41-21ksoftirqd/300:30:003
29802997033,4cyclictest41-21ksoftirqd/300:30:143
134491690,4ptp4l0-21swapper/000:05:260
29802996529,9cyclictest41-21ksoftirqd/321:10:193
29802996329,8cyclictest41-21ksoftirqd/322:45:133
29802996328,4cyclictest41-21ksoftirqd/319:20:123
29802996328,10cyclictest41-21ksoftirqd/319:42:493
134082610,3sleep30-21swapper/323:10:183
134491600,3ptp4l0-21swapper/022:00:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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