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2026-06-02 - 04:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 02, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1852521660,2sleep12669399cyclictest20:00:201
2612921640,6sleep32669599cyclictest20:15:253
2500521640,3sleep32669599cyclictest23:40:253
2641921450,6sleep22669499cyclictest21:25:292
26694998216,63cyclictest32204-21unixbench_singl23:55:292
134491590,4ptp4l0-21swapper/322:25:293
134491590,3ptp4l0-21swapper/319:15:573
134491580,4ptp4l0-21swapper/220:47:162
134491580,4ptp4l0-21swapper/200:17:372
134491570,4ptp4l0-21swapper/222:35:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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