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2026-08-29 - 00:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Aug 28, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
964821840,5sleep3458999cyclictest07:20:163
134491670,7ptp4l0-21swapper/007:05:250
134491660,5ptp4l0-21swapper/207:55:222
4589996410,11cyclictest20853-21chrt11:11:193
134491640,4ptp4l0-21swapper/111:19:001
134491630,3ptp4l31029-21iostat_ios10:25:180
458999628,16cyclictest21406-21grep12:25:133
134491610,4ptp4l0-21swapper/012:10:280
134491600,4ptp4l15741-21cat09:50:261
458999598,8cyclictest29742-21ssh11:30:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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