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2026-04-14 - 21:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Apr 14, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
625621790,2sleep01420499cyclictest11:30:150
137672700,4sleep20-21swapper/209:25:292
134491680,3ptp4l0-21swapper/309:00:153
134491620,3ptp4l22413-21meminfo09:45:213
134491620,3ptp4l0-21swapper/310:25:153
134491590,3ptp4l0-21swapper/109:46:111
134491580,4ptp4l0-21swapper/210:50:232
134491580,4ptp4l0-21swapper/210:50:232
134491580,3ptp4l0-21swapper/109:11:141
134491580,3ptp4l0-21swapper/010:14:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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