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2026-01-20 - 07:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jan 20, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
747821200,5sleep22156399cyclictest22:05:232
747821200,5sleep22156399cyclictest22:05:232
241802650,6sleep20-21swapper/223:50:262
21562996334,7cyclictest25-21ksoftirqd/123:20:011
134491610,4ptp4l0-21swapper/221:51:242
134491610,4ptp4l0-21swapper/022:25:010
21562996029,4cyclictest25-21ksoftirqd/122:30:191
134491600,4ptp4l13161-21iostat20:00:181
21562995925,4cyclictest25-21ksoftirqd/123:35:001
134491590,9ptp4l0-21swapper/222:53:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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