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2026-02-24 - 01:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 23, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1407521610,24sleep23142399cyclictest07:40:192
31423997810,65cyclictest29778-21latency_hist09:25:012
134491610,5ptp4l0-21swapper/307:05:163
134491610,5ptp4l0-21swapper/207:06:262
3142399603,2cyclictest0-21swapper/210:40:162
134491590,3ptp4l0-21swapper/111:20:231
134491580,4ptp4l0-21swapper/307:20:033
134491580,4ptp4l0-21swapper/212:20:212
134491580,3ptp4l0-21swapper/209:50:192
134491580,3ptp4l0-21swapper/011:40:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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