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2026-07-05 - 01:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 04, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
333421770,5sleep10-21swapper/107:05:201
134491670,3ptp4l0-21swapper/007:10:040
134491670,3ptp4l0-21swapper/007:10:040
134491620,4ptp4l13213-21memory10:55:220
134691610,2getstats0-21swapper/011:35:180
480899583,15cyclictest24973-21cat09:00:281
134491580,4ptp4l0-21swapper/209:48:422
134491580,4ptp4l0-21swapper/112:05:211
134491580,4ptp4l0-21swapper/011:19:250
134491580,3ptp4l0-21swapper/310:45:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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