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2026-08-11 - 21:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Aug 11, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491680,9ptp4l0-21swapper/007:54:440
134491660,5ptp4l0-21swapper/009:15:020
1196399658,11cyclictest7962-21sendmail11:40:013
1196199640,33cyclictest23552-21chrt09:52:161
134491610,4ptp4l0-21swapper/008:19:440
1196399617,12cyclictest12454-21taskset11:47:543
134491600,4ptp4l0-21swapper/207:49:382
134491600,3ptp4l1301-21snmpd07:42:052
134491580,4ptp4l0-21swapper/309:50:183
134491580,4ptp4l0-21swapper/011:23:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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