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2026-06-10 - 09:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jun 10, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
97852820,5sleep00-21swapper/020:30:210
134491720,3ptp4l0-21swapper/119:30:121
4147997031,8cyclictest41-21ksoftirqd/321:10:243
4147997029,8cyclictest41-21ksoftirqd/322:35:223
4147997025,7cyclictest41-21ksoftirqd/321:57:113
4147996936,7cyclictest41-21ksoftirqd/300:20:003
4147996732,3cyclictest41-21ksoftirqd/323:30:003
134491670,28ptp4l25293-21awk22:15:001
4147996635,7cyclictest41-21ksoftirqd/322:45:113
4147996627,11cyclictest41-21ksoftirqd/300:36:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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