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2025-12-01 - 22:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Dec 01, 2025 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1843522050,4sleep30-21swapper/307:05:363
3190621340,3sleep01921799cyclictest09:55:150
1597121300,6sleep21921999cyclictest09:20:192
2847191680,27ptp4l8932-21apt-get11:25:123
2847191670,5ptp4l0-21swapper/111:00:321
2847191670,2ptp4l121rcu_preempt09:45:263
2847191630,4ptp4l0-21swapper/008:35:260
2847191600,4ptp4l0-21swapper/111:54:561
2847191590,5ptp4l0-21swapper/007:07:270
2847191590,4ptp4l0-21swapper/110:15:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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