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2026-06-20 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jun 20, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
780521670,2sleep00-21swapper/011:45:220
789221510,6sleep0775799cyclictest07:10:130
2545521430,4sleep0775799cyclictest08:55:200
46521240,3sleep3776099cyclictest11:30:213
775899694,63cyclictest15552-21kworker/1:211:03:491
7757996634,4cyclictest9-21ksoftirqd/010:55:010
7757996531,5cyclictest9-21ksoftirqd/009:40:290
7757996524,6cyclictest9-21ksoftirqd/009:45:160
7757996431,6cyclictest9-21ksoftirqd/012:10:160
7757996430,5cyclictest9-21ksoftirqd/010:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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