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2025-09-18 - 06:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Sep 18, 2025 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2397821280,7sleep22780899cyclictest20:10:192
27806997515,48cyclictest11889-21df_inode22:10:160
2780699745,56cyclictest25623-1awk23:50:000
27806997214,16cyclictest30448-21cpuspeed_turbos20:25:140
27806996911,11cyclictest20773-21idleruntime-cro20:05:000
27806996816,9cyclictest4705-21cut20:40:000
27806996612,10cyclictest28305-21hwlatdetect19:10:170
27808996521,4cyclictest33-21ksoftirqd/219:45:192
27806996419,10cyclictest6930-21taskset20:44:310
27806996412,10cyclictest30058-21unixbench_singl23:55:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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