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2026-02-18 - 04:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Feb 18, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
432821450,7sleep02838099cyclictest21:45:200
134491680,3ptp4l29994-21ntp_states21:30:253
60942650,4sleep30-21swapper/319:30:203
134491640,5ptp4l0-21swapper/122:10:211
222922630,3sleep32838399cyclictest20:05:173
134491620,4ptp4l10988-21irqstats20:50:200
134491620,4ptp4l0-21swapper/023:35:150
134491610,28ptp4l41-21ksoftirqd/322:20:343
134491610,28ptp4l41-21ksoftirqd/322:20:343
134491590,4ptp4l831-21apt-get20:30:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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