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2026-07-09 - 05:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 09, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2931997335,7cyclictest33-21ksoftirqd/223:00:002
2931997237,5cyclictest33-21ksoftirqd/219:20:002
2931997236,4cyclictest33-21ksoftirqd/219:40:002
2931997236,4cyclictest33-21ksoftirqd/219:40:002
2931996936,5cyclictest33-21ksoftirqd/200:20:002
2931996930,6cyclictest33-21ksoftirqd/221:00:012
2931996733,6cyclictest33-21ksoftirqd/223:45:282
2931996732,5cyclictest33-21ksoftirqd/200:10:002
2931996532,6cyclictest33-21ksoftirqd/219:20:172
323562640,4sleep3448-21dbus-daemon20:10:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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