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2025-10-27 - 16:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Oct 27, 2025 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
916521460,7sleep0193999cyclictest07:25:170
1941996910,20cyclictest207-21systemd-journal11:43:382
2847191660,4ptp4l0-21swapper/108:50:421
2847191650,3ptp4l20520-21fschecks_time12:25:170
296352640,7sleep0193999cyclictest11:35:230
2847191610,4ptp4l0-21swapper/211:55:152
2847191610,4ptp4l0-21swapper/210:02:592
2847191600,18ptp4l15293-21fw_packets11:05:191
194199609,12cyclictest5066-21date09:35:002
1941995810,9cyclictest322-21df08:15:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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