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2026-06-01 - 15:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jun 01, 2026 12:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491640,5ptp4l0-21swapper/010:25:040
134491620,26ptp4l41-21ksoftirqd/310:15:023
146932610,7sleep02823099cyclictest09:00:140
134491600,4ptp4l0-21swapper/112:35:131
134491590,4ptp4l0-21swapper/311:57:553
134491590,4ptp4l0-21swapper/207:30:102
134491590,4ptp4l0-21swapper/007:34:510
134491580,4ptp4l0-21swapper/208:30:082
134491580,4ptp4l0-21swapper/207:26:152
134491580,4ptp4l0-21swapper/111:54:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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