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2026-07-13 - 15:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jul 13, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1170621690,2sleep2324599cyclictest21:45:262
134491610,4ptp4l0-21swapper/220:20:592
134491610,22ptp4l0-21swapper/223:35:012
134491610,18ptp4l5734-21apt-get20:25:103
324499596,15cyclictest3962-21hddtemp_smartct22:40:161
216512590,7sleep0324399cyclictest00:25:260
134491590,4ptp4l0-21swapper/023:58:460
134491580,4ptp4l0-21swapper/222:44:422
134491580,4ptp4l0-21swapper/200:31:442
324499573,14cyclictest6428-21df_abs23:55:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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