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2026-08-12 - 23:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 12, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1356521400,5sleep3380999cyclictest07:30:183
134491820,4ptp4l0-21swapper/012:20:170
134491590,4ptp4l0-21swapper/312:39:553
134491590,4ptp4l0-21swapper/208:40:072
134491580,4ptp4l0-21swapper/311:44:213
134491580,3ptp4l8602-21apt-get08:30:122
134491580,3ptp4l0-21swapper/207:35:162
134491570,4ptp4l0-21swapper/311:05:263
134491570,4ptp4l0-21swapper/310:00:133
134491550,4ptp4l0-21swapper/210:30:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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