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2026-01-18 - 18:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jan 18, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
869321580,6sleep00-21swapper/007:05:250
1825221580,2sleep1955699cyclictest08:44:591
119521390,6sleep3955899cyclictest10:30:013
2406921380,4sleep00-21swapper/012:25:270
148422720,7sleep3955899cyclictest09:50:013
134491680,3ptp4l3677-21apt-get08:15:040
134491630,5ptp4l0-21swapper/010:45:280
134491590,4ptp4l0-21swapper/108:20:271
134491590,3ptp4l14124-21ls09:45:252
134491580,4ptp4l0-21swapper/109:43:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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