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2025-06-29 - 00:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jun 28, 2025 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2698221640,5sleep11201899cyclictest10:00:011
2712121210,4sleep21201999cyclictest11:07:422
12020996412,11cyclictest1904-21chrt12:31:363
12020996312,11cyclictest6466-21chrt11:34:263
12020996311,39cyclictest31125-21apt-get09:00:163
2847191620,4ptp4l0-21swapper/210:09:142
2847191620,4ptp4l0-21swapper/207:55:202
12020996211,16cyclictest9764-21taskset08:14:553
12020996211,12cyclictest14615-21taskset09:30:363
12020996211,10cyclictest14116-21taskset08:20:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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