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2026-06-07 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jun 07, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
561721460,7sleep32293499cyclictest11:10:173
2293399842,79cyclictest0-21swapper/208:25:292
2293399792,2cyclictest0-21swapper/210:20:282
22933997716,59cyclictest0-21swapper/210:05:282
134491680,4ptp4l0-21swapper/209:45:172
134491680,4ptp4l0-21swapper/209:45:172
134491650,22ptp4l0-21swapper/210:35:002
134491610,4ptp4l8198-21basename11:15:173
134491610,4ptp4l0-21swapper/210:18:012
134491610,4ptp4l0-21swapper/008:25:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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