You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-06 - 01:26
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 05, 2026 12:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11815996824,5cyclictest9-21ksoftirqd/008:07:360
11815996723,4cyclictest9-21ksoftirqd/011:39:540
11815996722,7cyclictest9-21ksoftirqd/009:20:000
11815996518,9cyclictest9-21ksoftirqd/011:25:260
309582640,5sleep10-21swapper/110:55:161
11815996423,5cyclictest9-21ksoftirqd/007:12:400
11815996328,4cyclictest9-21ksoftirqd/011:18:470
134491620,17ptp4l448-21dbus-daemon11:18:222
11815996122,4cyclictest9-21ksoftirqd/011:31:080
11815996116,8cyclictest9-21ksoftirqd/010:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional