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2026-07-16 - 10:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 16, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3085722140,4sleep330855-21hddtemp_smartct19:05:173
161821540,6sleep23276099cyclictest23:50:152
792921380,7sleep13275999cyclictest19:25:171
105302680,5sleep10-21swapper/100:10:001
32758996629,4cyclictest9-21ksoftirqd/022:00:000
32759996529,8cyclictest25-21ksoftirqd/121:15:171
134491650,4ptp4l4187-21irqstats20:25:182
32758996421,10cyclictest9-21ksoftirqd/022:15:280
32759996231,3cyclictest25-21ksoftirqd/121:55:181
32758996233,3cyclictest9-21ksoftirqd/022:45:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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