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2026-08-10 - 20:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Aug 10, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2494221430,5sleep13260199cyclictest09:10:271
32601996421,4cyclictest25-21ksoftirqd/112:38:011
32601996220,7cyclictest25-21ksoftirqd/108:24:021
134491620,4ptp4l0-21swapper/007:20:250
134491610,5ptp4l0-21swapper/109:20:281
134491610,5ptp4l0-21swapper/010:35:060
134491610,4ptp4l12642-21irqstats07:35:201
32601996023,5cyclictest25-21ksoftirqd/112:10:331
32601995913,4cyclictest25-21ksoftirqd/110:56:141
134491590,4ptp4l0-21swapper/011:25:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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