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2026-01-12 - 09:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jan 12, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1674521560,6sleep2409899cyclictest00:10:282
167262680,4sleep10-21swapper/119:35:201
188172640,3sleep00-21swapper/022:00:160
101092640,3sleep10-21swapper/121:40:191
409799635,3cyclictest134491ptp4l21:15:291
134491590,4ptp4l0-21swapper/100:02:581
134491590,20ptp4l0-21swapper/200:38:482
134491580,4ptp4l0-21swapper/019:56:330
134491580,4ptp4l0-21swapper/000:15:200
134491570,4ptp4l0-21swapper/020:45:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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