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2026-01-09 - 01:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jan 08, 2026 12:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2115621760,4sleep0265599cyclictest07:50:000
134491800,6ptp4l0-21swapper/307:26:223
134491680,3ptp4l121rcu_preempt09:45:260
253392670,3sleep00-21swapper/010:25:130
2656996326,7cyclictest25-21ksoftirqd/112:01:241
2656996227,7cyclictest25-21ksoftirqd/109:05:201
134491620,18ptp4l0-21swapper/311:05:213
2656996027,6cyclictest25-21ksoftirqd/108:40:211
134491600,5ptp4l0-21swapper/011:10:150
2656995931,4cyclictest25-21ksoftirqd/107:35:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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