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2026-06-15 - 07:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jun 15, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2661821580,3sleep1173899cyclictest23:30:171
2675321440,3sleep2173999cyclictest21:10:212
267321400,3sleep1173899cyclictest20:20:141
2452721340,3sleep3174099cyclictest22:15:213
173799613,15cyclictest0-21swapper/021:20:270
134491610,4ptp4l0-21swapper/219:39:382
134491600,4ptp4l0-21swapper/219:50:052
134491590,9ptp4l0-21swapper/223:30:582
134491590,4ptp4l0-21swapper/220:15:252
134491590,3ptp4l0-21swapper/021:50:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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