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2026-01-01 - 12:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Dec 31, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1953499800,77cyclictest6741-21cut12:30:193
134491700,7ptp4l0-21swapper/210:22:342
1953499682,22cyclictest0-21swapper/310:35:013
1953499682,22cyclictest0-21swapper/310:35:013
1953499662,28cyclictest0-21swapper/312:15:583
1953499660,62cyclictest8882-21cut10:15:193
1953499660,22cyclictest137891phc2sys07:35:283
1953499631,59cyclictest24301-21dpkg08:30:003
134491630,3ptp4l8746-21fschecks_time09:05:160
1953499620,58cyclictest11051-21which10:20:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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