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2026-08-22 - 14:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Aug 22, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2103921800,6sleep21523299cyclictest23:55:272
884121550,3sleep31523399cyclictest20:05:173
59002700,4sleep35899-21needreboot22:15:223
1523299633,10cyclictest14717-21egrep23:45:122
1523299629,16cyclictest23901-21ntpq20:35:202
1523299627,13cyclictest0-21swapper/200:10:262
134491620,5ptp4l27191-21ntp_states23:00:220
1523299614,16cyclictest28188-21cat19:35:252
1523299614,15cyclictest21916-21cpuspeed00:00:132
134491610,4ptp4l0-21swapper/120:55:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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