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2026-08-08 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Aug 08, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2950099693,64cyclictest0-21swapper/209:50:292
2950099693,64cyclictest0-21swapper/209:50:292
29500996834,5cyclictest33-21ksoftirqd/210:20:232
134491680,3ptp4l0-21swapper/312:39:563
29500996734,5cyclictest33-21ksoftirqd/210:10:012
29500996733,6cyclictest33-21ksoftirqd/210:20:002
134491670,4ptp4l0-21swapper/312:33:393
134491670,4ptp4l0-21swapper/311:10:193
134491660,19ptp4l3744-21ls10:50:211
29500996432,5cyclictest33-21ksoftirqd/209:00:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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