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2026-07-15 - 08:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jul 15, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1569421390,5sleep0548299cyclictest00:05:280
548499809,61cyclictest12142-21timerandwakeup21:40:282
5484997911,65cyclictest10552-21tune2fs19:20:172
5484997511,62cyclictest0-21swapper/222:20:282
5484997413,11cyclictest15034-21latency_hist21:50:002
548499740,70cyclictest0-21swapper/223:00:152
5484997216,11cyclictest24386-21chrt22:08:482
5484997214,12cyclictest5653-21chrt21:28:132
5484997015,11cyclictest25227-21taskset00:25:322
5484997013,12cyclictest11472-21chrt23:58:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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