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2026-06-18 - 13:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jun 18, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24042740,1sleep32405-21/usr/sbin/munin23:50:293
31950997325,4cyclictest25-21ksoftirqd/120:21:141
31950996925,4cyclictest25-21ksoftirqd/119:54:221
134491690,5ptp4l41-21ksoftirqd/320:42:483
31950996822,8cyclictest25-21ksoftirqd/121:20:001
134491660,9ptp4l0-21swapper/023:25:310
31951996425,9cyclictest33-21ksoftirqd/219:13:392
31951996329,5cyclictest33-21ksoftirqd/200:04:002
31951996327,3cyclictest33-21ksoftirqd/200:10:172
31950996319,8cyclictest25-21ksoftirqd/119:20:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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