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2026-04-30 - 12:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Apr 30, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491710,4ptp4l0-21swapper/020:35:060
2496996930,8cyclictest41-21ksoftirqd/322:30:223
2496996926,3cyclictest41-21ksoftirqd/300:20:143
2496996732,8cyclictest41-21ksoftirqd/320:05:153
2496996630,4cyclictest41-21ksoftirqd/321:55:003
2496996528,4cyclictest41-21ksoftirqd/319:55:003
2496996432,7cyclictest41-21ksoftirqd/322:50:243
2496996431,9cyclictest41-21ksoftirqd/320:25:003
2496996430,7cyclictest41-21ksoftirqd/320:25:283
2496996430,4cyclictest41-21ksoftirqd/323:30:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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