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2026-07-09 - 17:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jul 09, 2026 12:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216002730,5sleep121604-21cpuspeed_turbos09:50:141
92962640,4sleep10-21swapper/111:40:261
268122620,4sleep10-21swapper/107:40:201
134491610,5ptp4l0-21swapper/310:55:113
134491610,4ptp4l0-21swapper/008:55:150
134491580,3ptp4l0-21swapper/011:55:110
134491570,4ptp4l0-21swapper/208:55:042
134491570,4ptp4l0-21swapper/108:12:331
134491570,4ptp4l0-21swapper/008:00:180
134491570,3ptp4l0-21swapper/311:00:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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