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2026-02-06 - 03:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 05, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
689299722,28cyclictest0-21swapper/320:55:243
6892996938,7cyclictest41-21ksoftirqd/322:50:013
36232680,4sleep30-21swapper/322:30:013
6892996727,8cyclictest41-21ksoftirqd/323:09:593
6892996631,9cyclictest41-21ksoftirqd/320:10:173
6892996526,8cyclictest41-21ksoftirqd/323:00:013
6892996433,3cyclictest41-21ksoftirqd/323:35:273
6892996432,6cyclictest41-21ksoftirqd/321:40:013
6892996428,7cyclictest41-21ksoftirqd/323:20:153
164062640,3sleep2689199cyclictest20:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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