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2026-09-05 - 21:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Sep 05, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509021550,4sleep03030099cyclictest12:00:210
30300997028,8cyclictest9-21ksoftirqd/010:30:220
134491700,16ptp4l0-21swapper/211:10:202
30301996837,3cyclictest25-21ksoftirqd/108:10:001
134491680,20ptp4l13155-21ntp_states07:40:252
30301996719,6cyclictest25-21ksoftirqd/112:25:231
30300996735,3cyclictest9-21ksoftirqd/008:35:000
30300996733,4cyclictest9-21ksoftirqd/008:15:010
30301996634,3cyclictest25-21ksoftirqd/111:40:261
30300996630,10cyclictest9-21ksoftirqd/008:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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