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2026-06-19 - 17:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 19, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2344421630,4sleep2826099cyclictest07:40:232
183602700,4sleep10-21swapper/111:00:001
8259996928,10cyclictest25-21ksoftirqd/108:20:191
8259996729,7cyclictest25-21ksoftirqd/107:55:171
134491660,4ptp4l0-21swapper/009:09:530
8259996428,4cyclictest25-21ksoftirqd/111:45:131
8259996424,3cyclictest25-21ksoftirqd/111:40:231
8259996331,6cyclictest25-21ksoftirqd/109:49:591
8259996331,4cyclictest25-21ksoftirqd/110:15:161
8259996329,4cyclictest25-21ksoftirqd/107:20:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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