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2026-08-26 - 08:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Aug 26, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491700,6ptp4l25-21ksoftirqd/123:00:301
2089599663,61cyclictest0-21swapper/222:55:282
134491630,4ptp4l0-21swapper/019:05:150
134491600,3ptp4l0-21swapper/022:30:190
134491590,5ptp4l0-21swapper/022:53:370
134491580,4ptp4l0-21swapper/323:06:273
2089599574,7cyclictest0-21swapper/220:10:172
2089599574,7cyclictest0-21swapper/220:10:172
134491570,3ptp4l8224-21ls19:50:220
2089599565,6cyclictest0-21swapper/200:20:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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