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2026-07-20 - 21:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jul 20, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32412997332,10cyclictest33-21ksoftirqd/211:10:012
32412997332,10cyclictest33-21ksoftirqd/211:10:012
3241299684,61cyclictest10011-21awk10:55:292
32412996731,6cyclictest33-21ksoftirqd/208:15:272
32412996529,5cyclictest33-21ksoftirqd/208:20:192
32412996431,4cyclictest33-21ksoftirqd/210:50:012
32412996421,7cyclictest33-21ksoftirqd/208:25:502
32412996331,4cyclictest33-21ksoftirqd/211:55:282
32412996325,7cyclictest33-21ksoftirqd/207:54:292
32412996232,5cyclictest33-21ksoftirqd/210:30:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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