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2026-07-25 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 25, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1566721780,7sleep33174299cyclictest19:59:113
1566721780,7sleep33174299cyclictest19:59:113
90921760,7sleep13174099cyclictest20:00:051
423321730,6sleep23174199cyclictest20:03:352
1600621720,3sleep23174199cyclictest23:45:242
1576421570,6sleep03173999cyclictest19:59:440
1576421570,6sleep03173999cyclictest19:59:440
365721560,6sleep03173999cyclictest19:17:060
184692930,4sleep118460-21expr19:39:031
120492830,3sleep012048-21wc20:03:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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