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2026-06-19 - 04:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 19, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2414121430,4sleep22788199cyclictest22:30:142
134491880,12ptp4l0-21swapper/221:55:292
319962690,10sleep031999-21unixbench_singl20:25:270
134491650,2ptp4l2939-21/usr/sbin/munin19:25:150
134491600,4ptp4l0-21swapper/021:10:160
134491600,3ptp4l0-21swapper/319:33:283
134491590,4ptp4l0-21swapper/021:05:160
27882995817,8cyclictest41-21ksoftirqd/300:25:263
134491580,4ptp4l0-21swapper/023:17:470
134491580,4ptp4l0-21swapper/019:20:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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