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2026-06-03 - 19:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed Jun 03, 2026 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1219721570,6sleep31362699cyclictest10:35:163
2361721450,6sleep11362499cyclictest08:40:171
765821430,3sleep21362599cyclictest11:35:132
1362699732,35cyclictest0-21swapper/308:00:263
1362399722,2cyclictest0-21swapper/009:48:520
13626996832,4cyclictest41-21ksoftirqd/312:20:003
1362699672,34cyclictest0-21swapper/311:10:143
13623996613,23cyclictest21180-21cat07:25:180
1362399643,5cyclictest0-21swapper/007:50:290
1362399633,3cyclictest134491ptp4l09:55:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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