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2026-08-25 - 06:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Aug 25, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
364199782,33cyclictest0-21swapper/321:10:243
134491700,17ptp4l0-21swapper/120:48:091
3641996828,8cyclictest41-21ksoftirqd/319:12:293
3641996627,5cyclictest41-21ksoftirqd/322:15:013
181682660,5sleep318172-21irqrtprio19:40:193
134491660,5ptp4l0-21swapper/021:25:250
134491660,5ptp4l0-21swapper/021:25:250
3641996531,4cyclictest41-21ksoftirqd/320:30:003
3641996531,4cyclictest41-21ksoftirqd/320:30:003
3641996530,4cyclictest41-21ksoftirqd/319:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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