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2026-09-04 - 20:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Sep 04, 2026 12:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2831021800,7sleep02740499cyclictest07:10:200
124421210,4sleep10-21swapper/112:00:211
74802730,6sleep10-21swapper/108:45:171
134491690,8ptp4l0-21swapper/212:04:542
134491680,5ptp4l0-21swapper/107:35:101
27407996634,4cyclictest41-21ksoftirqd/309:55:263
27407996627,8cyclictest41-21ksoftirqd/311:26:553
27407996627,10cyclictest41-21ksoftirqd/309:51:043
27407996527,8cyclictest41-21ksoftirqd/309:39:373
246732650,6sleep10-21swapper/110:30:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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