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2026-06-21 - 06:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Jun 21, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491670,6ptp4l0-21swapper/020:05:210
134491670,5ptp4l0-21swapper/322:35:113
280602660,3sleep30-21swapper/323:25:183
235922640,5sleep10-21swapper/122:05:211
134491640,18ptp4l0-21swapper/023:35:000
134491600,3ptp4l0-21swapper/023:05:160
134491590,4ptp4l0-21swapper/322:34:493
134491590,3ptp4l0-21swapper/122:10:271
134491580,4ptp4l0-21swapper/300:05:243
134491580,3ptp4l0-21swapper/220:10:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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