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2026-01-16 - 01:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Jan 15, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36792800,21sleep20-21swapper/209:45:002
195792710,5sleep20-21swapper/211:25:252
28516996427,5cyclictest41-21ksoftirqd/311:38:013
28516996335,6cyclictest41-21ksoftirqd/308:40:173
28516996332,3cyclictest41-21ksoftirqd/307:35:173
28516996331,4cyclictest41-21ksoftirqd/310:29:413
28516996331,4cyclictest41-21ksoftirqd/310:29:413
28516996329,4cyclictest41-21ksoftirqd/312:27:003
134491630,4ptp4l0-21swapper/108:30:171
134491630,4ptp4l0-21swapper/108:30:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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