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2026-09-06 - 11:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Sep 06, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2540621390,5sleep20-21swapper/222:00:272
2540621390,5sleep20-21swapper/222:00:272
1869121360,5sleep3912699cyclictest21:45:273
9125998418,63cyclictest32021-21users19:55:282
9125998418,63cyclictest32021-21users19:55:282
9125997815,61cyclictest0-21swapper/219:25:282
912599711,68cyclictest0-21swapper/220:10:282
38342710,5sleep03835-21ps20:05:230
317972700,3sleep20-21swapper/222:15:192
912499690,66cyclictest31476-21/usr/sbin/munin21:05:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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