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2026-05-27 - 03:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Wed May 27, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
485599711,1cyclictest0-21swapper/220:00:282
134491620,4ptp4l0-21swapper/223:43:052
134491610,9ptp4l0-21swapper/223:23:222
134491600,4ptp4l0-21swapper/123:55:191
134491590,3ptp4l11848-21ls00:00:291
134491580,5ptp4l0-21swapper/219:09:282
134491580,4ptp4l0-21swapper/223:11:592
134491580,2ptp4l22493-21grep19:45:251
134491570,4ptp4l0-21swapper/100:07:591
134491570,3ptp4l9-21ksoftirqd/019:35:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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