You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-13 - 01:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jan 12, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
943421270,4sleep12902199cyclictest08:45:201
943421270,4sleep12902199cyclictest08:45:201
29022997138,3cyclictest33-21ksoftirqd/208:25:162
29022996733,5cyclictest33-21ksoftirqd/212:10:162
134491670,8ptp4l0-21swapper/212:30:072
134491670,20ptp4l14988-21/usr/sbin/munin12:30:141
29022996534,8cyclictest33-21ksoftirqd/210:30:262
29022996533,5cyclictest33-21ksoftirqd/207:55:212
29022996434,5cyclictest33-21ksoftirqd/212:19:592
29022996424,8cyclictest33-21ksoftirqd/210:07:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional