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2026-08-09 - 18:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 09, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491790,10ptp4l14612-21sshd19:07:130
15122996434,7cyclictest41-21ksoftirqd/320:00:263
134491610,4ptp4l0-21swapper/119:35:201
15122996032,4cyclictest41-21ksoftirqd/321:18:313
15122996028,6cyclictest41-21ksoftirqd/321:00:163
15122996028,4cyclictest41-21ksoftirqd/322:10:193
15120996011,4cyclictest25-21ksoftirqd/120:35:001
15120996011,4cyclictest25-21ksoftirqd/120:35:001
15122995924,7cyclictest41-21ksoftirqd/321:45:023
15122995822,7cyclictest41-21ksoftirqd/323:15:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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