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2026-06-12 - 13:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Jun 12, 2026 00:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1457221520,8sleep02442999cyclictest23:25:170
1495421360,3sleep30-21swapper/323:25:213
12672650,6sleep30-21swapper/322:55:283
134491640,6ptp4l0-21swapper/219:25:252
134491620,3ptp4l0-21swapper/022:50:290
134491590,4ptp4l15698-21/usr/sbin/munin20:00:170
134491580,4ptp4l0-21swapper/000:29:050
134491570,3ptp4l0-21swapper/321:40:303
134491550,4ptp4l0-21swapper/000:04:510
134491550,3ptp4l0-21swapper/321:25:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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