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2026-06-22 - 06:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jun 22, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2495121600,5sleep31541099cyclictest19:30:143
2495121600,5sleep31541099cyclictest19:30:143
326521390,6sleep11540899cyclictest00:30:191
15408996933,5cyclictest25-21ksoftirqd/122:59:591
15408996724,5cyclictest25-21ksoftirqd/119:15:181
134491670,3ptp4l0-21swapper/019:36:250
15408996432,4cyclictest25-21ksoftirqd/121:20:251
15408996330,8cyclictest25-21ksoftirqd/122:30:001
15408996329,8cyclictest25-21ksoftirqd/120:10:281
15408996228,6cyclictest25-21ksoftirqd/122:35:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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