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2026-04-23 - 22:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Thu Apr 23, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
162232760,5sleep20-21swapper/207:30:242
569299743,3cyclictest0-21swapper/209:55:142
134491710,4ptp4l0-21swapper/007:39:540
255792690,6sleep1569199cyclictest12:30:131
102832620,3sleep20-21swapper/211:55:202
134491610,25ptp4l25-21ksoftirqd/110:45:221
134491610,18ptp4l13580-21latency_hist10:55:000
134491600,4ptp4l0-21swapper/310:20:243
134491600,4ptp4l0-21swapper/307:12:443
134491600,4ptp4l0-21swapper/307:12:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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