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2026-08-30 - 15:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Aug 30, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3131421690,7sleep12641399cyclictest08:29:131
981721590,6sleep22641499cyclictest12:20:172
981721590,6sleep22641499cyclictest12:20:172
2172621480,4sleep32641599cyclictest09:15:293
2641499730,31cyclictest1633-21taskset12:00:402
2641499710,30cyclictest8659-21taskset11:08:332
2641499691,31cyclictest15684-21chrt11:21:332
2641499690,32cyclictest15699-21chrt12:32:342
2641499690,31cyclictest14746-21chrt07:54:402
2641499681,28cyclictest28721-21chrt07:15:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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