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2026-06-02 - 17:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Tue Jun 02, 2026 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
222792780,7sleep12351999cyclictest09:25:191
134491720,5ptp4l33-21ksoftirqd/210:25:232
134491690,4ptp4l15908-21meminfo11:30:202
134491660,5ptp4l12191-21/usr/sbin/munin12:30:300
23519996428,8cyclictest25-21ksoftirqd/110:05:011
23519996333,8cyclictest25-21ksoftirqd/110:20:281
23519996331,3cyclictest25-21ksoftirqd/109:45:001
134491630,4ptp4l0-21swapper/207:05:042
23519996232,8cyclictest25-21ksoftirqd/112:00:011
23519996231,6cyclictest25-21ksoftirqd/107:50:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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