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2026-03-06 - 09:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot1.osadl.org (updated Fri Mar 06, 2026 00:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2202099772,33cyclictest0-21swapper/320:25:473
2202099732,32cyclictest0-21swapper/300:00:263
134491680,4ptp4l0-21swapper/122:50:561
134491680,4ptp4l0-21swapper/122:50:561
177632670,6sleep02201799cyclictest20:10:010
22019996634,4cyclictest33-21ksoftirqd/222:05:162
134491660,17ptp4l11290-21hddtemp_smartct21:05:181
22019996530,6cyclictest33-21ksoftirqd/223:51:172
22019996330,4cyclictest33-21ksoftirqd/222:45:532
22019996131,3cyclictest33-21ksoftirqd/221:05:202
22019996128,4cyclictest33-21ksoftirqd/219:38:352
22019996029,3cyclictest33-21ksoftirqd/221:10:262
2202099592,32cyclictest0-21swapper/322:34:093
134491590,5ptp4l0-21swapper/022:25:200
134491590,4ptp4l0-21swapper/023:50:160
134491590,4ptp4l0-21swapper/021:00:210
22019995830,4cyclictest33-21ksoftirqd/221:35:252
22019995830,3cyclictest33-21ksoftirqd/223:56:402
134491580,4ptp4l0-21swapper/321:45:373
134491580,3ptp4l0-21swapper/122:35:251
2202099572,39cyclictest0-21swapper/323:24:443
2202099572,36cyclictest0-21swapper/322:25:433
2202099571,6cyclictest13021-21sed21:10:003
22019995727,5cyclictest33-21ksoftirqd/220:50:142
22019995727,3cyclictest33-21ksoftirqd/223:35:192
22019995725,4cyclictest33-21ksoftirqd/222:20:192
22019995722,11cyclictest33-21ksoftirqd/222:00:292
2202099562,34cyclictest0-21swapper/321:58:223
2202099562,33cyclictest0-21swapper/319:46:533
22019995629,7cyclictest33-21ksoftirqd/221:25:182
22019995628,3cyclictest33-21ksoftirqd/220:22:102
22019995628,3cyclictest33-21ksoftirqd/220:15:212
22019995627,3cyclictest33-21ksoftirqd/200:05:002
22019995626,7cyclictest33-21ksoftirqd/223:40:242
22019995626,5cyclictest33-21ksoftirqd/223:10:252
22019995624,8cyclictest33-21ksoftirqd/220:50:012
22019995622,7cyclictest33-21ksoftirqd/200:30:002
134491560,4ptp4l0-21swapper/000:18:170
2202099554,7cyclictest0-21swapper/321:01:543
2202099552,34cyclictest0-21swapper/322:08:533
2202099552,34cyclictest0-21swapper/300:38:103
2201999556,2cyclictest14068-21sendmail-msp00:40:012
22019995528,6cyclictest33-21ksoftirqd/200:05:192
22019995528,3cyclictest33-21ksoftirqd/222:25:272
22019995526,4cyclictest33-21ksoftirqd/200:20:282
22019995522,7cyclictest33-21ksoftirqd/219:45:012
22019995522,7cyclictest33-21ksoftirqd/219:45:012
22019995522,3cyclictest33-21ksoftirqd/223:25:002
134491550,3ptp4l0-21swapper/120:52:551
134491550,3ptp4l0-21swapper/022:00:140
2202099542,32cyclictest0-21swapper/320:19:143
2202099542,32cyclictest0-21swapper/319:57:163
2202099541,7cyclictest2261-21grep23:05:133
22019995426,3cyclictest33-21ksoftirqd/219:15:182
22019995425,4cyclictest33-21ksoftirqd/220:36:382
160732540,4sleep316078-21irqrtprio20:05:193
134491540,4ptp4l0-21swapper/120:49:171
134491540,3ptp4l0-21swapper/122:24:011
2202099537,7cyclictest0-21swapper/319:20:303
22020995349,2cyclictest401ktimersoftd/322:00:153
2202099532,6cyclictest6645-21cut20:55:193
2202099531,6cyclictest8950-21unixbench_multi00:25:293
2202099531,6cyclictest27050-21sed23:55:283
2202099530,6cyclictest401ktimersoftd/321:15:003
22019995322,9cyclictest33-21ksoftirqd/222:10:222
22019995322,3cyclictest33-21ksoftirqd/219:30:272
22019995321,4cyclictest33-21ksoftirqd/219:26:522
134491530,4ptp4l0-21swapper/123:05:371
134491530,4ptp4l0-21swapper/023:33:220
2202099525,6cyclictest0-21swapper/322:43:443
2202099525,5cyclictest0-21swapper/320:45:563
2202099524,6cyclictest0-21swapper/321:34:393
2202099522,31cyclictest0-21swapper/320:00:373
2202099521,6cyclictest30643-21cut22:55:173
2202099520,6cyclictest17083-1kworker/3:2H19:15:013
2201999525,3cyclictest33-21ksoftirqd/221:35:002
22019995222,4cyclictest33-21ksoftirqd/222:55:222
22019995222,4cyclictest33-21ksoftirqd/222:40:232
22019995221,3cyclictest33-21ksoftirqd/220:30:312
134491520,5ptp4l0-21swapper/319:07:043
134491520,4ptp4l0-21swapper/123:53:581
134491520,4ptp4l0-21swapper/100:30:581
134491520,4ptp4l0-21swapper/023:16:120
134491520,4ptp4l0-21swapper/023:11:080
134491520,4ptp4l0-21swapper/000:10:280
134491520,3ptp4l0-21swapper/119:36:411
2202099515,11cyclictest0-21swapper/300:10:123
2202099514,8cyclictest41-21ksoftirqd/321:15:273
2202099514,7cyclictest0-21swapper/300:06:253
2202099514,6cyclictest0-21swapper/319:51:013
2202099514,11cyclictest0-21swapper/323:40:253
2202099512,5cyclictest11301-21latency_hist22:15:013
2202099512,37cyclictest0-21swapper/320:23:513
2201999514,3cyclictest121rcu_preempt20:30:002
2201999512,6cyclictest0-21swapper/221:15:262
22019995114,11cyclictest33-21ksoftirqd/219:10:262
2201999510,5cyclictest33-21ksoftirqd/222:39:592
134491510,4ptp4l0-21swapper/122:34:401
2202099504,7cyclictest0-21swapper/323:52:443
2202099503,5cyclictest401ktimersoftd/321:40:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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