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2026-01-27 - 06:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot1.osadl.org (updated Tue Jan 27, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
160192830,29sleep233-21ksoftirqd/222:20:122
23895997712,63cyclictest22394-21kworker/1:120:06:091
207612660,5sleep20-21swapper/220:10:192
134491610,16ptp4l0-21swapper/022:30:140
134491600,4ptp4l0-21swapper/000:30:250
134491590,5ptp4l0-21swapper/019:25:220
134491580,4ptp4l0-21swapper/219:26:402
134491580,3ptp4l0-21swapper/021:15:260
134491570,3ptp4l32214-21ls20:35:180
134491570,3ptp4l0-21swapper/222:47:442
134491570,3ptp4l0-21swapper/222:47:442
134491570,3ptp4l0-21swapper/122:20:251
134491560,4ptp4l0-21swapper/219:48:062
134491560,4ptp4l0-21swapper/219:48:062
134491560,12ptp4l0-21swapper/020:58:260
134491540,4ptp4l0-21swapper/020:20:160
23896995323,7cyclictest33-21ksoftirqd/223:27:322
23896995320,7cyclictest33-21ksoftirqd/219:10:422
134491530,4ptp4l0-21swapper/222:35:282
134491520,4ptp4l0-21swapper/023:07:440
134491520,4ptp4l0-21swapper/020:26:110
134491520,3ptp4l0-21swapper/223:18:192
23896995119,6cyclictest33-21ksoftirqd/222:55:212
23896995119,4cyclictest33-21ksoftirqd/223:04:352
23896995118,5cyclictest33-21ksoftirqd/222:19:462
23896995118,4cyclictest33-21ksoftirqd/220:44:512
134491510,5ptp4l0-21swapper/219:42:032
134491510,5ptp4l0-21swapper/019:05:020
134491510,4ptp4l0-21swapper/220:54:582
134491510,3ptp4l0-21swapper/219:51:442
134491510,19ptp4l29897-21df_abs21:40:130
134491510,11ptp4l0-21swapper/021:35:170
23896995016,5cyclictest33-21ksoftirqd/222:40:192
23896995016,5cyclictest33-21ksoftirqd/222:40:192
134491500,5ptp4l0-21swapper/020:15:200
134491500,4ptp4l0-21swapper/323:45:593
134491500,4ptp4l0-21swapper/223:44:382
134491500,4ptp4l0-21swapper/022:16:060
134491500,3ptp4l0-21swapper/319:55:303
134491500,12ptp4l0-21swapper/119:45:441
134491500,12ptp4l0-21swapper/119:45:441
134491500,10ptp4l0-21swapper/221:15:122
134491500,10ptp4l0-21swapper/120:34:551
2389699492,2cyclictest121rcu_preempt23:20:582
23896994915,6cyclictest33-21ksoftirqd/221:25:002
134491490,4ptp4l0-21swapper/300:03:163
134491490,4ptp4l0-21swapper/300:03:163
134491490,4ptp4l0-21swapper/223:57:212
134491490,4ptp4l0-21swapper/221:36:282
134491490,4ptp4l0-21swapper/021:28:540
134491490,4ptp4l0-21swapper/019:35:040
134491490,4ptp4l0-21swapper/019:24:260
134491490,4ptp4l0-21swapper/019:16:010
134491490,4ptp4l0-21swapper/019:11:080
2389699482,4cyclictest0-21swapper/223:13:252
2389699482,2cyclictest121rcu_preempt23:50:582
23896994818,4cyclictest33-21ksoftirqd/200:25:312
23896994817,4cyclictest33-21ksoftirqd/200:24:502
23896994813,4cyclictest33-21ksoftirqd/223:35:262
23896994812,6cyclictest33-21ksoftirqd/222:50:202
2389599489,37cyclictest22394-21kworker/1:120:01:491
134491480,5ptp4l0-21swapper/119:05:181
134491480,4ptp4l0-21swapper/321:47:333
134491480,4ptp4l0-21swapper/320:12:483
134491480,4ptp4l0-21swapper/300:20:203
134491480,4ptp4l0-21swapper/019:59:290
134491480,4ptp4l0-21swapper/000:37:520
134491480,3ptp4l0-21swapper/320:33:403
134491480,3ptp4l0-21swapper/220:01:472
134491480,3ptp4l0-21swapper/219:18:332
134491480,3ptp4l0-21swapper/200:17:562
134491480,2ptp4l121rcu_preempt23:10:221
134491480,11ptp4l0-21swapper/022:08:280
2389699472,2cyclictest121rcu_preempt23:09:582
23896994716,4cyclictest33-21ksoftirqd/200:14:402
23896994715,4cyclictest33-21ksoftirqd/220:19:272
23896994710,8cyclictest33-21ksoftirqd/200:30:452
2389599472,43cyclictest0-21swapper/120:50:391
2389599471,3cyclictest25-21ksoftirqd/123:15:281
134491470,8ptp4l25752-21memory21:30:202
134491470,5ptp4l0-21swapper/219:07:502
134491470,4ptp4l0-21swapper/321:59:403
134491470,4ptp4l0-21swapper/020:54:480
134491470,3ptp4l0-21swapper/221:03:232
134491470,3ptp4l0-21swapper/000:27:500
2389699462,2cyclictest121rcu_preempt22:09:582
23896994620,6cyclictest33-21ksoftirqd/221:58:082
2389699461,3cyclictest121rcu_preempt19:37:592
2389699461,2cyclictest121rcu_preempt23:34:582
2389699460,2cyclictest121rcu_preempt23:48:582
2389699460,2cyclictest121rcu_preempt22:11:582
134491460,5ptp4l0-21swapper/319:06:403
134491460,4ptp4l0-21swapper/123:45:441
134491460,3ptp4l0-21swapper/119:17:321
23896994538,4cyclictest33-21ksoftirqd/220:55:282
23896994511,5cyclictest33-21ksoftirqd/222:30:232
134491450,9ptp4l0-21swapper/219:30:322
134491450,9ptp4l0-21swapper/021:46:490
134491450,4ptp4l13793-21diskstats22:15:151
134491450,3ptp4l0-21swapper/323:40:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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