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2026-02-17 - 09:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 17, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209521510,7sleep3291899cyclictest20:15:263
249621440,5sleep2291799cyclictest23:45:142
291799749,63cyclictest0-21swapper/223:50:292
291799731,70cyclictest0-21swapper/221:25:092
228692680,6sleep0291599cyclictest00:25:270
170672660,7sleep3291899cyclictest21:55:263
170672660,7sleep3291899cyclictest21:55:263
46198650,17rtkit-daemon21404-21cpuspeed00:25:133
291799652,61cyclictest0-21swapper/222:10:292
291799631,59cyclictest26996-21users23:25:282
16192590,6sleep0291599cyclictest23:40:270
152012590,5sleep10-21swapper/123:00:281
134491590,2ptp4l1907-21perl21:25:160
134491580,3ptp4l0-21swapper/319:30:263
291699576,9cyclictest25-21ksoftirqd/121:35:001
2916995724,6cyclictest25-21ksoftirqd/122:10:161
134491570,4ptp4l291799cyclictest22:59:592
134491570,4ptp4l0-21swapper/019:32:360
2916995626,7cyclictest25-21ksoftirqd/119:37:161
134491560,3ptp4l0-21swapper/322:05:143
134491550,4ptp4l291799cyclictest22:15:222
134491550,4ptp4l0-21swapper/300:24:283
134491550,3ptp4l0-21swapper/223:05:292
291699545,6cyclictest12007-21idleruntime-cro19:30:001
2916995421,6cyclictest25-21ksoftirqd/100:32:531
2916995418,4cyclictest25-21ksoftirqd/122:00:531
134491540,4ptp4l0-21swapper/019:37:140
134491540,4ptp4l0-21swapper/019:25:270
134491540,4ptp4l0-21swapper/019:13:580
134491540,4ptp4l0-21swapper/019:13:580
134491540,3ptp4l0-21swapper/100:35:231
134491540,1ptp4l12985-21kworker/2:200:22:572
246712530,3sleep20-21swapper/219:55:192
134491530,4ptp4l0-21swapper/019:05:550
134491530,4ptp4l0-21swapper/000:07:500
134491530,4ptp4l0-21swapper/000:01:140
134491530,3ptp4l0-21swapper/221:57:512
134491530,3ptp4l0-21swapper/221:57:512
291699522,7cyclictest0-21swapper/122:45:221
291699521,7cyclictest0-21swapper/119:30:211
2915995213,4cyclictest12680-21kworker/0:121:07:080
134491520,3ptp4l0-21swapper/020:00:540
134491520,11ptp4l0-21swapper/023:10:160
291699516,8cyclictest25-21ksoftirqd/119:40:131
291699515,6cyclictest5437-21sort20:25:011
291699515,6cyclictest25-21ksoftirqd/123:15:151
2916995123,6cyclictest25-21ksoftirqd/119:52:591
291699511,6cyclictest25-21ksoftirqd/123:45:231
291699510,5cyclictest241ktimersoftd/122:50:171
134491510,5ptp4l0-21swapper/119:08:521
291699505,8cyclictest25-21ksoftirqd/100:10:211
291699505,8cyclictest25-21ksoftirqd/100:10:211
291699504,6cyclictest0-21swapper/119:20:191
291699503,5cyclictest1440-21sh22:35:001
291699503,5cyclictest1440-21sh22:35:001
291699502,5cyclictest25-21ksoftirqd/123:35:271
2916995017,6cyclictest25-21ksoftirqd/100:07:061
291699500,6cyclictest25-21ksoftirqd/123:30:171
134491500,4ptp4l0-21swapper/323:39:353
134491500,4ptp4l0-21swapper/020:11:580
291699494,8cyclictest25-21ksoftirqd/121:20:011
291699494,6cyclictest25-21ksoftirqd/121:40:181
291699494,3cyclictest0-21swapper/119:15:001
291699494,3cyclictest0-21swapper/119:15:001
291699492,6cyclictest25071-21/usr/sbin/munin22:15:121
291699491,6cyclictest25-21ksoftirqd/123:25:001
291699491,6cyclictest0-21swapper/120:30:261
291699491,5cyclictest241ktimersoftd/122:40:141
291699490,6cyclictest25-21ksoftirqd/120:50:191
2915994919,4cyclictest9-21ksoftirqd/021:35:010
134491490,4ptp4l0-21swapper/321:02:023
134491490,4ptp4l0-21swapper/023:22:030
134491490,4ptp4l0-21swapper/022:14:030
134491490,3ptp4l0-21swapper/323:49:543
134491490,3ptp4l0-21swapper/020:35:090
134491490,14ptp4l0-21swapper/200:30:162
291699484,2cyclictest121rcu_preempt20:15:161
291699482,6cyclictest0-21swapper/122:05:231
291699482,4cyclictest0-21swapper/121:10:241
291699481,6cyclictest25-21ksoftirqd/122:25:271
291699480,7cyclictest241ktimersoftd/119:15:251
291699480,6cyclictest241ktimersoftd/121:50:171
291699480,5cyclictest241ktimersoftd/122:20:241
134491480,9ptp4l0-21swapper/220:49:382
134491480,4ptp4l0-21swapper/323:50:223
134491480,4ptp4l0-21swapper/322:47:173
134491480,4ptp4l0-21swapper/200:05:182
134491480,4ptp4l0-21swapper/023:02:280
134491480,4ptp4l0-21swapper/021:17:050
291799475,40cyclictest0-21swapper/221:15:092
291799472,43cyclictest0-21swapper/221:35:192
291699474,9cyclictest25-21ksoftirqd/121:55:251
291699474,9cyclictest25-21ksoftirqd/121:55:251
291699473,6cyclictest25-21ksoftirqd/122:55:191
291699473,5cyclictest25-21ksoftirqd/123:45:001
291699472,6cyclictest25-21ksoftirqd/120:45:261
291699472,6cyclictest25-21ksoftirqd/120:05:271
291699472,5cyclictest25-21ksoftirqd/120:10:281
291699471,6cyclictest25-21ksoftirqd/120:35:211
291699471,6cyclictest25-21ksoftirqd/100:15:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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