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2026-02-10 - 06:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 10, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491760,32ptp4l28950-21apt-get19:05:131
134491720,24ptp4l9034-21ps21:50:190
132932710,4sleep30-21swapper/322:00:143
134491670,4ptp4l9530-21apt-get00:10:130
31288996430,6cyclictest41-21ksoftirqd/320:37:123
31288996425,8cyclictest41-21ksoftirqd/320:20:003
31288996425,8cyclictest41-21ksoftirqd/320:20:003
31288996331,4cyclictest41-21ksoftirqd/321:35:153
31288996331,4cyclictest41-21ksoftirqd/319:30:003
31288996329,8cyclictest41-21ksoftirqd/320:45:153
31288996328,4cyclictest41-21ksoftirqd/321:30:183
31288996324,3cyclictest41-21ksoftirqd/322:25:153
31288996233,6cyclictest41-21ksoftirqd/323:20:003
31288996232,3cyclictest41-21ksoftirqd/320:55:153
31288996228,7cyclictest41-21ksoftirqd/321:45:253
31288996228,4cyclictest41-21ksoftirqd/323:35:013
31288996227,6cyclictest41-21ksoftirqd/300:25:233
31288996227,6cyclictest41-21ksoftirqd/300:25:233
31288996226,10cyclictest41-21ksoftirqd/320:50:243
31288996132,6cyclictest41-21ksoftirqd/320:25:283
31288996130,4cyclictest41-21ksoftirqd/319:24:093
31288996128,7cyclictest41-21ksoftirqd/322:15:193
31288996124,7cyclictest41-21ksoftirqd/300:35:133
31288996124,3cyclictest41-21ksoftirqd/322:50:223
31288996121,8cyclictest41-21ksoftirqd/300:03:123
31288996033,6cyclictest41-21ksoftirqd/320:10:273
31288996032,7cyclictest41-21ksoftirqd/323:35:223
31288996028,3cyclictest41-21ksoftirqd/321:55:213
31288996027,8cyclictest41-21ksoftirqd/319:55:163
31288996027,8cyclictest41-21ksoftirqd/300:30:173
31288996027,7cyclictest41-21ksoftirqd/322:25:013
31288996025,4cyclictest41-21ksoftirqd/320:04:593
31288996022,8cyclictest41-21ksoftirqd/319:37:313
31288996020,7cyclictest41-21ksoftirqd/323:08:403
134491600,4ptp4l0-21swapper/119:25:201
134491600,4ptp4l0-21swapper/020:23:580
31288995930,8cyclictest41-21ksoftirqd/321:05:543
31288995929,3cyclictest41-21ksoftirqd/323:25:153
31288995922,8cyclictest41-21ksoftirqd/322:57:373
31288995922,4cyclictest41-21ksoftirqd/319:45:263
31288995922,4cyclictest41-21ksoftirqd/319:45:263
31288995921,8cyclictest41-21ksoftirqd/300:05:253
134491590,5ptp4l0-21swapper/123:10:251
134491590,3ptp4l0-21swapper/019:20:110
31288995828,7cyclictest41-21ksoftirqd/319:30:233
31288995827,3cyclictest41-21ksoftirqd/300:15:123
31288995826,4cyclictest41-21ksoftirqd/321:21:503
31288995822,8cyclictest41-21ksoftirqd/320:43:313
31288995820,7cyclictest41-21ksoftirqd/323:23:203
134491580,4ptp4l0-21swapper/020:40:180
134491580,3ptp4l0-21swapper/200:15:212
134491580,3ptp4l0-21swapper/120:40:451
31288995731,6cyclictest41-21ksoftirqd/319:50:433
31288995724,8cyclictest41-21ksoftirqd/319:10:153
31288995717,8cyclictest41-21ksoftirqd/319:43:403
31288995629,6cyclictest41-21ksoftirqd/300:10:223
31288995628,4cyclictest41-21ksoftirqd/322:35:183
31288995624,3cyclictest41-21ksoftirqd/323:45:123
31288995623,9cyclictest41-21ksoftirqd/320:09:593
31288995617,7cyclictest41-21ksoftirqd/319:18:183
134491560,5ptp4l0-21swapper/219:09:492
134491560,4ptp4l0-21swapper/021:00:210
134491560,3ptp4l0-21swapper/119:55:291
31288995529,4cyclictest41-21ksoftirqd/321:10:173
31288995525,8cyclictest41-21ksoftirqd/321:40:263
134491550,3ptp4l1317-21runrttasks19:10:191
31288995425,9cyclictest41-21ksoftirqd/321:15:173
31288995423,8cyclictest41-21ksoftirqd/323:05:003
134491540,3ptp4l0-21swapper/020:00:150
31288995317,4cyclictest41-21ksoftirqd/322:08:553
134491530,4ptp4l0-21swapper/023:10:150
134491530,3ptp4l4411-21iostat21:40:190
31288995228,3cyclictest41-21ksoftirqd/322:45:003
3128899522,7cyclictest0-21swapper/323:50:123
3128899522,7cyclictest0-21swapper/321:25:243
31288995221,7cyclictest41-21ksoftirqd/322:10:173
134491520,4ptp4l0-21swapper/220:21:132
134491520,3ptp4l0-21swapper/222:33:132
4982510,5sleep20-21swapper/219:10:282
31288995120,7cyclictest41-21ksoftirqd/321:50:193
134491510,6ptp4l33-21ksoftirqd/222:20:232
134491510,4ptp4l0-21swapper/121:32:281
134491510,4ptp4l0-21swapper/119:45:091
134491510,4ptp4l0-21swapper/119:45:091
134491510,4ptp4l0-21swapper/100:37:451
134491510,4ptp4l0-21swapper/100:20:391
134491510,3ptp4l0-21swapper/023:20:230
134491510,3ptp4l0-21swapper/022:53:110
134491510,19ptp4l0-21swapper/219:23:502
3128899502,6cyclictest0-21swapper/323:10:153
31288995017,9cyclictest41-21ksoftirqd/320:20:213
134491500,4ptp4l0-21swapper/222:47:512
134491500,4ptp4l0-21swapper/120:05:191
134491500,4ptp4l0-21swapper/021:58:270
134491500,4ptp4l0-21swapper/000:06:280
134491500,3ptp4l0-21swapper/020:54:550
3128899490,7cyclictest121rcu_preempt00:21:023
134491490,4ptp4l0-21swapper/222:38:392
134491490,4ptp4l0-21swapper/221:34:082
134491490,4ptp4l0-21swapper/219:46:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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