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2026-01-24 - 22:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot1.osadl.org (updated Sat Jan 24, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134491680,3ptp4l0-21swapper/011:00:220
134491630,3ptp4l16008-21ls08:40:260
134491620,23ptp4l0-21swapper/310:07:033
5094996030,13cyclictest33-21ksoftirqd/209:45:292
5094996030,13cyclictest33-21ksoftirqd/209:45:292
134491600,5ptp4l16296-21kworker/0:009:15:000
134491600,4ptp4l0-21swapper/209:00:502
134491590,3ptp4l0-21swapper/211:35:272
5094995824,5cyclictest33-21ksoftirqd/210:35:252
134491580,3ptp4l0-21swapper/307:32:073
5094995725,6cyclictest33-21ksoftirqd/212:30:202
5094995724,3cyclictest33-21ksoftirqd/212:36:312
134491570,4ptp4l0-21swapper/307:36:123
134491570,4ptp4l0-21swapper/210:29:502
134491570,3ptp4l0-21swapper/207:58:262
5094995622,11cyclictest33-21ksoftirqd/208:39:062
134491560,3ptp4l0-21swapper/307:43:333
134491560,3ptp4l0-21swapper/209:42:192
134491560,3ptp4l0-21swapper/208:44:502
5094995523,4cyclictest33-21ksoftirqd/212:05:252
5094995519,10cyclictest33-21ksoftirqd/211:00:002
134491550,3ptp4l0-21swapper/207:49:392
134491550,3ptp4l0-21swapper/108:00:081
5094995429,8cyclictest33-21ksoftirqd/211:52:182
5094995421,6cyclictest33-21ksoftirqd/210:15:212
5094995420,4cyclictest33-21ksoftirqd/208:27:262
5094995420,4cyclictest33-21ksoftirqd/207:18:222
134491530,5ptp4l0-21swapper/107:09:371
134491530,4ptp4l0-21swapper/109:13:331
5094995221,5cyclictest33-21ksoftirqd/211:48:272
5094995220,6cyclictest33-21ksoftirqd/211:32:402
5094995220,4cyclictest33-21ksoftirqd/211:58:242
5094995217,4cyclictest33-21ksoftirqd/209:57:522
134491520,4ptp4l0-21swapper/309:21:543
134491520,4ptp4l0-21swapper/209:36:142
134491520,4ptp4l0-21swapper/010:38:540
134491520,3ptp4l0-21swapper/107:57:301
5094995124,6cyclictest33-21ksoftirqd/211:15:002
5094995120,4cyclictest33-21ksoftirqd/212:15:002
5094995119,4cyclictest33-21ksoftirqd/207:11:192
5094995118,4cyclictest33-21ksoftirqd/210:50:262
134491510,4ptp4l0-21swapper/111:33:261
134491510,4ptp4l0-21swapper/012:33:340
134491510,4ptp4l0-21swapper/012:12:120
134491510,4ptp4l0-21swapper/011:24:120
134491510,4ptp4l0-21swapper/011:19:490
134491510,4ptp4l0-21swapper/009:27:400
134491510,3ptp4l0-21swapper/307:51:153
134491510,3ptp4l0-21swapper/007:24:410
134491510,18ptp4l0-21swapper/111:02:481
5094995024,7cyclictest33-21ksoftirqd/208:45:322
509499502,3cyclictest121rcu_preempt12:15:132
5094995019,4cyclictest33-21ksoftirqd/207:37:342
5094995019,3cyclictest33-21ksoftirqd/207:50:212
5094995018,6cyclictest33-21ksoftirqd/210:45:152
5094995018,10cyclictest33-21ksoftirqd/210:10:392
5094995011,7cyclictest33-21ksoftirqd/208:19:372
153902500,4sleep10-21swapper/112:09:591
134491500,7ptp4l2756-21apt-get07:05:132
134491500,4ptp4l0-21swapper/311:27:093
134491500,4ptp4l0-21swapper/308:04:043
134491500,4ptp4l0-21swapper/111:54:401
134491500,4ptp4l0-21swapper/010:31:110
134491500,4ptp4l0-21swapper/008:23:260
134491500,4ptp4l0-21swapper/008:15:320
134491500,4ptp4l0-21swapper/008:02:400
5094994924,4cyclictest33-21ksoftirqd/208:31:362
5094994923,5cyclictest33-21ksoftirqd/212:29:152
5094994922,4cyclictest33-21ksoftirqd/209:13:462
5094994921,3cyclictest33-21ksoftirqd/209:31:332
5094994910,5cyclictest33-21ksoftirqd/209:25:222
134491490,4ptp4l0-21swapper/312:23:163
134491490,4ptp4l0-21swapper/211:02:132
134491490,4ptp4l0-21swapper/011:39:390
134491490,4ptp4l0-21swapper/010:16:010
134491490,10ptp4l0-21swapper/311:18:313
5094994825,5cyclictest33-21ksoftirqd/210:23:222
5094994821,6cyclictest33-21ksoftirqd/209:10:012
5094994817,3cyclictest33-21ksoftirqd/208:50:212
5094994814,5cyclictest33-21ksoftirqd/208:56:382
134491480,4ptp4l0-21swapper/312:03:313
134491480,4ptp4l0-21swapper/311:44:353
134491480,4ptp4l0-21swapper/310:13:543
134491480,4ptp4l0-21swapper/307:21:303
134491480,4ptp4l0-21swapper/012:39:500
134491480,4ptp4l0-21swapper/010:27:270
134491480,4ptp4l0-21swapper/010:10:560
134491480,4ptp4l0-21swapper/009:21:100
134491480,4ptp4l0-21swapper/008:10:310
134491480,4ptp4l0-21swapper/007:56:190
134491480,4ptp4l0-21swapper/007:17:210
134491480,3ptp4l0-21swapper/110:11:521
134491480,3ptp4l0-21swapper/008:35:170
134491480,2ptp4l0-21swapper/309:40:233
509499478,7cyclictest33-21ksoftirqd/210:06:402
509499473,2cyclictest121rcu_preempt11:18:592
5094994714,3cyclictest33-21ksoftirqd/209:21:322
5094994713,3cyclictest33-21ksoftirqd/211:28:432
5094994711,6cyclictest33-21ksoftirqd/208:05:142
134491470,5ptp4l0-21swapper/307:05:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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