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2026-03-02 - 08:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot1.osadl.org (updated Mon Mar 02, 2026 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314452740,4sleep10-21swapper/120:30:211
25744997331,9cyclictest41-21ksoftirqd/300:25:013
134491700,4ptp4l0-21swapper/022:04:570
25744996631,4cyclictest41-21ksoftirqd/322:35:173
25744996532,9cyclictest41-21ksoftirqd/321:15:123
25744996433,9cyclictest41-21ksoftirqd/323:50:153
25744996330,10cyclictest41-21ksoftirqd/321:40:263
25744996330,10cyclictest41-21ksoftirqd/321:40:263
25744996324,8cyclictest41-21ksoftirqd/300:35:213
220292630,2sleep222033-21cpuspeed_turbos23:40:132
25744996230,9cyclictest41-21ksoftirqd/323:30:203
25744996230,9cyclictest41-21ksoftirqd/323:25:153
25744996230,8cyclictest41-21ksoftirqd/321:15:023
25744996228,8cyclictest41-21ksoftirqd/320:35:223
25744996228,6cyclictest41-21ksoftirqd/320:10:133
25744996130,9cyclictest41-21ksoftirqd/321:05:003
25744996127,9cyclictest41-21ksoftirqd/323:05:163
25744996127,9cyclictest41-21ksoftirqd/323:05:163
25744996127,4cyclictest41-21ksoftirqd/322:05:263
25744996126,8cyclictest41-21ksoftirqd/321:28:453
25744996124,6cyclictest41-21ksoftirqd/300:05:243
25744996029,10cyclictest41-21ksoftirqd/319:35:223
25744996026,7cyclictest41-21ksoftirqd/320:25:283
134491600,4ptp4l0-21swapper/019:07:340
25744995928,4cyclictest41-21ksoftirqd/322:40:153
25744995926,9cyclictest41-21ksoftirqd/300:30:013
25744995827,8cyclictest41-21ksoftirqd/323:45:143
134491580,5ptp4l0-21swapper/020:55:180
134491580,4ptp4l0-21swapper/120:05:171
2574499575,7cyclictest22715-21seq23:40:193
25744995726,3cyclictest41-21ksoftirqd/323:15:193
25744995725,6cyclictest41-21ksoftirqd/323:35:173
25744995723,8cyclictest41-21ksoftirqd/323:12:003
134491570,3ptp4l11878-21/usr/sbin/munin21:00:242
134491570,3ptp4l0-21swapper/119:14:291
25744995627,3cyclictest41-21ksoftirqd/322:20:183
25744995624,9cyclictest41-21ksoftirqd/320:40:483
134491560,4ptp4l0-21swapper/021:30:230
134491560,3ptp4l0-21swapper/220:24:572
134491560,3ptp4l0-21swapper/022:40:150
134491560,3ptp4l0-21swapper/019:18:370
25744995528,7cyclictest41-21ksoftirqd/321:55:203
25744995522,8cyclictest41-21ksoftirqd/319:55:133
25744995522,8cyclictest41-21ksoftirqd/319:55:133
25744995521,6cyclictest41-21ksoftirqd/320:45:193
134491550,5ptp4l0-21swapper/020:23:250
134491550,3ptp4l0-21swapper/300:16:313
25744995421,7cyclictest41-21ksoftirqd/319:44:443
25744995420,7cyclictest41-21ksoftirqd/321:38:003
134491540,4ptp4l0-21swapper/119:05:171
134491540,3ptp4l0-21swapper/319:31:143
134491540,10ptp4l0-21swapper/019:25:170
2574499532,7cyclictest41-21ksoftirqd/321:10:013
2574499532,26cyclictest0-21swapper/322:14:083
134491530,4ptp4l0-21swapper/123:14:431
134491530,4ptp4l0-21swapper/121:45:351
134491530,4ptp4l0-21swapper/100:19:301
134491530,3ptp4l0-21swapper/200:35:232
2574499523,7cyclictest0-21swapper/322:30:253
2574499523,7cyclictest0-21swapper/319:10:213
25744995231,9cyclictest41-21ksoftirqd/322:15:253
2574499522,25cyclictest0-21swapper/321:48:383
134491520,4ptp4l0-21swapper/100:11:001
134491520,3ptp4l0-21swapper/222:35:392
134491520,3ptp4l0-21swapper/022:20:150
2574499512,7cyclictest0-21swapper/321:30:163
2574499512,7cyclictest0-21swapper/300:10:123
2574499512,27cyclictest0-21swapper/323:21:193
2574499512,25cyclictest0-21swapper/300:01:003
2574499512,22cyclictest0-21swapper/322:29:473
25744995118,6cyclictest41-21ksoftirqd/323:00:233
25744995118,6cyclictest41-21ksoftirqd/323:00:233
134491510,7ptp4l9-21ksoftirqd/019:35:090
134491510,4ptp4l0-21swapper/021:02:570
134491510,4ptp4l0-21swapper/019:40:160
134491510,3ptp4l0-21swapper/023:06:590
134491510,3ptp4l0-21swapper/023:06:590
134491510,3ptp4l0-21swapper/020:45:270
134491510,14ptp4l0-21swapper/220:35:012
134491510,11ptp4l0-21swapper/019:45:500
2574499504,2cyclictest41-21ksoftirqd/322:02:043
25744995038,3cyclictest41-21ksoftirqd/320:50:133
25744995038,3cyclictest41-21ksoftirqd/320:50:133
134491500,4ptp4l0-21swapper/219:17:442
134491500,4ptp4l0-21swapper/021:28:530
134491500,10ptp4l0-21swapper/020:04:020
2574499495,7cyclictest41-21ksoftirqd/320:20:233
2574499495,3cyclictest121rcu_preempt19:45:283
2574499495,2cyclictest41-21ksoftirqd/320:05:253
25744994916,7cyclictest41-21ksoftirqd/320:03:453
2574499490,8cyclictest41-21ksoftirqd/322:45:153
134491490,4ptp4l0-21swapper/223:10:492
134491490,4ptp4l0-21swapper/219:56:202
134491490,4ptp4l0-21swapper/219:56:202
134491490,4ptp4l0-21swapper/200:29:352
134491490,4ptp4l0-21swapper/123:15:501
134491490,3ptp4l0-21swapper/123:47:171
2574499484,7cyclictest41-21ksoftirqd/319:20:163
25744994830,10cyclictest41-21ksoftirqd/322:55:153
2574499482,7cyclictest0-21swapper/320:56:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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