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2026-03-13 - 18:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Fri Mar 13, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
989621720,7sleep20-21swapper/207:10:012
1829821360,5sleep3995599cyclictest09:45:233
134491750,7ptp4l0-21swapper/309:06:503
9953996731,8cyclictest25-21ksoftirqd/111:35:281
995299631,16cyclictest27302-21ls11:15:130
134491630,3ptp4l31373-21taskset12:32:023
182092610,3sleep218203-21phc2sys08:35:212
182092610,3sleep218203-21phc2sys08:35:212
134491600,5ptp4l0-21swapper/007:10:160
9953995930,6cyclictest25-21ksoftirqd/111:45:121
9953995926,4cyclictest25-21ksoftirqd/108:00:201
9953995922,9cyclictest25-21ksoftirqd/110:10:011
9953995922,9cyclictest25-21ksoftirqd/110:10:011
156072590,5sleep315612-21irqrtprio09:40:173
134491590,5ptp4l0-21swapper/211:55:152
995399585,9cyclictest25-21ksoftirqd/108:55:221
995399584,9cyclictest25-21ksoftirqd/110:30:231
9953995729,4cyclictest25-21ksoftirqd/111:20:211
9953995729,10cyclictest25-21ksoftirqd/107:20:001
9953995728,6cyclictest25-21ksoftirqd/108:40:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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