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2026-01-27 - 15:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Tue Jan 27, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
737021570,6sleep1200799cyclictest10:50:131
737021570,6sleep1200799cyclictest10:50:131
134491740,5ptp4l0-21swapper/207:05:562
93772620,4sleep0200699cyclictest09:45:140
134491600,4ptp4l0-21swapper/312:00:223
134491590,4ptp4l0-21swapper/110:23:221
134491580,4ptp4l0-21swapper/108:13:361
134491570,4ptp4l0-21swapper/112:30:121
134491560,3ptp4l0-21swapper/108:58:181
134491560,3ptp4l0-21swapper/108:29:261
134491560,3ptp4l0-21swapper/011:26:460
134491560,2ptp4l0-21swapper/009:30:280
134491550,4ptp4l0-21swapper/308:43:003
134491540,4ptp4l0-21swapper/307:28:343
134491540,3ptp4l0-21swapper/212:32:142
134491530,7ptp4l0-21swapper/010:15:200
134491530,4ptp4l0-21swapper/008:25:160
134491530,3ptp4l0-21swapper/009:25:190
134491530,3ptp4l0-21swapper/007:29:490
134491520,4ptp4l0-21swapper/310:00:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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