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2026-06-12 - 00:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Thu Jun 11, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1443621300,3sleep314430-21turbostat07:40:003
685997416,55cyclictest11895-21seq07:32:111
685996914,15cyclictest15283-21chrt12:19:311
685996912,17cyclictest1317-21runrttasks10:33:521
68599688,57cyclictest31474-21if_enp4s009:25:171
685996714,15cyclictest9793-21chrt09:48:161
68799668,15cyclictest31894-21iostat10:35:183
685996613,15cyclictest31239-21chrt11:41:411
685996612,12cyclictest884-21chrt10:39:101
685996611,16cyclictest1317-21runrttasks09:01:241
685996610,17cyclictest16708-21awk11:10:211
685996514,14cyclictest28206-21taskset08:06:541
685996514,14cyclictest16813-21chrt10:01:521
685996513,12cyclictest7808-21chrt10:52:341
685996512,16cyclictest1317-21runrttasks11:17:451
68599649,19cyclictest0-21swapper/111:28:501
685996415,16cyclictest2771-21chrt09:32:271
685996415,16cyclictest2771-21chrt09:32:271
685996413,10cyclictest1057-21taskset11:45:491
685996412,9cyclictest12837-21chrt12:12:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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