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2025-12-13 - 08:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Fri Dec 12, 2025 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191690,4ptp4l0-21swapper/119:20:251
174052690,4sleep00-21swapper/021:00:310
2847191660,3ptp4l10451-21meminfo21:55:261
2923799637,39cyclictest2847191ptp4l00:15:563
2847191630,4ptp4l29186-21iostat_ios23:45:201
2847191620,4ptp4l0-21swapper/219:05:082
2847191600,3ptp4l32664-21iostat_ios21:35:171
29234995825,7cyclictest9-21ksoftirqd/020:19:510
2847191580,5ptp4l0-21swapper/122:30:331
2847191560,3ptp4l0-21swapper/221:16:232
2847191560,3ptp4l0-21swapper/122:20:161
2847191560,3ptp4l0-21swapper/120:00:131
2847191560,3ptp4l0-21swapper/119:31:101
2847191560,3ptp4l0-21swapper/100:14:011
2847191550,4ptp4l0-21swapper/120:43:571
2847191550,4ptp4l0-21swapper/120:38:451
29237995424,17cyclictest41-21ksoftirqd/321:40:193
2847191540,17ptp4l5779-21sshd19:27:221
2847191540,12ptp4l0-21swapper/120:07:361
102142540,5sleep10-21swapper/119:35:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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