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2026-11-01 - 02:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Sat Oct 31, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
687221520,3sleep32045399cyclictest11:15:253
2097721390,5sleep30-21swapper/309:30:013
134491720,37ptp4l41-21ksoftirqd/307:50:273
137891684,19phc2sys0-21swapper/007:05:230
134491610,5ptp4l0-21swapper/010:55:200
134491610,4ptp4l22052-21ls07:10:271
134491610,4ptp4l0-21swapper/208:09:232
134491610,4ptp4l0-21swapper/208:09:232
134491610,4ptp4l0-21swapper/110:25:031
134491570,4ptp4l0-21swapper/209:04:142
134491570,4ptp4l0-21swapper/010:15:170
134491570,3ptp4l0-21swapper/111:50:131
134491570,10ptp4l0-21swapper/207:28:082
134491560,3ptp4l17580-21interrupts10:30:190
134491560,3ptp4l0-21swapper/009:55:150
134491550,4ptp4l0-21swapper/107:45:191
134491550,4ptp4l0-21swapper/011:35:190
134491550,3ptp4l0-21swapper/212:21:482
134491540,6ptp4l0-21swapper/312:03:403
134491540,4ptp4l0-21swapper/110:11:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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