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2025-09-13 - 06:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Sat Sep 13, 2025 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1982021800,6sleep01480999cyclictest20:30:010
533521520,6sleep31481299cyclictest22:15:183
80202770,4sleep31481299cyclictest23:30:213
2847191650,4ptp4l0-21swapper/320:45:233
2847191630,5ptp4l0-21swapper/122:25:271
2847191620,3ptp4l12070-21hddtemp_smartct23:40:160
2847191610,4ptp4l0-21swapper/223:54:322
2847191600,2ptp4l18719-21ls19:15:270
2847191590,3ptp4l0-21swapper/300:35:323
2847191590,3ptp4l0-21swapper/200:25:342
2847191590,3ptp4l0-21swapper/200:25:342
2847191580,4ptp4l0-21swapper/322:21:523
2847191580,4ptp4l0-21swapper/000:25:240
2847191580,4ptp4l0-21swapper/000:25:240
2847191580,3ptp4l0-21swapper/023:16:520
2847191580,2ptp4l0-21swapper/321:15:313
2847191570,4ptp4l0-21swapper/119:06:371
2847191570,3ptp4l0-21swapper/121:00:211
2847191560,3ptp4l0-21swapper/020:15:260
2847191550,3ptp4l32762-21threads19:45:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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