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2026-02-02 - 15:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 02, 2026 12:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285712930,5sleep10-21swapper/112:00:241
2273199747,65cyclictest0-21swapper/211:05:292
2273199731,3cyclictest0-21swapper/207:35:292
2273199727,63cyclictest0-21swapper/207:10:292
22730997235,7cyclictest25-21ksoftirqd/108:55:181
2273199716,63cyclictest0-21swapper/210:50:292
22730997128,8cyclictest25-21ksoftirqd/110:40:281
22730997128,8cyclictest25-21ksoftirqd/110:40:281
2273199702,66cyclictest0-21swapper/207:15:292
248742670,5sleep22273199cyclictest10:40:212
248742670,5sleep22273199cyclictest10:40:212
22730996632,8cyclictest25-21ksoftirqd/112:15:221
134491640,3ptp4l7918-21hddtemp_smartct08:55:160
22730996320,8cyclictest25-21ksoftirqd/112:25:241
22730996226,6cyclictest25-21ksoftirqd/112:05:171
22730996129,8cyclictest25-21ksoftirqd/107:30:011
22730996127,4cyclictest25-21ksoftirqd/111:10:181
22730996126,6cyclictest25-21ksoftirqd/111:15:131
22730996028,8cyclictest25-21ksoftirqd/109:28:101
22730996025,3cyclictest25-21ksoftirqd/108:50:241
22730996020,10cyclictest25-21ksoftirqd/108:20:211
134491600,5ptp4l25002-21ntp_states10:40:230
134491600,5ptp4l25002-21ntp_states10:40:230
134491600,4ptp4l0-21swapper/309:25:173
134491600,3ptp4l0-21swapper/012:05:000
22730995926,4cyclictest25-21ksoftirqd/109:45:201
22730995829,4cyclictest25-21ksoftirqd/108:30:251
22730995823,7cyclictest25-21ksoftirqd/110:55:111
22730995822,8cyclictest25-21ksoftirqd/110:11:311
134491580,3ptp4l0-21swapper/008:15:120
22730995727,8cyclictest25-21ksoftirqd/109:55:221
22730995727,7cyclictest25-21ksoftirqd/108:10:261
22730995725,3cyclictest25-21ksoftirqd/110:16:491
22730995723,10cyclictest25-21ksoftirqd/108:05:261
22730995720,4cyclictest25-21ksoftirqd/109:00:021
134491570,4ptp4l6680-21processes10:00:240
134491570,4ptp4l0-21swapper/011:13:170
134491570,3ptp4l0-21swapper/011:37:410
2273199568,46cyclictest0-21swapper/212:00:292
22730995627,3cyclictest25-21ksoftirqd/112:35:291
22730995626,6cyclictest25-21ksoftirqd/112:20:291
22730995626,5cyclictest25-21ksoftirqd/109:20:251
134491560,4ptp4l0-21swapper/010:05:260
134491560,4ptp4l0-21swapper/007:20:350
134491560,13ptp4l41-21ksoftirqd/311:59:193
22731995514,39cyclictest0-21swapper/209:55:092
22730995524,9cyclictest25-21ksoftirqd/107:30:151
22730995523,8cyclictest25-21ksoftirqd/109:30:181
134491550,3ptp4l0-21swapper/110:20:151
2273099545,8cyclictest25-21ksoftirqd/107:20:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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