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2026-02-24 - 13:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Tue Feb 24, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1471121700,5sleep33183999cyclictest22:00:143
31838997333,9cyclictest33-21ksoftirqd/222:15:012
31836997231,6cyclictest9-21ksoftirqd/020:05:270
3183799704,63cyclictest10889-21kworker/1:120:31:081
31838996731,3cyclictest33-21ksoftirqd/222:54:592
298972660,6sleep10-21swapper/119:05:131
298972660,6sleep10-21swapper/119:05:131
31838996527,5cyclictest33-21ksoftirqd/221:00:262
31836996533,5cyclictest9-21ksoftirqd/021:35:010
31836996429,6cyclictest9-21ksoftirqd/020:00:250
31838996330,5cyclictest33-21ksoftirqd/221:45:392
31838996329,5cyclictest33-21ksoftirqd/220:50:232
31838996328,6cyclictest33-21ksoftirqd/221:55:192
31836996329,6cyclictest9-21ksoftirqd/022:45:180
31836996328,5cyclictest9-21ksoftirqd/021:00:010
280252630,7sleep33183999cyclictest21:20:153
31838996257,2cyclictest321ktimersoftd/222:40:202
31838996231,5cyclictest33-21ksoftirqd/221:40:252
31838996230,5cyclictest33-21ksoftirqd/200:20:252
31836996223,4cyclictest9-21ksoftirqd/019:25:260
31838996131,4cyclictest33-21ksoftirqd/223:58:592
31838996129,3cyclictest33-21ksoftirqd/223:44:062
31838996128,4cyclictest33-21ksoftirqd/223:50:272
31838996128,3cyclictest33-21ksoftirqd/219:25:232
31836996126,5cyclictest9-21ksoftirqd/023:25:250
31836996126,5cyclictest9-21ksoftirqd/023:15:000
31836996125,5cyclictest9-21ksoftirqd/022:05:280
31836996123,5cyclictest9-21ksoftirqd/022:40:230
314132610,3sleep30-21swapper/322:35:213
31838996027,9cyclictest33-21ksoftirqd/223:50:002
31838996027,9cyclictest33-21ksoftirqd/219:40:272
31836996031,6cyclictest9-21ksoftirqd/000:20:160
31836996025,5cyclictest9-21ksoftirqd/019:40:010
134491600,3ptp4l0-21swapper/020:30:010
31838995929,9cyclictest33-21ksoftirqd/223:20:192
31838995922,7cyclictest33-21ksoftirqd/219:14:212
31838995918,7cyclictest33-21ksoftirqd/220:25:342
31836995928,5cyclictest9-21ksoftirqd/022:30:160
31836995927,5cyclictest9-21ksoftirqd/021:15:010
31838995823,6cyclictest33-21ksoftirqd/223:10:182
31838995822,6cyclictest33-21ksoftirqd/219:35:012
31838995821,4cyclictest33-21ksoftirqd/200:30:282
31836995827,5cyclictest9-21ksoftirqd/022:55:260
31836995824,5cyclictest9-21ksoftirqd/019:40:260
31836995822,5cyclictest9-21ksoftirqd/000:25:130
31836995821,4cyclictest9-21ksoftirqd/022:26:270
134491580,3ptp4l0-21swapper/121:10:281
31838995726,6cyclictest33-21ksoftirqd/219:15:592
31836995726,5cyclictest9-21ksoftirqd/023:55:240
31836995725,6cyclictest9-21ksoftirqd/000:10:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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