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2026-02-27 - 21:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Fri Feb 27, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18931996733,3cyclictest25-21ksoftirqd/109:00:001
134491620,5ptp4l0-21swapper/309:45:193
18931996132,8cyclictest25-21ksoftirqd/108:10:191
134491600,4ptp4l0-21swapper/011:25:180
18931995928,3cyclictest25-21ksoftirqd/111:50:181
18931995927,7cyclictest25-21ksoftirqd/108:55:001
134491590,4ptp4l0-21swapper/209:20:122
134491590,4ptp4l0-21swapper/111:35:171
134491590,3ptp4l121rcu_preempt11:45:143
134491590,25ptp4l9-21ksoftirqd/008:50:110
18931995828,8cyclictest25-21ksoftirqd/109:10:191
18931995828,7cyclictest25-21ksoftirqd/110:29:591
18931995828,4cyclictest25-21ksoftirqd/111:26:251
18931995826,8cyclictest25-21ksoftirqd/107:50:211
18931995824,8cyclictest25-21ksoftirqd/109:45:201
18931995822,6cyclictest25-21ksoftirqd/107:35:151
134491580,4ptp4l0-21swapper/108:00:521
18931995729,7cyclictest25-21ksoftirqd/111:23:361
18931995726,4cyclictest25-21ksoftirqd/107:32:541
18931995725,8cyclictest25-21ksoftirqd/112:25:151
134491570,12ptp4l17935-21python07:05:242
18931995628,6cyclictest25-21ksoftirqd/112:21:041
18931995628,3cyclictest25-21ksoftirqd/108:07:201
18931995627,3cyclictest25-21ksoftirqd/109:43:271
18931995627,3cyclictest25-21ksoftirqd/109:43:271
18931995625,9cyclictest25-21ksoftirqd/112:30:231
18931995625,3cyclictest25-21ksoftirqd/109:25:251
18931995620,4cyclictest25-21ksoftirqd/108:35:271
18931995619,4cyclictest25-21ksoftirqd/110:10:261
134491560,4ptp4l0-21swapper/311:35:133
134491560,4ptp4l0-21swapper/210:20:382
18931995527,7cyclictest25-21ksoftirqd/110:23:301
18931995527,6cyclictest25-21ksoftirqd/109:50:451
18931995526,3cyclictest25-21ksoftirqd/111:10:121
18931995525,5cyclictest25-21ksoftirqd/109:30:311
18931995518,9cyclictest25-21ksoftirqd/110:45:181
134491550,5ptp4l0-21swapper/107:40:121
134491550,4ptp4l0-21swapper/012:15:280
18931995427,7cyclictest25-21ksoftirqd/107:11:271
18931995427,4cyclictest25-21ksoftirqd/107:17:171
18931995426,4cyclictest25-21ksoftirqd/110:53:191
18931995425,3cyclictest25-21ksoftirqd/109:05:271
18931995425,11cyclictest25-21ksoftirqd/107:29:171
18931995425,11cyclictest25-21ksoftirqd/107:29:171
18931995424,3cyclictest25-21ksoftirqd/108:31:271
18931995424,3cyclictest25-21ksoftirqd/108:31:271
18931995419,8cyclictest25-21ksoftirqd/110:34:591
18931995418,4cyclictest25-21ksoftirqd/111:40:131
134491540,4ptp4l0-21swapper/109:59:241
134491540,3ptp4l0-21swapper/011:02:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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