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2026-02-28 - 21:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Sat Feb 28, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2293221690,6sleep11342799cyclictest09:45:271
239621590,6sleep11342799cyclictest11:20:261
1342999782,32cyclictest0-21swapper/309:05:153
1342999742,30cyclictest0-21swapper/309:10:133
134491690,4ptp4l7201-21hddtemp_smartct08:05:151
13429996733,8cyclictest41-21ksoftirqd/310:10:003
134491660,4ptp4l0-21swapper/107:20:251
13429996532,7cyclictest41-21ksoftirqd/308:35:143
13429996530,9cyclictest41-21ksoftirqd/308:10:153
13429996529,10cyclictest41-21ksoftirqd/309:00:133
13429996527,5cyclictest41-21ksoftirqd/312:35:003
13429996431,8cyclictest41-21ksoftirqd/310:50:003
13429996429,4cyclictest41-21ksoftirqd/308:50:243
13429996328,8cyclictest41-21ksoftirqd/308:30:173
13429996328,8cyclictest41-21ksoftirqd/308:30:163
13429996328,8cyclictest41-21ksoftirqd/307:29:593
13429996328,7cyclictest41-21ksoftirqd/312:10:053
13429996232,9cyclictest41-21ksoftirqd/308:20:263
13429996230,4cyclictest41-21ksoftirqd/311:15:273
13429996227,8cyclictest41-21ksoftirqd/311:00:183
13429996227,8cyclictest41-21ksoftirqd/309:55:163
13429996225,4cyclictest41-21ksoftirqd/307:35:253
13429996131,3cyclictest41-21ksoftirqd/307:10:233
13429996131,3cyclictest41-21ksoftirqd/307:10:233
13429996125,7cyclictest41-21ksoftirqd/311:50:193
134491600,4ptp4l0-21swapper/107:15:511
13429996028,9cyclictest41-21ksoftirqd/307:30:143
13429996028,6cyclictest41-21ksoftirqd/311:45:203
13429996028,6cyclictest41-21ksoftirqd/311:45:203
13429996023,8cyclictest41-21ksoftirqd/311:32:383
134491590,4ptp4l0-21swapper/210:20:062
13429995930,9cyclictest41-21ksoftirqd/311:35:003
134491580,4ptp4l0-21swapper/210:05:212
134491580,4ptp4l0-21swapper/011:17:130
1342999586,8cyclictest121rcu_preempt12:05:293
13429995831,7cyclictest41-21ksoftirqd/308:25:143
13429995824,7cyclictest41-21ksoftirqd/310:24:593
13429995823,4cyclictest41-21ksoftirqd/311:10:113
134491570,3ptp4l0-21swapper/111:30:231
134491570,15ptp4l26130-21df09:55:130
13429995731,3cyclictest41-21ksoftirqd/308:40:153
13429995727,8cyclictest41-21ksoftirqd/312:01:263
13429995721,6cyclictest41-21ksoftirqd/307:15:203
13429995721,5cyclictest41-21ksoftirqd/308:45:183
134491560,4ptp4l0-21swapper/110:30:121
1342999565,9cyclictest41-21ksoftirqd/309:35:253
13429995627,8cyclictest41-21ksoftirqd/310:30:123
134491550,3ptp4l27327-21df_inode12:15:141
134491550,3ptp4l0-21swapper/111:00:161
134491550,3ptp4l0-21swapper/009:50:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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