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2026-02-19 - 22:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Thu Feb 19, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1360321690,7sleep32880999cyclictest11:15:123
727321530,2sleep32880999cyclictest08:40:243
727321530,2sleep32880999cyclictest08:40:243
2880899743,69cyclictest0-21swapper/208:40:282
2880899743,69cyclictest0-21swapper/208:40:282
2880899651,31cyclictest21878-21taskset09:11:532
28806996530,6cyclictest9-21ksoftirqd/011:40:250
28806996330,6cyclictest9-21ksoftirqd/008:50:260
2880899621,29cyclictest16117-21date12:30:002
28806996228,5cyclictest9-21ksoftirqd/007:25:170
28806996224,6cyclictest9-21ksoftirqd/011:05:180
28806996129,6cyclictest9-21ksoftirqd/009:15:270
28806996129,6cyclictest9-21ksoftirqd/009:15:270
28806996128,5cyclictest9-21ksoftirqd/010:10:130
28806996127,6cyclictest9-21ksoftirqd/008:40:270
28806996127,6cyclictest9-21ksoftirqd/008:40:270
28806996126,6cyclictest9-21ksoftirqd/009:05:160
28806996029,6cyclictest9-21ksoftirqd/011:50:270
28806996028,6cyclictest9-21ksoftirqd/008:15:170
28806996027,5cyclictest9-21ksoftirqd/011:50:000
134491600,4ptp4l0-21swapper/207:14:522
28806995931,5cyclictest9-21ksoftirqd/011:55:160
28806995931,5cyclictest9-21ksoftirqd/011:55:160
28806995929,5cyclictest9-21ksoftirqd/008:30:200
28806995928,5cyclictest9-21ksoftirqd/009:00:130
134491590,3ptp4l0-21swapper/209:23:322
134491590,3ptp4l0-21swapper/108:23:131
28806995831,7cyclictest9-21ksoftirqd/007:10:220
28806995830,5cyclictest9-21ksoftirqd/010:55:160
28806995827,5cyclictest9-21ksoftirqd/009:45:250
28806995826,5cyclictest9-21ksoftirqd/010:50:180
28806995821,5cyclictest9-21ksoftirqd/007:55:240
134491580,4ptp4l0-21swapper/211:59:012
134491580,4ptp4l0-21swapper/211:59:012
134491580,4ptp4l0-21swapper/010:35:500
134491580,3ptp4l0-21swapper/111:10:251
134491580,3ptp4l0-21swapper/107:45:271
28806995726,5cyclictest9-21ksoftirqd/008:55:250
28806995725,5cyclictest9-21ksoftirqd/008:35:130
28806995723,6cyclictest9-21ksoftirqd/010:40:140
28806995723,5cyclictest9-21ksoftirqd/009:35:150
28806995720,5cyclictest9-21ksoftirqd/012:05:260
134491570,4ptp4l0-21swapper/208:05:272
134491570,3ptp4l0-21swapper/110:55:171
134491570,3ptp4l0-21swapper/108:09:071
2880899567,18cyclictest28502-21sed08:15:262
28806995627,5cyclictest9-21ksoftirqd/007:30:140
28806995626,6cyclictest9-21ksoftirqd/011:30:150
28806995624,5cyclictest9-21ksoftirqd/007:40:140
28806995623,5cyclictest9-21ksoftirqd/011:15:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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