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2026-02-09 - 16:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 09, 2026 12:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3169199758,20cyclictest0-21swapper/211:15:002
31691997315,10cyclictest21204-21chrt11:26:452
31691997310,60cyclictest23860-21latency08:00:192
31691997215,19cyclictest4947-21chrt10:51:112
31691997114,11cyclictest16982-21chrt12:28:522
31691997014,12cyclictest20821-21taskset09:07:452
31691996914,12cyclictest14187-21chrt12:20:572
31691996914,11cyclictest8276-21chrt07:26:202
31691996912,10cyclictest17462chrt08:24:092
3169199683,63cyclictest0-21swapper/211:55:292
31691996814,11cyclictest25528-21chrt09:19:042
31691996814,10cyclictest3389-21taskset07:15:412
31691996813,11cyclictest3562-21irqrtprio09:40:182
31691996813,11cyclictest23994-21/usr/sbin/munin11:35:152
31691996714,11cyclictest17855-21chrt08:57:272
31691996714,11cyclictest16775-21taskset11:19:152
3169199669,16cyclictest21694-21/usr/sbin/munin11:30:172
31691996610,11cyclictest26836-21memory09:20:232
31691996517,17cyclictest21546-21taskset12:35:412
31691996517,11cyclictest20094-21taskset07:51:382
31691996510,9cyclictest18379-21grep09:00:132
31691996510,11cyclictest23741-21cat10:25:012
3169199649,11cyclictest8781-21latency_hist08:40:012
3169199649,11cyclictest6345-21latency_hist07:25:002
3169199648,16cyclictest0-21swapper/212:30:192
31691996418,10cyclictest9704-21taskset12:12:482
31691996414,11cyclictest4146-21taskset08:29:412
134491640,5ptp4l0-21swapper/311:30:103
134491640,20ptp4l0-21swapper/310:45:203
134491640,20ptp4l0-21swapper/310:45:203
3169199638,17cyclictest0-21swapper/211:05:172
3169199634,57cyclictest0-21swapper/209:25:282
31691996319,9cyclictest5162-21chrt12:03:322
31691996314,11cyclictest1032-21runrttasks07:11:022
31691996313,11cyclictest62512sleep208:32:122
31691996311,16cyclictest26291-21/usr/sbin/munin10:30:292
31691996311,11cyclictest27100-21irqrtprio11:40:192
31691996218,10cyclictest25569-21chrt10:26:332
31691996212,9cyclictest16168-21df07:45:132
31691996212,11cyclictest110242sleep207:34:182
189612620,4sleep118963-21latency_hist10:15:001
3169199609,17cyclictest31567-21irqrtprio11:50:192
3169199608,11cyclictest31497-21cut09:30:192
3169199603,54cyclictest10488-21/usr/sbin/munin08:40:292
31691996017,10cyclictest26984-21taskset08:06:122
3169199600,17cyclictest0-21swapper/211:20:132
270672600,5sleep30-21swapper/309:20:263
3169199598,8cyclictest13291-21ntpq10:00:202
3169199598,11cyclictest22199-21missed_timers09:10:162
31691995818,10cyclictest20956-21chrt10:16:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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