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2026-02-16 - 21:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Mon Feb 16, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2234722480,4sleep322345-21od07:09:383
436221870,5sleep04360-21tee07:08:550
1863521850,4sleep2311rcuc/207:08:082
2619121840,7sleep126182-21sh07:07:471
1022399822,78cyclictest21633-21kworker/1:110:15:091
10932730,4sleep21099-21od07:12:532
1022399728,62cyclictest21633-21kworker/1:108:50:491
10225996930,8cyclictest41-21ksoftirqd/307:10:393
134491670,15ptp4l0-21swapper/208:24:092
10225996731,8cyclictest41-21ksoftirqd/311:50:013
10225996632,8cyclictest41-21ksoftirqd/307:25:003
10225996531,6cyclictest41-21ksoftirqd/310:10:153
10225996523,7cyclictest41-21ksoftirqd/312:30:273
134491640,3ptp4l0-21swapper/208:45:222
10225996430,7cyclictest41-21ksoftirqd/312:20:143
134491630,5ptp4l0-21swapper/007:45:140
134491630,5ptp4l0-21swapper/007:45:130
10225996332,6cyclictest41-21ksoftirqd/310:00:163
10225996324,7cyclictest41-21ksoftirqd/308:39:273
134491620,4ptp4l8430-21/usr/sbin/munin08:25:230
10225996233,4cyclictest41-21ksoftirqd/310:15:233
10225996230,6cyclictest41-21ksoftirqd/309:40:003
10225996225,6cyclictest41-21ksoftirqd/310:37:243
10225996132,7cyclictest41-21ksoftirqd/309:50:193
10225996131,8cyclictest41-21ksoftirqd/311:15:153
10225996125,8cyclictest41-21ksoftirqd/308:20:233
10225996122,8cyclictest41-21ksoftirqd/310:50:163
10225996119,4cyclictest41-21ksoftirqd/311:00:163
10225996029,9cyclictest41-21ksoftirqd/309:05:143
10225996028,9cyclictest41-21ksoftirqd/308:55:243
10225996024,4cyclictest41-21ksoftirqd/307:55:183
10223996013,45cyclictest21633-21kworker/1:110:02:081
134491590,4ptp4l0-21swapper/012:04:110
10225995928,8cyclictest41-21ksoftirqd/309:00:193
10225995927,7cyclictest41-21ksoftirqd/309:25:003
10225995924,4cyclictest41-21ksoftirqd/307:35:253
10225995921,5cyclictest41-21ksoftirqd/309:35:003
10225995920,6cyclictest41-21ksoftirqd/310:55:243
134491580,4ptp4l0-21swapper/208:26:332
10225995827,3cyclictest41-21ksoftirqd/311:30:183
10225995827,10cyclictest41-21ksoftirqd/307:30:173
10225995823,7cyclictest41-21ksoftirqd/312:00:163
10225995820,7cyclictest41-21ksoftirqd/307:45:003
10225995820,11cyclictest41-21ksoftirqd/310:34:363
10223995811,45cyclictest14693-21kworker/1:212:07:091
135372570,4sleep313540-21latency12:05:193
134491570,4ptp4l0-21swapper/210:48:082
134491570,3ptp4l0-21swapper/310:27:403
10225995724,8cyclictest41-21ksoftirqd/308:00:013
10225995723,7cyclictest41-21ksoftirqd/312:15:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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