You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-28 - 10:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Thu May 28, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299462800,5sleep00-21swapper/021:15:260
55432690,5sleep00-21swapper/022:45:000
2596996728,4cyclictest41-21ksoftirqd/321:55:013
259699632,42cyclictest0-21swapper/322:15:273
2595996233,4cyclictest33-21ksoftirqd/222:07:592
2596996016,9cyclictest41-21ksoftirqd/321:40:003
165552600,3sleep216559-21cpuspeed19:40:122
259699592,34cyclictest0-21swapper/321:57:483
2595995927,3cyclictest33-21ksoftirqd/223:30:262
134491590,4ptp4l0-21swapper/222:00:182
134491590,4ptp4l0-21swapper/219:35:182
134491590,4ptp4l0-21swapper/019:30:320
2596995850,6cyclictest0-21swapper/321:45:183
2595995827,4cyclictest33-21ksoftirqd/223:20:202
2595995823,6cyclictest33-21ksoftirqd/219:50:122
134491580,4ptp4l0-21swapper/200:35:272
134491580,3ptp4l0-21swapper/320:00:533
2595995724,8cyclictest33-21ksoftirqd/219:20:002
259699562,34cyclictest0-21swapper/320:37:313
259699560,6cyclictest23915-21latency_hist22:15:003
2595995625,4cyclictest33-21ksoftirqd/223:25:262
134491560,3ptp4l0-21swapper/219:29:572
2595995529,18cyclictest33-21ksoftirqd/222:00:012
2595995526,4cyclictest33-21ksoftirqd/221:20:262
2595995525,8cyclictest33-21ksoftirqd/221:40:002
2595995525,4cyclictest33-21ksoftirqd/223:10:132
2595995525,4cyclictest33-21ksoftirqd/220:30:282
134491550,4ptp4l0-21swapper/021:55:260
134491550,3ptp4l28466-21latency_hist20:05:002
2595995414,7cyclictest33-21ksoftirqd/220:05:252
259699533,6cyclictest11655-21latency_hist19:30:003
259699530,6cyclictest41-21ksoftirqd/322:30:153
259699530,6cyclictest401ktimersoftd/320:00:003
134491530,4ptp4l0-21swapper/219:55:072
134491530,3ptp4l0-21swapper/221:45:322
259699524,9cyclictest41-21ksoftirqd/323:10:273
259699522,6cyclictest0-21swapper/322:50:263
2596995219,8cyclictest41-21ksoftirqd/319:45:123
259699521,6cyclictest29228-21irqrtprio20:05:183
259699520,6cyclictest41-21ksoftirqd/322:35:273
259699520,6cyclictest31284-21tune2fs21:20:143
259699520,5cyclictest9294-21latency_hist19:25:013
2595995223,4cyclictest33-21ksoftirqd/223:40:002
2595995222,3cyclictest33-21ksoftirqd/221:40:182
134491520,4ptp4l0-21swapper/200:26:382
134491520,3ptp4l0-21swapper/123:52:201
259699515,8cyclictest41-21ksoftirqd/323:30:263
2596995143,6cyclictest0-21swapper/320:15:183
259699512,6cyclictest0-21swapper/321:25:243
259699512,6cyclictest0-21swapper/320:49:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional