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2026-01-24 - 01:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot1.osadl.org (updated Fri Jan 23, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
576521560,3sleep0542499cyclictest07:10:160
542699762,33cyclictest0-21swapper/207:50:192
542699762,32cyclictest0-21swapper/208:00:242
134491750,12ptp4l401ktimersoftd/309:45:143
134491750,12ptp4l401ktimersoftd/309:45:143
5426996731,9cyclictest33-21ksoftirqd/210:57:222
5426996528,6cyclictest33-21ksoftirqd/210:43:062
5426996329,5cyclictest33-21ksoftirqd/211:30:132
5426996329,5cyclictest33-21ksoftirqd/207:35:192
134491630,21ptp4l27486-21iostat_ios07:55:190
5426996231,9cyclictest33-21ksoftirqd/209:55:282
5426996229,6cyclictest33-21ksoftirqd/208:20:172
5426996127,6cyclictest33-21ksoftirqd/208:05:192
5426996029,3cyclictest33-21ksoftirqd/207:25:282
542599605,11cyclictest4919-21sed09:25:171
542599604,11cyclictest8746-21date07:15:171
134491600,4ptp4l0-21swapper/310:46:353
134491600,3ptp4l19140-21memory09:55:220
542699592,30cyclictest0-21swapper/210:14:132
542599596,9cyclictest14718-21date07:30:001
542599596,10cyclictest3061-21cat08:10:271
542599595,10cyclictest13474-21cat11:15:171
542599594,10cyclictest15497-21latency_hist12:35:011
134491590,5ptp4l0-21swapper/012:35:140
134491590,5ptp4l0-21swapper/007:34:480
5426995825,5cyclictest33-21ksoftirqd/207:15:262
542699582,32cyclictest0-21swapper/211:23:362
542599589,12cyclictest0-21swapper/108:36:361
542599588,9cyclictest16841-21phc2sys08:40:231
542599585,11cyclictest20601-21grep08:50:151
134491580,3ptp4l0-21swapper/110:50:001
542699573,33cyclictest0-21swapper/208:37:342
542699572,9cyclictest33-21ksoftirqd/210:30:002
5426995728,3cyclictest33-21ksoftirqd/207:34:242
542699572,30cyclictest0-21swapper/209:10:362
542599577,11cyclictest4030-21latency_hist09:25:001
542599577,11cyclictest15954-21sed11:20:181
542599577,10cyclictest29329-21sort09:10:001
542599575,12cyclictest11904-21sed09:40:171
542599574,12cyclictest24849-21df_abs07:50:131
542699563,34cyclictest0-21swapper/207:56:462
542599566,14cyclictest10886-21/usr/sbin/munin12:20:261
542599566,11cyclictest0-21swapper/107:45:151
542599565,9cyclictest10717-21sed12:20:001
134491560,4ptp4l0-21swapper/009:33:360
134491560,3ptp4l0-21swapper/209:33:242
134491560,3ptp4l0-21swapper/012:00:140
5426995525,5cyclictest33-21ksoftirqd/208:40:212
542699552,31cyclictest0-21swapper/211:53:432
5426995521,6cyclictest33-21ksoftirqd/209:00:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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