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2025-11-18 - 20:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Nov 18, 2025 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191237170,22phc2sys0-21swapper/307:06:183
300842213164,22sleep10-21swapper/107:08:131
300232205172,22sleep20-21swapper/207:07:262
280732203169,23sleep00-21swapper/007:05:010
2631521370,4sleep13052899cyclictest11:30:031
3052899660,25cyclictest5155-21tail09:35:321
3052899590,30cyclictest1975-21dpkg08:25:151
3052899580,23cyclictest22886-21expr11:20:281
3052799587,20cyclictest1900-21cut09:30:210
3052799586,15cyclictest17670-21cut08:55:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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