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2026-09-11 - 23:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Sep 11, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
162762228168,49sleep10-21swapper/107:06:391
139491224164,49phc2sys0-21swapper/307:06:253
163122208165,32sleep20-21swapper/207:07:082
163622202169,22sleep00-21swapper/007:07:460
16835996932,5cyclictest25-21ksoftirqd/107:20:001
16835996730,10cyclictest25-21ksoftirqd/110:20:001
16835996730,10cyclictest25-21ksoftirqd/110:20:001
16835996332,4cyclictest25-21ksoftirqd/109:20:001
16835996332,4cyclictest25-21ksoftirqd/109:19:591
22822610,1sleep22285-21cut10:00:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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