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2025-12-06 - 22:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Dec 06, 2025 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191220128,80phc2sys0-21swapper/307:05:173
60162203168,23sleep00-21swapper/007:07:230
59312203170,22sleep20-21swapper/207:06:172
59302202169,22sleep10-21swapper/107:06:151
2921821850,6sleep1651499cyclictest11:20:001
136991690,1ptp4l401ktimersoftd/310:38:463
136991650,1ptp4l401ktimersoftd/308:11:433
320402580,1sleep10-21swapper/109:10:151
136991550,1ptp4l401ktimersoftd/310:05:163
186562500,2sleep00-21swapper/012:05:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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