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2025-06-29 - 00:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Jun 28, 2025 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191235171,20phc2sys0-21swapper/307:08:043
200022206172,23sleep00-21swapper/007:06:000
200092205172,22sleep20-21swapper/207:06:062
199712204169,23sleep10-21swapper/107:05:381
2060899831,80cyclictest23836-21kworker/2:112:10:282
136991820,1ptp4l391rcuc/310:40:163
20609996230,5cyclictest41-21ksoftirqd/310:30:173
20609996228,5cyclictest41-21ksoftirqd/312:40:013
20609996227,7cyclictest41-21ksoftirqd/309:50:203
20609996225,9cyclictest41-21ksoftirqd/311:15:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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