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2026-05-15 - 15:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri May 15, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491239171,23phc2sys0-21swapper/307:09:323
325582203169,23sleep10-21swapper/107:09:271
304362203170,22sleep20-21swapper/207:05:022
324202201167,23sleep00-21swapper/007:07:450
1394918363,11phc2sys0-21swapper/307:10:013
290322590,4sleep30-21swapper/310:25:003
134491580,1getstats0-21swapper/308:00:273
316312490,2sleep20-21swapper/211:35:242
279442480,2sleep00-21swapper/010:20:200
134491480,1getstats0-21swapper/311:15:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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