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2025-12-02 - 21:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Dec 02, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311312206172,22sleep10-21swapper/107:06:381
137191206172,22phc2sys0-21swapper/307:05:343
311892203169,23sleep20-21swapper/207:07:232
312222202167,23sleep00-21swapper/007:07:490
313952163125,13sleep20-21swapper/207:10:002
1776621380,6sleep33169099cyclictest07:45:273
3168799658,17cyclictest0-21swapper/009:10:180
31687996514,10cyclictest27865-21ls08:10:010
31687996513,9cyclictest14070-21fschecks_count07:40:150
31687996510,11cyclictest3652-21fschecks_count10:40:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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