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2025-11-22 - 23:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Nov 22, 2025 12:46:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
254562204169,23sleep10-21swapper/107:08:371
137191204170,22phc2sys0-21swapper/307:05:523
254942203170,22sleep20-21swapper/207:09:062
254922202169,22sleep00-21swapper/007:09:040
2586999576,11cyclictest6166-21sh12:05:003
2586999576,11cyclictest6166-21sh12:05:003
80032550,2sleep00-21swapper/007:40:000
283012550,2sleep20-21swapper/211:40:282
2586999555,10cyclictest7486-21sed12:05:223
2586999544,11cyclictest18086-21cat10:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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