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2025-11-15 - 17:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Nov 15, 2025 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1817322240,16sleep10-21swapper/107:05:141
198492200166,23sleep20-21swapper/207:06:202
137191200166,23phc2sys0-21swapper/307:09:553
200912196163,22sleep00-21swapper/007:09:270
1097921300,3sleep12043799cyclictest10:10:161
2043699670,22cyclictest11428-21fschecks_count09:05:180
20436996512,18cyclictest5623-21sed07:45:200
2043699649,24cyclictest16862-21cstates11:30:180
2043699640,21cyclictest15678-21mailstats11:25:270
2043699620,21cyclictest21015-21grep09:25:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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