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2025-11-28 - 03:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Nov 27, 2025 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
221302220171,37sleep20-21swapper/207:08:032
137191208174,22phc2sys0-21swapper/307:06:373
221852199166,22sleep00-21swapper/007:08:450
220322199165,23sleep10-21swapper/107:06:441
976321640,5sleep12258399cyclictest10:05:001
1933921580,4sleep32258599cyclictest09:15:193
3062921360,4sleep12258399cyclictest11:55:161
56462680,2sleep10-21swapper/112:10:161
22583996836,3cyclictest25-21ksoftirqd/112:20:001
22583995828,3cyclictest25-21ksoftirqd/107:15:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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