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2025-12-30 - 04:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Dec 30, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110792203170,22sleep30-21swapper/319:07:173
111982201168,22sleep20-21swapper/219:08:492
111082200167,22sleep00-21swapper/019:07:380
110242200168,21sleep10-21swapper/119:06:391
1945421700,6sleep31158699cyclictest23:55:233
2898121500,7sleep21158499cyclictest00:15:202
1393911080,1ptp4l15076-21ls19:15:223
139391720,1ptp4l401ktimersoftd/321:05:183
11582996231,7cyclictest9-21ksoftirqd/023:10:000
11582996126,3cyclictest9-21ksoftirqd/019:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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