You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-09-13 - 16:38
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Sep 13, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62232207174,22sleep20-21swapper/207:06:302
61922205171,23sleep10-21swapper/107:06:051
137191204171,22phc2sys0-21swapper/307:06:173
64272202171,20sleep00-21swapper/007:09:090
91021500,6sleep0679299cyclictest09:10:290
2653721490,6sleep0679299cyclictest12:20:200
6793995928,11cyclictest25-21ksoftirqd/111:10:261
6793995718,7cyclictest25-21ksoftirqd/110:30:311
6793995718,7cyclictest25-21ksoftirqd/110:30:311
6793995621,7cyclictest25-21ksoftirqd/112:05:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional