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2025-11-19 - 21:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Nov 19, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191205171,23phc2sys0-21swapper/307:08:553
186762203169,22sleep20-21swapper/207:09:062
186742201167,23sleep00-21swapper/007:09:040
186702201168,22sleep10-21swapper/107:09:011
105472610,3sleep30-21swapper/308:00:013
136991570,1ptp4l401ktimersoftd/308:25:223
26412560,4sleep30-21swapper/307:40:273
59298470,9rtkit-daemon0-21swapper/212:02:442
19042994639,4cyclictest16321-21cat09:19:593
59298440,12rtkit-daemon0-21swapper/210:20:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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