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2025-08-21 - 21:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 21, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239512224150,63sleep10-21swapper/107:06:581
238452206172,22sleep30-21swapper/307:05:363
238442205172,22sleep20-21swapper/207:05:362
240892203170,22sleep00-21swapper/007:08:460
279621630,1sleep30-21swapper/312:00:223
2771021590,4sleep12447899cyclictest10:35:261
225452750,23sleep09-21ksoftirqd/011:35:120
24479997034,5cyclictest33-21ksoftirqd/208:20:002
24479997034,5cyclictest33-21ksoftirqd/208:20:002
24479996432,4cyclictest33-21ksoftirqd/208:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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