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2026-06-05 - 18:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Jun 05, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206172,22phc2sys0-21swapper/307:06:023
173232204171,22sleep10-21swapper/107:08:281
172282203170,22sleep20-21swapper/207:07:172
173222200167,22sleep00-21swapper/007:08:270
17739996120,7cyclictest9-21ksoftirqd/011:15:250
17739996119,8cyclictest9-21ksoftirqd/009:10:210
17739996027,4cyclictest9-21ksoftirqd/010:50:250
17739995924,4cyclictest9-21ksoftirqd/009:30:120
17739995923,4cyclictest9-21ksoftirqd/012:15:210
17739995922,5cyclictest9-21ksoftirqd/008:30:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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