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2025-12-15 - 12:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 15, 2025 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
298052217186,21sleep10-21swapper/119:06:311
279672215179,25sleep30-21swapper/319:05:203
299082212180,21sleep20-21swapper/219:07:432
279692212179,22sleep00-21swapper/019:05:200
3218721550,4sleep23037899cyclictest19:10:482
3037899643,21cyclictest370-21latency_hist23:44:592
3037899636,15cyclictest549-21in:imuxsock20:20:182
3037899615,15cyclictest449-21dbus-daemon22:20:022
3037899595,16cyclictest207-21systemd-journal23:05:522
3037899586,9cyclictest22818-21cat23:20:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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