You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-12-03 - 22:00
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Dec 03, 2025 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287312208169,28sleep20-21swapper/207:06:072
137191206172,22phc2sys0-21swapper/307:08:543
287512202169,22sleep10-21swapper/107:06:221
289662200167,22sleep00-21swapper/007:09:020
315521860,5sleep12933599cyclictest09:35:251
290432163125,13sleep20-21swapper/207:10:012
29336996811,16cyclictest16206-21cat10:05:002
29336996811,16cyclictest16206-21cat10:05:002
29336996612,16cyclictest32713-21irqstats07:15:212
29336996510,15cyclictest6384-21latency_hist09:45:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional