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2026-01-07 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 07, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
72242228162,21sleep30-21swapper/319:07:073
71382199165,23sleep20-21swapper/219:06:052
73402198165,22sleep10-21swapper/119:08:381
71942198163,23sleep00-21swapper/019:06:430
774399800,78cyclictest2080-21kworker/3:223:37:133
7742997833,8cyclictest33-21ksoftirqd/222:40:012
7742997833,8cyclictest33-21ksoftirqd/222:40:012
7741996832,7cyclictest25-21ksoftirqd/120:45:001
139391650,1ptp4l401ktimersoftd/323:25:163
7741996430,7cyclictest25-21ksoftirqd/120:05:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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