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2025-11-08 - 17:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sat Nov 08, 2025 12:45:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191210165,33phc2sys0-21swapper/307:09:133
304692201168,22sleep00-21swapper/007:08:090
304662197163,23sleep20-21swapper/207:08:072
302892197164,22sleep10-21swapper/107:05:491
1103421570,4sleep33092099cyclictest10:55:293
238422710,5sleep1478-21dbus-daemon12:30:251
71242700,7sleep33092099cyclictest08:35:013
94122630,2sleep33092099cyclictest09:45:203
136991630,1ptp4l401ktimersoftd/307:16:083
136991580,1ptp4l401ktimersoftd/312:13:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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