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2026-08-29 - 00:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Aug 28, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9332231169,51sleep20-21swapper/207:07:312
139491226163,51phc2sys0-21swapper/307:09:403
8182206172,22sleep10-21swapper/107:06:011
8742203170,22sleep00-21swapper/007:06:450
212972590,2sleep121302-21irqrtprio07:50:181
33512560,2sleep00-21swapper/011:40:200
139391520,1ptp4l401ktimersoftd/312:05:503
49172510,1sleep10-21swapper/111:45:111
144199501,46cyclictest0-21swapper/210:10:232
144199482,3cyclictest17322-21kworker/2:209:00:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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