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2025-11-27 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Nov 26, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
163702206173,22sleep30-21swapper/307:07:303
162522203169,23sleep20-21swapper/207:05:562
163112202169,22sleep10-21swapper/107:06:441
163152201167,23sleep00-21swapper/007:06:470
53921510,7sleep01686999cyclictest08:50:170
1371918363,10phc2sys0-21swapper/307:10:003
136991720,1ptp4l401ktimersoftd/307:43:313
136991690,1ptp4l401ktimersoftd/309:00:173
136991650,1ptp4l401ktimersoftd/310:40:233
178922580,2sleep2311rcuc/210:35:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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