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2026-07-31 - 20:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 31, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2736223060,53sleep10-21swapper/107:05:211
286352205172,22sleep30-21swapper/307:09:503
283882204171,22sleep20-21swapper/207:06:452
265202202169,22sleep00-21swapper/007:05:100
286492162123,13sleep10-21swapper/107:10:011
286492162123,13sleep10-21swapper/107:10:011
1177721350,6sleep22894399cyclictest08:45:282
139391720,1ptp4l391rcuc/309:15:273
28944996123,4cyclictest41-21ksoftirqd/312:35:153
2894299618,11cyclictest16616-21/usr/sbin/munin12:20:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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