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2025-10-13 - 17:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Oct 13, 2025 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191206171,23phc2sys0-21swapper/307:07:153
52012205172,22sleep10-21swapper/107:06:491
52302204171,22sleep00-21swapper/007:07:110
51012204171,22sleep20-21swapper/207:05:332
621821730,5sleep0573899cyclictest11:40:160
1371918966,12phc2sys0-21swapper/307:10:013
1371918966,12phc2sys0-21swapper/307:10:003
5740996414,48cyclictest33-21ksoftirqd/208:20:282
136991640,0ptp4l401ktimersoftd/307:36:343
149182590,5sleep2574099cyclictest09:40:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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