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2026-01-18 - 15:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Sun Jan 18, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
619523390,9sleep341-21ksoftirqd/307:05:233
70042203170,22sleep00-21swapper/007:08:460
68482202169,22sleep10-21swapper/107:06:511
67662202169,22sleep20-21swapper/207:05:462
2175921600,4sleep2739499cyclictest10:05:152
197832610,2sleep10-21swapper/112:15:181
7393995825,7cyclictest25-21ksoftirqd/110:55:001
7393995216,4cyclictest25-21ksoftirqd/111:10:251
7393995215,5cyclictest25-21ksoftirqd/110:05:181
115222520,2sleep20-21swapper/208:30:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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