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2025-12-12 - 08:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Dec 12, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191207142,53phc2sys0-21swapper/319:07:523
203592203169,22sleep20-21swapper/219:07:152
184422202167,24sleep00-21swapper/019:05:080
202852199166,22sleep10-21swapper/119:06:211
680821150,2sleep00-21swapper/000:15:180
2087099731,70cyclictest13547-21kworker/2:100:30:272
20870996212,33cyclictest17297-21kworker/2:020:45:272
2087099613,56cyclictest17747-21kworker/2:122:35:472
281802520,2sleep00-21swapper/022:45:160
199542500,4sleep00-21swapper/020:15:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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