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2026-03-16 - 14:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 16, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491212169,22phc2sys0-21swapper/319:08:373
178132207174,22sleep10-21swapper/119:08:011
178142203169,22sleep20-21swapper/219:08:032
178122202168,23sleep00-21swapper/019:08:010
1796528263,10sleep30-21swapper/319:10:013
271772700,1sleep00-21swapper/020:35:140
18261996127,8cyclictest41-21ksoftirqd/323:11:273
18261995924,4cyclictest41-21ksoftirqd/320:20:213
1825999597,12cyclictest14586-21latency_hist20:10:011
1825999588,11cyclictest23276-21sed23:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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