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2025-11-28 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Nov 28, 2025 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
227512204170,23sleep20-21swapper/207:08:072
137191204171,22phc2sys0-21swapper/307:07:163
227202203170,22sleep10-21swapper/107:07:411
228912201168,22sleep00-21swapper/007:09:460
1371918964,16phc2sys0-21swapper/307:10:013
23205996029,8cyclictest25-21ksoftirqd/108:35:011
23205996027,7cyclictest25-21ksoftirqd/112:05:191
23205995925,4cyclictest25-21ksoftirqd/109:20:141
23205995924,8cyclictest25-21ksoftirqd/110:00:141
23205995923,9cyclictest25-21ksoftirqd/108:40:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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