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2026-10-10 - 01:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Oct 09, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307052205171,22sleep10-21swapper/107:05:371
308962204172,21sleep20-21swapper/207:08:082
139491204170,23phc2sys0-21swapper/307:09:013
307922200167,22sleep00-21swapper/007:06:450
31340997027,7cyclictest9-21ksoftirqd/011:10:240
31343996927,8cyclictest41-21ksoftirqd/308:25:263
31340996930,4cyclictest9-21ksoftirqd/007:20:020
31343996726,8cyclictest41-21ksoftirqd/310:45:253
31340996727,4cyclictest9-21ksoftirqd/009:45:180
31340996627,8cyclictest9-21ksoftirqd/012:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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