You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-09 - 05:43
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri May 09, 2025 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117822204172,22sleep10-21swapper/119:08:111
116972204169,23sleep30-21swapper/319:07:053
118552203170,22sleep20-21swapper/219:09:092
116112203169,23sleep00-21swapper/019:05:570
137191164126,13phc2sys0-21swapper/319:10:013
137191164126,13phc2sys0-21swapper/319:10:013
12215996325,5cyclictest33-21ksoftirqd/221:00:192
12215996221,8cyclictest33-21ksoftirqd/223:30:222
12215996221,8cyclictest33-21ksoftirqd/223:30:222
12215996030,4cyclictest33-21ksoftirqd/221:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional