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2026-01-20 - 05:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 20, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323002205171,23sleep10-21swapper/119:07:141
323002205171,23sleep10-21swapper/119:07:141
139491205170,23phc2sys0-21swapper/319:05:523
139491205170,23phc2sys0-21swapper/319:05:523
322712204172,21sleep20-21swapper/219:06:512
322712204172,21sleep20-21swapper/219:06:512
325152200170,20sleep00-21swapper/019:09:550
325152200170,20sleep00-21swapper/019:09:550
1362121570,4sleep20-21swapper/200:05:002
489997431,8cyclictest9-21ksoftirqd/023:05:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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