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2026-02-26 - 23:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 26, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
309852226164,51sleep00-21swapper/007:08:020
139491205171,23phc2sys0-21swapper/307:09:213
309912200168,21sleep10-21swapper/107:08:081
309102200168,21sleep20-21swapper/207:07:032
3114529470,13sleep20-21swapper/207:10:012
286692750,2sleep10-21swapper/110:25:151
139391730,1ptp4l12580-21awk12:05:213
206462700,3sleep220609-21cron10:10:002
3143899596,10cyclictest8773-21latency_hist12:00:012
3143899594,16cyclictest0-21swapper/210:35:172
3143899591,15cyclictest0-21swapper/209:50:262
3143899587,10cyclictest17380-21systemctl07:45:242
3143899584,17cyclictest0-21swapper/211:10:162
3143899572,15cyclictest0-21swapper/211:48:152
3143899566,10cyclictest17071-21cut12:15:192
3143899564,16cyclictest0-21swapper/212:10:232
3143899564,15cyclictest16505-21forks10:00:152
3143899562,16cyclictest0-21swapper/209:57:552
3143899556,10cyclictest22439-21cat12:25:252
3143899555,16cyclictest9915-21wc08:40:002
1394915536,12phc2sys0-21swapper/307:10:013
3143899546,15cyclictest13668-21latency_hist12:10:002
3143899543,17cyclictest0-21swapper/211:28:102
3143899536,16cyclictest13294-21cut11:00:192
3143899526,11cyclictest31673-21grep11:40:102
3143899526,11cyclictest31673-21grep11:40:102
3143899523,15cyclictest0-21swapper/208:45:152
3143899522,16cyclictest0-21swapper/211:05:262
180272510,3sleep30-21swapper/311:10:183
3143899506,14cyclictest1166-21cron07:15:012
3143899505,15cyclictest11213-21/usr/sbin/munin07:35:122
3143899501,16cyclictest0-21swapper/209:05:262
3143899497,16cyclictest20159-21sed12:20:252
3143899496,10cyclictest13966-21df_abs07:40:152
3143899486,14cyclictest15463-21chrt08:50:172
3143899485,8cyclictest27643-21ps09:15:172
3143899483,16cyclictest0-21swapper/209:40:232
31437994614,4cyclictest25-21ksoftirqd/107:20:001
3143899458,8cyclictest23398-21cat08:00:132
3143899456,7cyclictest26255-21awk10:20:162
3143899455,8cyclictest4309-21ps10:40:232
3143899451,16cyclictest0-21swapper/208:09:242
31437994515,4cyclictest25-21ksoftirqd/109:45:161
3143899446,8cyclictest21714-21irqstats07:55:192
3143799447,4cyclictest25-21ksoftirqd/112:10:011
31437994415,4cyclictest25-21ksoftirqd/110:35:271
139391440,0ptp4l401ktimersoftd/312:36:403
3143899435,7cyclictest5702-21ls09:35:242
3143899434,15cyclictest0-21swapper/210:50:272
31437994312,4cyclictest25-21ksoftirqd/111:30:261
139391430,0ptp4l401ktimersoftd/308:45:283
139391430,0ptp4l401ktimersoftd/307:35:013
139391430,0ptp4l401ktimersoftd/307:25:243
3143899423,16cyclictest0-21swapper/210:25:162
3143799427,5cyclictest25-21ksoftirqd/111:05:251
3143799427,3cyclictest25-21ksoftirqd/107:20:251
31437994222,3cyclictest25-21ksoftirqd/107:45:181
31437994213,4cyclictest25-21ksoftirqd/111:00:151
139391420,0ptp4l401ktimersoftd/309:24:573
3143899415,7cyclictest11737-21ls08:40:262
3143799419,4cyclictest25-21ksoftirqd/110:50:191
3143799419,3cyclictest25-21ksoftirqd/110:45:261
139391410,0ptp4l401ktimersoftd/309:49:523
3143899405,8cyclictest26264-21ls09:10:262
3143899404,8cyclictest19860-21ls07:50:282
3143899403,17cyclictest0-21swapper/211:35:012
3143799409,6cyclictest25-21ksoftirqd/107:35:161
3143799409,4cyclictest25-21ksoftirqd/109:30:201
3143799409,4cyclictest25-21ksoftirqd/108:10:271
3143799409,4cyclictest25-21ksoftirqd/108:10:271
3143799407,9cyclictest25-21ksoftirqd/111:54:591
3143799407,6cyclictest25-21ksoftirqd/108:35:141
3143799406,4cyclictest25-21ksoftirqd/108:45:141
3143799405,3cyclictest25-21ksoftirqd/107:25:181
3143799404,4cyclictest25-21ksoftirqd/110:20:161
31437994035,3cyclictest25-21ksoftirqd/108:25:011
31437994015,7cyclictest25-21ksoftirqd/111:45:281
31437994012,4cyclictest25-21ksoftirqd/110:34:251
31437994010,3cyclictest25-21ksoftirqd/107:40:251
139391400,1ptp4l391rcuc/307:44:133
3143899395,14cyclictest1300-21snmpd10:32:242
3143899393,11cyclictest0-21swapper/211:52:432
3143799399,4cyclictest25-21ksoftirqd/110:00:351
3143799396,4cyclictest25-21ksoftirqd/107:55:251
3143799395,8cyclictest25-21ksoftirqd/109:25:121
3143799395,6cyclictest25-21ksoftirqd/109:10:251
3143799395,4cyclictest25-21ksoftirqd/109:05:191
3143799395,3cyclictest25-21ksoftirqd/109:00:191
3143799394,4cyclictest25-21ksoftirqd/109:15:141
3143799394,3cyclictest121rcu_preempt11:15:171
3143799394,3cyclictest121rcu_preempt09:20:151
3143799394,2cyclictest121rcu_preempt07:50:271
139391390,0ptp4l401ktimersoftd/312:10:193
31438993810,26cyclictest20910-21kworker/2:212:35:222
3143799387,6cyclictest25-21ksoftirqd/111:35:221
3143799387,4cyclictest25-21ksoftirqd/108:17:371
3143799386,6cyclictest25-21ksoftirqd/111:55:231
3143799384,3cyclictest121rcu_preempt07:30:271
31437993833,3cyclictest25-21ksoftirqd/108:05:001
3143799382,4cyclictest25-21ksoftirqd/109:40:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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