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2026-02-05 - 21:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 05, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8482206173,22sleep20-21swapper/219:08:432
8482206173,22sleep20-21swapper/219:08:432
6802203170,22sleep30-21swapper/319:06:393
6802203170,22sleep30-21swapper/319:06:393
7802202168,22sleep10-21swapper/119:07:501
7802202168,22sleep10-21swapper/119:07:501
6822199165,23sleep00-21swapper/019:06:400
6822199165,23sleep00-21swapper/019:06:400
139391660,1ptp4l401ktimersoftd/323:55:113
124099620,22cyclictest17503-21expr21:55:280
124099610,20cyclictest17121-21irqstats00:10:180
124099600,20cyclictest13064-21irqrtprio22:55:180
104582570,2sleep10-21swapper/121:40:251
139391550,1ptp4l401ktimersoftd/319:10:153
208382540,2sleep30-21swapper/320:55:223
139391530,1ptp4l401ktimersoftd/321:55:023
124099520,18cyclictest3085-21mailstats21:25:240
65272510,2sleep00-21swapper/023:50:130
124099460,33cyclictest22671-21awk22:05:280
139391430,0ptp4l401ktimersoftd/323:05:403
139391430,0ptp4l401ktimersoftd/322:04:423
139391430,0ptp4l401ktimersoftd/320:45:243
1242994339,2cyclictest33-21ksoftirqd/223:40:002
1242994339,2cyclictest33-21ksoftirqd/221:39:592
1242994338,3cyclictest33-21ksoftirqd/200:20:002
1242994338,3cyclictest33-21ksoftirqd/200:20:002
139391420,0ptp4l401ktimersoftd/320:39:153
1242994211,4cyclictest33-21ksoftirqd/219:25:162
124099420,21cyclictest14650-21mailstats19:35:250
124099420,21cyclictest14650-21mailstats19:35:240
1242994136,2cyclictest33-21ksoftirqd/221:55:002
1242994118,3cyclictest33-21ksoftirqd/222:45:262
1242994035,3cyclictest33-21ksoftirqd/221:50:002
1242994010,4cyclictest33-21ksoftirqd/223:44:592
1242994010,3cyclictest33-21ksoftirqd/222:25:262
1242993934,3cyclictest33-21ksoftirqd/222:35:132
1242993934,3cyclictest33-21ksoftirqd/219:55:202
124299388,3cyclictest33-21ksoftirqd/223:50:212
124299387,7cyclictest33-21ksoftirqd/223:10:012
1242993833,3cyclictest33-21ksoftirqd/221:25:262
1242993828,8cyclictest33-21ksoftirqd/221:10:152
124299382,3cyclictest121rcu_preempt22:00:212
1241993834,2cyclictest25-21ksoftirqd/121:30:001
1241993833,3cyclictest25-21ksoftirqd/121:40:001
1241993833,3cyclictest25-21ksoftirqd/120:10:001
1243993731,4cyclictest41-21ksoftirqd/322:13:213
124299376,9cyclictest33-21ksoftirqd/220:10:292
124299376,5cyclictest121rcu_preempt22:55:232
1242993734,2cyclictest33-21ksoftirqd/220:25:012
1242993733,2cyclictest33-21ksoftirqd/220:55:182
1242993732,3cyclictest33-21ksoftirqd/219:45:252
1242993732,3cyclictest33-21ksoftirqd/219:20:012
1242993732,2cyclictest33-21ksoftirqd/219:54:592
124299371,4cyclictest33-21ksoftirqd/222:05:272
1241993732,3cyclictest25-21ksoftirqd/123:30:181
1241993732,3cyclictest25-21ksoftirqd/120:14:591
1241993731,3cyclictest25-21ksoftirqd/123:55:001
1241993731,3cyclictest25-21ksoftirqd/121:20:001
1240993732,3cyclictest1363-21sh21:25:010
124099370,22cyclictest8894-21awk19:25:160
139391360,0ptp4l401ktimersoftd/323:49:253
1243993631,3cyclictest41-21ksoftirqd/319:40:013
1243993631,3cyclictest41-21ksoftirqd/319:40:013
1243993631,3cyclictest41-21ksoftirqd/319:15:103
124299366,3cyclictest33-21ksoftirqd/200:25:242
1242993632,2cyclictest33-21ksoftirqd/222:20:172
1242993632,2cyclictest33-21ksoftirqd/219:40:242
1242993631,4cyclictest33-21ksoftirqd/219:40:002
1242993631,4cyclictest33-21ksoftirqd/219:40:002
1242993631,3cyclictest33-21ksoftirqd/223:05:012
1242993631,3cyclictest33-21ksoftirqd/220:55:002
1242993631,3cyclictest33-21ksoftirqd/220:15:312
1242993631,3cyclictest33-21ksoftirqd/220:10:012
1242993630,4cyclictest33-21ksoftirqd/219:35:012
1242993630,3cyclictest33-21ksoftirqd/220:30:152
1242993630,3cyclictest33-21ksoftirqd/200:05:132
1242993629,5cyclictest33-21ksoftirqd/221:42:062
124299361,2cyclictest121rcu_preempt00:00:192
1241993630,4cyclictest25-21ksoftirqd/123:11:061
1241993630,4cyclictest25-21ksoftirqd/122:17:041
1241993630,4cyclictest25-21ksoftirqd/100:15:011
1241993630,4cyclictest25-21ksoftirqd/100:02:171
1241993630,3cyclictest25-21ksoftirqd/121:09:591
1241993629,5cyclictest25-21ksoftirqd/122:38:341
1241993629,5cyclictest25-21ksoftirqd/119:43:151
124099360,20cyclictest0-21swapper/000:06:530
139391350,1ptp4l0-21swapper/323:54:333
1243993530,3cyclictest41-21ksoftirqd/321:44:003
1243993529,4cyclictest41-21ksoftirqd/323:01:013
1243993529,4cyclictest41-21ksoftirqd/321:20:363
1243993529,4cyclictest41-21ksoftirqd/319:51:323
1243993529,4cyclictest41-21ksoftirqd/300:07:163
1242993531,2cyclictest33-21ksoftirqd/221:20:182
1242993530,3cyclictest33-21ksoftirqd/223:55:132
1242993530,3cyclictest33-21ksoftirqd/223:45:412
1242993530,3cyclictest33-21ksoftirqd/222:50:162
1242993530,3cyclictest33-21ksoftirqd/220:35:162
1242993530,3cyclictest33-21ksoftirqd/219:10:142
1242993530,3cyclictest33-21ksoftirqd/200:38:342
1242993529,4cyclictest33-21ksoftirqd/220:27:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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