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2026-01-30 - 19:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot3.osadl.org (updated Fri Jan 30, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299342220154,22sleep00-21swapper/007:09:220
298412203168,23sleep30-21swapper/307:08:183
299482202169,22sleep20-21swapper/207:09:322
298392202169,22sleep10-21swapper/107:08:161
3129321820,6sleep03027699cyclictest07:10:220
1012821640,6sleep33027999cyclictest10:55:223
2998528763,16sleep20-21swapper/207:10:002
1394918463,11phc2sys0-21swapper/307:10:013
79422760,7sleep13027799cyclictest12:00:131
31112760,5sleep13117-21cpuspeed_turbos09:35:121
139391700,1ptp4l401ktimersoftd/307:28:293
7122610,7sleep1241ktimersoftd/108:20:231
6062570,2sleep00-21swapper/008:20:220
139391560,1ptp4l401ktimersoftd/312:04:383
138262540,3sleep20-21swapper/209:55:242
139391520,1ptp4l401ktimersoftd/309:01:123
30278995115,10cyclictest33-21ksoftirqd/210:15:152
30279994439,3cyclictest41-21ksoftirqd/307:40:003
3027999440,2cyclictest121rcu_preempt08:10:003
139391440,5ptp4l3027999cyclictest09:47:213
139391440,1ptp4l401ktimersoftd/307:20:133
139391440,0ptp4l401ktimersoftd/309:10:053
30279994339,2cyclictest1308-21sshd08:04:123
139391430,0ptp4l401ktimersoftd/310:02:403
3027999427,9cyclictest41-21ksoftirqd/312:40:003
30279994215,2cyclictest41-21ksoftirqd/311:45:013
30278994235,4cyclictest20560-21cron09:05:002
139391420,0ptp4l401ktimersoftd/311:15:143
3027999407,5cyclictest41-21ksoftirqd/311:35:223
3027999401,3cyclictest121rcu_preempt10:15:153
3027999400,3cyclictest121rcu_preempt10:35:193
30278994035,3cyclictest33-21ksoftirqd/212:20:012
30278994031,7cyclictest33-21ksoftirqd/207:44:052
30279993934,3cyclictest41-21ksoftirqd/311:25:003
30279993934,3cyclictest41-21ksoftirqd/309:10:003
30279993925,4cyclictest41-21ksoftirqd/307:45:153
139391390,1ptp4l401ktimersoftd/311:45:153
3027999388,8cyclictest41-21ksoftirqd/312:05:153
3027999388,8cyclictest41-21ksoftirqd/312:05:153
3027999387,4cyclictest41-21ksoftirqd/309:55:003
3027999384,3cyclictest121rcu_preempt08:13:183
30278993833,3cyclictest33-21ksoftirqd/209:25:182
3027999377,3cyclictest41-21ksoftirqd/311:25:193
30279993732,3cyclictest41-21ksoftirqd/310:10:013
30279993732,3cyclictest41-21ksoftirqd/309:39:593
30279993732,3cyclictest41-21ksoftirqd/309:20:123
30279993731,3cyclictest41-21ksoftirqd/308:40:003
3027999371,7cyclictest41-21ksoftirqd/309:30:233
30278993732,3cyclictest33-21ksoftirqd/208:10:002
30278993731,4cyclictest33-21ksoftirqd/209:21:212
30278993731,4cyclictest33-21ksoftirqd/208:32:192
30278993731,3cyclictest33-21ksoftirqd/208:20:122
30278993730,4cyclictest33-21ksoftirqd/207:45:592
30277993731,4cyclictest25-21ksoftirqd/111:14:251
30277993730,4cyclictest2506-21idleruntime-cro09:35:001
3027999365,4cyclictest41-21ksoftirqd/310:50:003
30279993633,2cyclictest41-21ksoftirqd/309:59:353
30279993631,3cyclictest41-21ksoftirqd/308:26:323
30279993630,4cyclictest41-21ksoftirqd/310:23:203
30279993630,4cyclictest41-21ksoftirqd/310:23:203
30278993631,3cyclictest33-21ksoftirqd/211:50:012
30278993631,3cyclictest33-21ksoftirqd/210:35:012
30278993630,4cyclictest33-21ksoftirqd/210:40:082
30278993630,4cyclictest33-21ksoftirqd/209:19:292
30278993630,4cyclictest33-21ksoftirqd/208:50:372
30278993629,4cyclictest33-21ksoftirqd/209:35:122
30278993627,7cyclictest33-21ksoftirqd/211:22:492
30277993630,4cyclictest25-21ksoftirqd/109:41:181
30277993630,4cyclictest25-21ksoftirqd/109:05:481
30277993629,5cyclictest25-21ksoftirqd/107:49:181
30277993629,4cyclictest25-21ksoftirqd/108:00:061
30276993627,6cyclictest21912-21cron08:00:010
139391360,0ptp4l401ktimersoftd/312:14:363
139391360,0ptp4l401ktimersoftd/309:40:013
3027999358,7cyclictest41-21ksoftirqd/308:55:003
3027999355,2cyclictest121rcu_preempt09:15:143
30279993532,2cyclictest41-21ksoftirqd/311:55:173
30279993530,2cyclictest41-21ksoftirqd/308:15:133
30278993530,3cyclictest33-21ksoftirqd/212:35:002
30278993530,3cyclictest33-21ksoftirqd/212:10:412
30278993530,3cyclictest33-21ksoftirqd/211:55:232
30278993530,3cyclictest33-21ksoftirqd/208:13:312
30278993530,3cyclictest33-21ksoftirqd/207:50:172
30278993529,3cyclictest33-21ksoftirqd/209:40:172
30277993529,4cyclictest25-21ksoftirqd/109:23:581
57898340,2rtkit-daemon0-21swapper/111:30:461
3027999348,5cyclictest41-21ksoftirqd/307:15:253
3027999347,6cyclictest41-21ksoftirqd/310:30:143
3027999345,3cyclictest41-21ksoftirqd/310:25:153
3027999345,3cyclictest121rcu_preempt07:50:213
30279993429,3cyclictest41-21ksoftirqd/311:00:193
30279993429,3cyclictest41-21ksoftirqd/310:10:203
30279993428,4cyclictest41-21ksoftirqd/312:15:053
30279993428,4cyclictest41-21ksoftirqd/311:51:343
30279993428,3cyclictest41-21ksoftirqd/311:10:123
30279993428,3cyclictest41-21ksoftirqd/311:10:003
30279993427,5cyclictest41-21ksoftirqd/307:57:103
3027999340,5cyclictest41-21ksoftirqd/308:45:163
30278993429,3cyclictest33-21ksoftirqd/211:50:182
30278993429,3cyclictest33-21ksoftirqd/210:47:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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