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2026-01-18 - 11:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot3.osadl.org (updated Sun Jan 18, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491204170,22phc2sys0-21swapper/319:06:043
186372202168,22sleep10-21swapper/119:06:551
185682202168,23sleep20-21swapper/219:06:002
186722201168,22sleep00-21swapper/019:07:150
1914921470,7sleep01917599cyclictest21:25:220
139391680,1ptp4l401ktimersoftd/323:33:533
19175996527,7cyclictest9-21ksoftirqd/020:50:000
19175996430,3cyclictest9-21ksoftirqd/023:29:590
177112640,6sleep01917599cyclictest22:30:170
1917699630,61cyclictest0-21swapper/122:13:331
19175996131,3cyclictest9-21ksoftirqd/019:15:010
19175996024,6cyclictest9-21ksoftirqd/021:55:270
19175995827,3cyclictest9-21ksoftirqd/022:40:010
19175995819,4cyclictest9-21ksoftirqd/019:20:260
19175995519,5cyclictest9-21ksoftirqd/023:45:260
19175995420,6cyclictest9-21ksoftirqd/000:05:290
19175995411,2cyclictest9-21ksoftirqd/020:55:180
19175995327,6cyclictest9-21ksoftirqd/022:55:160
19175995324,6cyclictest9-21ksoftirqd/019:40:190
19175995318,6cyclictest9-21ksoftirqd/000:28:010
139391530,1ptp4l401ktimersoftd/322:36:523
139391530,1ptp4l401ktimersoftd/321:47:293
1917599529,3cyclictest9-21ksoftirqd/019:55:260
19175995222,6cyclictest9-21ksoftirqd/019:50:000
19175995222,5cyclictest9-21ksoftirqd/000:20:140
19175995220,6cyclictest9-21ksoftirqd/019:15:190
19175995219,6cyclictest9-21ksoftirqd/020:10:130
19175995219,6cyclictest9-21ksoftirqd/020:10:130
297522510,2sleep10-21swapper/100:05:001
1917599516,2cyclictest9-21ksoftirqd/023:05:230
19175995145,3cyclictest15583-21sh20:09:590
19175995121,3cyclictest9-21ksoftirqd/020:01:530
19175995110,7cyclictest9-21ksoftirqd/022:50:130
278352500,2sleep20-21swapper/219:25:212
1917599508,3cyclictest9-21ksoftirqd/019:25:140
1917599507,7cyclictest9-21ksoftirqd/020:50:250
1917599505,2cyclictest9-21ksoftirqd/022:00:140
19175995022,6cyclictest9-21ksoftirqd/023:30:140
19175995018,4cyclictest9-21ksoftirqd/000:35:000
19175995015,5cyclictest9-21ksoftirqd/000:00:260
1917599500,7cyclictest9-21ksoftirqd/020:25:000
139391500,0ptp4l401ktimersoftd/320:06:353
21652490,1sleep22166-21/usr/sbin/munin19:40:182
1917599494,6cyclictest9-21ksoftirqd/023:10:220
1917599494,6cyclictest9-21ksoftirqd/023:10:210
19175994910,6cyclictest9-21ksoftirqd/023:15:140
19175994910,6cyclictest9-21ksoftirqd/020:35:180
1917599488,3cyclictest9-21ksoftirqd/020:40:220
1917599487,6cyclictest9-21ksoftirqd/021:05:320
1917599486,3cyclictest9-21ksoftirqd/022:15:010
1917599485,7cyclictest9-21ksoftirqd/020:25:180
1917599483,5cyclictest9-21ksoftirqd/021:45:230
1917599483,3cyclictest121rcu_preempt19:50:150
19175994814,5cyclictest9-21ksoftirqd/022:45:170
1917599481,10cyclictest9-21ksoftirqd/023:45:000
1917599476,3cyclictest9-21ksoftirqd/019:30:140
1917599475,9cyclictest9-21ksoftirqd/022:15:180
1917599471,6cyclictest9-21ksoftirqd/000:10:220
139391470,1ptp4l401ktimersoftd/300:22:033
1917599466,3cyclictest9-21ksoftirqd/021:35:190
1917599464,3cyclictest9-21ksoftirqd/023:35:250
19175994636,3cyclictest9-21ksoftirqd/023:55:190
1917599462,8cyclictest9-21ksoftirqd/023:50:230
1917599462,6cyclictest9-21ksoftirqd/021:15:240
1917599462,5cyclictest9-21ksoftirqd/022:05:230
1917599455,3cyclictest9-21ksoftirqd/023:25:000
1917599454,3cyclictest9-21ksoftirqd/022:20:250
19175994536,2cyclictest9-21ksoftirqd/023:00:130
1917599452,2cyclictest9-21ksoftirqd/021:40:190
1917699440,2cyclictest0-21swapper/121:41:231
1917699440,1cyclictest0-21swapper/122:01:421
1917599446,3cyclictest9-21ksoftirqd/021:05:010
1917599445,2cyclictest9-21ksoftirqd/020:30:190
1917599444,6cyclictest9-21ksoftirqd/019:35:270
1917599444,3cyclictest9-21ksoftirqd/021:20:170
1917599441,4cyclictest9-21ksoftirqd/020:15:140
1917699439,11cyclictest0-21swapper/121:05:041
1917599434,6cyclictest9-21ksoftirqd/021:50:140
19175994333,3cyclictest9-21ksoftirqd/000:15:230
141282430,1sleep10-21swapper/123:30:231
57898420,2rtkit-daemon0-21swapper/122:35:051
1917599424,6cyclictest9-21ksoftirqd/021:30:220
19175994234,2cyclictest9-21ksoftirqd/022:25:180
19175994228,6cyclictest9-21ksoftirqd/021:10:200
19175994219,3cyclictest9-21ksoftirqd/000:37:110
139391420,0ptp4l401ktimersoftd/323:46:313
19176994118,21cyclictest0-21swapper/121:00:041
1917599393,4cyclictest9-21ksoftirqd/022:40:400
1917599393,4cyclictest9-21ksoftirqd/022:40:400
19178993834,2cyclictest41-21ksoftirqd/323:40:003
19178993833,3cyclictest41-21ksoftirqd/323:45:013
19178993833,3cyclictest41-21ksoftirqd/320:40:013
139391380,1ptp4l401ktimersoftd/300:01:223
19177993731,4cyclictest33-21ksoftirqd/222:55:002
19177993731,4cyclictest33-21ksoftirqd/221:23:482
19177993710,26cyclictest0-21swapper/222:40:032
19177993710,26cyclictest0-21swapper/222:40:032
1917799368,26cyclictest0-21swapper/221:38:232
19177993630,4cyclictest33-21ksoftirqd/223:14:482
19177993630,4cyclictest33-21ksoftirqd/223:14:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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