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2026-02-17 - 04:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 17, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327092205176,19sleep30-21swapper/319:07:593
327082203170,22sleep20-21swapper/219:07:572
325602203170,22sleep00-21swapper/019:06:060
327392201168,22sleep10-21swapper/119:08:211
139391950,1ptp4l32148-21taskset22:28:343
54832600,4sleep30-21swapper/320:25:173
139391590,1ptp4l401ktimersoftd/323:20:143
139391560,1ptp4l401ktimersoftd/320:50:283
735995419,7cyclictest41-21ksoftirqd/320:34:593
49772540,2sleep20-21swapper/221:30:222
735995324,3cyclictest41-21ksoftirqd/323:00:263
66492530,6sleep36650-21/usr/sbin/munin19:20:223
735995217,7cyclictest41-21ksoftirqd/322:55:243
735995217,7cyclictest41-21ksoftirqd/320:15:243
735995120,8cyclictest41-21ksoftirqd/320:05:273
735995118,6cyclictest41-21ksoftirqd/323:25:273
735995022,7cyclictest41-21ksoftirqd/322:50:013
735995021,4cyclictest41-21ksoftirqd/300:25:013
735995019,8cyclictest41-21ksoftirqd/322:40:013
735995017,8cyclictest41-21ksoftirqd/322:20:003
735995017,7cyclictest41-21ksoftirqd/323:50:183
735994917,7cyclictest41-21ksoftirqd/321:00:263
735994913,5cyclictest41-21ksoftirqd/321:40:003
735994817,4cyclictest41-21ksoftirqd/321:45:163
735994817,4cyclictest41-21ksoftirqd/320:00:183
735994811,4cyclictest41-21ksoftirqd/319:29:593
203752480,2sleep20-21swapper/222:05:002
735994719,7cyclictest41-21ksoftirqd/319:55:013
735994719,3cyclictest41-21ksoftirqd/300:10:233
735994718,4cyclictest41-21ksoftirqd/321:15:223
735994716,8cyclictest41-21ksoftirqd/300:30:003
735994716,7cyclictest41-21ksoftirqd/321:30:223
735994715,7cyclictest41-21ksoftirqd/320:55:203
735994620,7cyclictest41-21ksoftirqd/321:10:013
735994616,3cyclictest41-21ksoftirqd/300:15:143
735994614,8cyclictest41-21ksoftirqd/300:35:263
735994612,7cyclictest41-21ksoftirqd/319:15:263
735994612,4cyclictest41-21ksoftirqd/322:05:183
735994611,8cyclictest41-21ksoftirqd/300:00:193
735994518,7cyclictest41-21ksoftirqd/323:10:003
735994514,3cyclictest41-21ksoftirqd/320:40:153
735994512,4cyclictest41-21ksoftirqd/300:10:003
735994413,8cyclictest41-21ksoftirqd/320:45:213
735994413,3cyclictest41-21ksoftirqd/322:50:153
735994412,7cyclictest41-21ksoftirqd/323:10:143
735994412,7cyclictest41-21ksoftirqd/323:10:143
735994410,5cyclictest41-21ksoftirqd/319:40:003
735994316,6cyclictest41-21ksoftirqd/322:10:143
735994316,6cyclictest41-21ksoftirqd/322:10:143
735994315,3cyclictest41-21ksoftirqd/321:40:203
735994315,3cyclictest41-21ksoftirqd/321:40:203
735994314,6cyclictest41-21ksoftirqd/321:20:133
735994314,3cyclictest41-21ksoftirqd/321:50:183
735994312,4cyclictest41-21ksoftirqd/323:35:263
735994312,3cyclictest41-21ksoftirqd/323:35:003
139391430,0ptp4l401ktimersoftd/323:46:073
73599429,4cyclictest41-21ksoftirqd/319:10:133
73599427,4cyclictest41-21ksoftirqd/322:20:213
73599424,3cyclictest121rcu_preempt20:39:593
735994214,7cyclictest41-21ksoftirqd/320:20:163
57898420,2rtkit-daemon577-21rtkit-daemon19:55:221
735994136,3cyclictest41-21ksoftirqd/319:45:013
73599413,4cyclictest41-21ksoftirqd/322:04:073
735994115,6cyclictest41-21ksoftirqd/300:30:213
735994113,7cyclictest41-21ksoftirqd/322:30:123
735994110,4cyclictest41-21ksoftirqd/322:40:153
732994136,3cyclictest9-21ksoftirqd/022:50:000
732994134,4cyclictest27923-21cron00:35:000
73599409,5cyclictest41-21ksoftirqd/321:10:163
73599407,4cyclictest41-21ksoftirqd/323:55:253
732994034,3cyclictest9-21ksoftirqd/000:00:000
73599399,4cyclictest41-21ksoftirqd/323:15:243
73599395,4cyclictest41-21ksoftirqd/319:55:273
73599394,6cyclictest41-21ksoftirqd/319:50:013
73599394,3cyclictest41-21ksoftirqd/319:30:153
73599391,5cyclictest41-21ksoftirqd/323:42:443
735993833,3cyclictest41-21ksoftirqd/320:15:013
735993710,7cyclictest41-21ksoftirqd/321:25:143
734993730,4cyclictest33-21ksoftirqd/223:07:022
732993732,3cyclictest9-21ksoftirqd/021:40:000
732993731,3cyclictest520-21cron19:19:590
73599361,2cyclictest121rcu_preempt21:55:193
733993630,4cyclictest25-21ksoftirqd/100:05:111
732993629,4cyclictest10329-21turbostat.cron19:30:000
57898360,5rtkit-daemon590-21gmain23:48:060
734993530,3cyclictest33-21ksoftirqd/223:50:002
734993530,3cyclictest33-21ksoftirqd/219:53:582
734993529,4cyclictest33-21ksoftirqd/223:13:282
734993529,4cyclictest33-21ksoftirqd/223:13:272
734993529,4cyclictest33-21ksoftirqd/222:24:542
734993529,4cyclictest33-21ksoftirqd/221:02:342
734993529,4cyclictest33-21ksoftirqd/200:21:232
733993530,3cyclictest25-21ksoftirqd/121:02:071
733993529,4cyclictest25-21ksoftirqd/123:31:031
733993529,4cyclictest25-21ksoftirqd/122:21:511
733993529,4cyclictest25-21ksoftirqd/121:35:421
733993529,4cyclictest25-21ksoftirqd/120:26:511
733993529,4cyclictest25-21ksoftirqd/120:16:401
732993531,3cyclictest9-21ksoftirqd/022:00:000
732993530,3cyclictest9-21ksoftirqd/022:25:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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