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2026-03-02 - 05:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 02, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,22phc2sys0-21swapper/319:06:513
79072204170,23sleep20-21swapper/219:09:192
77222203169,22sleep10-21swapper/119:06:531
77562201168,22sleep00-21swapper/019:07:200
1394919368,13phc2sys0-21swapper/319:10:013
8254998334,3cyclictest25-21ksoftirqd/123:19:591
153802730,1sleep00-21swapper/019:25:010
8256995928,7cyclictest41-21ksoftirqd/322:32:093
8256995828,9cyclictest41-21ksoftirqd/320:40:003
8256995827,10cyclictest41-21ksoftirqd/300:30:213
253702580,6sleep1825499cyclictest20:50:271
95752570,1sleep10-21swapper/122:35:011
825499569,7cyclictest25-21ksoftirqd/122:55:201
281342560,1sleep20-21swapper/223:10:282
825699554,6cyclictest29955-21cat00:24:593
825699544,7cyclictest5310-21tune2fs22:25:173
8254995413,9cyclictest121rcu_preempt22:45:121
825699530,7cyclictest401ktimersoftd/322:40:013
825699524,7cyclictest1985-21cut23:25:173
825699523,7cyclictest401ktimersoftd/322:45:013
825699523,7cyclictest14706-21hwlatdetect20:30:163
825699523,6cyclictest401ktimersoftd/321:30:243
825699522,7cyclictest8021-21vmstat21:20:263
8256995227,8cyclictest41-21ksoftirqd/320:25:253
8255995229,5cyclictest33-21ksoftirqd/220:11:442
8255995221,7cyclictest33-21ksoftirqd/200:10:232
8254995234,4cyclictest25-21ksoftirqd/100:00:011
160842520,2sleep10-21swapper/121:40:121
825699514,5cyclictest0-21swapper/319:30:203
8254995112,8cyclictest25-21ksoftirqd/122:00:251
163012510,1sleep20-21swapper/219:25:192
8256995022,9cyclictest41-21ksoftirqd/320:00:253
825699501,7cyclictest9006-21cat20:20:003
8255995023,17cyclictest33-21ksoftirqd/222:10:252
825499508,9cyclictest25-21ksoftirqd/123:10:281
825499508,8cyclictest25-21ksoftirqd/122:50:131
8254995031,3cyclictest25-21ksoftirqd/100:10:261
825699493,6cyclictest401ktimersoftd/319:20:143
8256994919,9cyclictest41-21ksoftirqd/320:25:013
825699491,6cyclictest401ktimersoftd/321:05:143
825699490,6cyclictest401ktimersoftd/300:10:143
8255994923,19cyclictest33-21ksoftirqd/223:05:272
8254994911,2cyclictest121rcu_preempt19:55:191
8253994918,7cyclictest9-21ksoftirqd/023:40:130
8253994915,4cyclictest9-21ksoftirqd/021:30:230
825699483,7cyclictest401ktimersoftd/321:25:133
825699483,6cyclictest401ktimersoftd/322:20:123
825699482,6cyclictest27564-21cat22:05:013
825699481,6cyclictest401ktimersoftd/323:30:213
8254994812,4cyclictest25-21ksoftirqd/122:15:251
8254994811,3cyclictest121rcu_preempt19:10:181
8254994810,9cyclictest25-21ksoftirqd/120:20:111
825399486,3cyclictest9-21ksoftirqd/022:30:260
825699474,5cyclictest401ktimersoftd/319:35:123
825699473,6cyclictest401ktimersoftd/300:00:153
8256994723,8cyclictest41-21ksoftirqd/321:00:133
8256994717,3cyclictest41-21ksoftirqd/323:05:383
825699470,7cyclictest401ktimersoftd/320:10:263
8255994721,18cyclictest33-21ksoftirqd/222:35:242
8254994736,3cyclictest25-21ksoftirqd/121:15:191
8254994724,11cyclictest25-21ksoftirqd/100:15:251
8254994722,4cyclictest25-21ksoftirqd/123:54:591
8253994726,3cyclictest9-21ksoftirqd/019:15:140
8253994717,6cyclictest9-21ksoftirqd/023:02:160
8253994714,8cyclictest9-21ksoftirqd/023:25:260
8256994617,3cyclictest41-21ksoftirqd/300:28:293
825699461,6cyclictest3948-21cat21:15:113
825699460,6cyclictest21829-21gzip21:50:213
8255994630,8cyclictest33-21ksoftirqd/220:50:282
8255994627,16cyclictest33-21ksoftirqd/221:05:112
8254994640,3cyclictest449-21dbus-daemon20:20:001
825499463,7cyclictest25-21ksoftirqd/119:15:141
8254994613,2cyclictest121rcu_preempt20:15:001
8253994614,4cyclictest9-21ksoftirqd/020:55:170
825699453,6cyclictest401ktimersoftd/323:35:273
825699452,6cyclictest41-21ksoftirqd/300:39:563
825699451,7cyclictest27932-21df_abs22:05:143
825699450,7cyclictest401ktimersoftd/322:10:233
825699450,6cyclictest401ktimersoftd/319:40:173
825699450,42cyclictest401ktimersoftd/321:40:243
825599456,3cyclictest33-21ksoftirqd/223:20:002
8255994529,9cyclictest33-21ksoftirqd/200:30:182
825599450,42cyclictest24992-21sh22:00:002
8254994525,3cyclictest25-21ksoftirqd/121:25:001
825499452,2cyclictest121rcu_preempt19:40:121
825399452,3cyclictest121rcu_preempt22:40:000
8253994515,3cyclictest9-21ksoftirqd/000:05:150
825699440,7cyclictest21946-21grep23:00:143
825699440,6cyclictest401ktimersoftd/321:35:263
8255994425,10cyclictest33-21ksoftirqd/220:05:152
8255994424,9cyclictest33-21ksoftirqd/222:55:262
8255994424,10cyclictest33-21ksoftirqd/222:25:142
825499449,7cyclictest25-21ksoftirqd/100:20:191
825499445,7cyclictest25-21ksoftirqd/120:40:151
825499444,10cyclictest25-21ksoftirqd/122:20:181
8254994438,3cyclictest25-21ksoftirqd/121:40:011
825499442,2cyclictest25-21ksoftirqd/121:10:251
8254994412,7cyclictest25-21ksoftirqd/120:05:231
8254994410,7cyclictest25-21ksoftirqd/123:35:181
8253994416,4cyclictest9-21ksoftirqd/021:04:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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