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2026-09-20 - 22:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Sep 20, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30862209175,23sleep20-21swapper/207:09:152
139491206163,32phc2sys0-21swapper/307:09:293
31172204170,22sleep10-21swapper/107:09:381
27882197164,22sleep00-21swapper/007:06:110
1394918562,15phc2sys0-21swapper/307:10:013
169622680,7sleep0343899cyclictest08:45:150
3438996615,4cyclictest9-21ksoftirqd/008:40:010
344199621,18cyclictest449-21dbus-daemon11:30:243
344199610,19cyclictest16932-21unixbench_multi09:50:273
3439996131,4cyclictest25-21ksoftirqd/108:00:231
344199580,20cyclictest6064-21awk10:35:293
3439995826,4cyclictest25-21ksoftirqd/111:30:161
3439995825,3cyclictest25-21ksoftirqd/108:10:011
3438995822,8cyclictest9-21ksoftirqd/010:10:260
262412580,1sleep00-21swapper/012:25:270
3439995729,3cyclictest25-21ksoftirqd/110:25:261
136972560,5sleep313698-21irqrtprio09:45:213
3439995523,8cyclictest25-21ksoftirqd/108:20:131
3439995420,4cyclictest25-21ksoftirqd/110:45:011
3438995422,4cyclictest9-21ksoftirqd/010:50:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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