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2026-06-25 - 23:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jun 25, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491237193,34phc2sys0-21swapper/307:06:583
53932236170,22sleep20-21swapper/207:07:072
53092213150,51sleep00-21swapper/007:05:590
53722202169,22sleep10-21swapper/107:06:491
3162921480,6sleep3591699cyclictest11:25:133
551521470,3sleep0591399cyclictest10:30:180
19222770,6sleep10-21swapper/109:15:181
134491640,7getstats591699cyclictest08:25:213
134491630,5getstats41-21ksoftirqd/309:15:213
139391570,1ptp4l401ktimersoftd/307:39:513
139391550,1ptp4l401ktimersoftd/311:47:203
292872530,2sleep10-21swapper/107:55:261
163092520,2sleep116311-21awk10:50:251
147122510,1sleep10-21swapper/107:25:271
139391500,1ptp4l401ktimersoftd/308:18:113
88802490,2sleep00-21swapper/011:45:120
5916994716,3cyclictest41-21ksoftirqd/307:45:273
139391470,1ptp4l401ktimersoftd/312:28:203
139391470,1ptp4l401ktimersoftd/312:28:203
5916994625,2cyclictest41-21ksoftirqd/310:25:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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