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2026-03-17 - 08:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Mar 17, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4272204171,22sleep00-21swapper/019:06:010
7432203170,22sleep30-21swapper/319:09:333
4292201169,21sleep20-21swapper/219:06:032
6762200168,21sleep10-21swapper/119:08:471
1521921710,4sleep2107399cyclictest23:00:142
2317121490,2sleep30-21swapper/322:10:013
1120921320,4sleep3107499cyclictest23:55:343
1393911230,1ptp4l26327-21interrupts22:15:183
1072997116,53cyclictest0-21swapper/122:25:331
139391640,1ptp4l401ktimersoftd/322:32:043
280872610,4sleep3107499cyclictest22:20:123
1073996127,4cyclictest33-21ksoftirqd/219:25:012
1073996029,6cyclictest33-21ksoftirqd/223:55:012
107299600,58cyclictest0-21swapper/122:36:531
1073995826,4cyclictest33-21ksoftirqd/222:50:192
139391570,1ptp4l401ktimersoftd/320:57:443
8532560,5sleep233-21ksoftirqd/221:20:252
58892560,2sleep20-21swapper/220:25:172
1073995626,7cyclictest33-21ksoftirqd/219:45:002
1073995625,4cyclictest33-21ksoftirqd/221:25:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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