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2026-09-05 - 16:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Sep 05, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190782228161,22sleep00-21swapper/007:05:060
210932208172,25sleep20-21swapper/207:08:372
139491208175,22phc2sys0-21swapper/307:09:583
211542200168,21sleep10-21swapper/107:09:261
302942670,5sleep230298-21switchtime09:40:242
21499996332,6cyclictest9-21ksoftirqd/012:30:180
21499996332,6cyclictest9-21ksoftirqd/012:30:180
21499996331,4cyclictest9-21ksoftirqd/009:35:010
21499996128,6cyclictest9-21ksoftirqd/012:15:240
21499996128,3cyclictest9-21ksoftirqd/007:35:240
181202610,6sleep32150299cyclictest08:10:083
21499996027,4cyclictest9-21ksoftirqd/009:15:010
21499996027,10cyclictest9-21ksoftirqd/008:55:000
116722600,4sleep011669-21cat11:20:000
21499995928,4cyclictest9-21ksoftirqd/010:35:140
21499995927,4cyclictest9-21ksoftirqd/007:20:250
21499995927,4cyclictest9-21ksoftirqd/007:20:250
21499995830,3cyclictest9-21ksoftirqd/009:00:200
21499995829,5cyclictest9-21ksoftirqd/011:45:220
21499995829,4cyclictest9-21ksoftirqd/011:54:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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