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2026-07-27 - 16:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 27, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491209176,22phc2sys0-21swapper/307:09:523
86952207174,22sleep20-21swapper/207:08:022
87292203171,21sleep10-21swapper/107:08:291
86112202169,22sleep00-21swapper/007:06:560
2174221670,5sleep0914799cyclictest09:50:150
276042560,3sleep027607-21ptp4l-jitter07:45:260
139391560,1ptp4l401ktimersoftd/311:20:223
139391470,1ptp4l401ktimersoftd/312:12:473
139391450,1ptp4l401ktimersoftd/310:06:403
139391440,35ptp4l0-21swapper/307:10:013
9150994338,3cyclictest9082-21sh09:25:003
9147994336,4cyclictest3028-21cron12:35:000
139391430,0ptp4l401ktimersoftd/307:31:223
914899422,37cyclictest7363-21fschecks_count09:20:161
57898420,9rtkit-daemon0-21swapper/309:06:123
9150994035,3cyclictest41-21ksoftirqd/309:20:013
9147994035,3cyclictest9-21ksoftirqd/012:09:590
9147994034,3cyclictest9-21ksoftirqd/008:00:010
915099396,6cyclictest121rcu_preempt12:39:593
9150993935,2cyclictest16359-21turbostat11:55:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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