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2026-07-16 - 10:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 16, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491233168,22phc2sys0-21swapper/319:06:223
294392230163,22sleep10-21swapper/119:09:271
292482210162,37sleep20-21swapper/219:06:592
292782205172,22sleep00-21swapper/019:07:200
1394918362,11phc2sys0-21swapper/319:10:013
29776996729,4cyclictest33-21ksoftirqd/200:30:002
29776996631,6cyclictest33-21ksoftirqd/200:20:002
139391660,1ptp4l401ktimersoftd/300:20:213
255682610,3sleep20-21swapper/221:15:122
2977699574,6cyclictest321ktimersoftd/200:00:002
139391570,1ptp4l401ktimersoftd/323:39:463
29776995626,4cyclictest33-21ksoftirqd/223:30:142
29776995623,4cyclictest33-21ksoftirqd/220:05:152
139391560,1ptp4l401ktimersoftd/323:25:113
139391560,1ptp4l401ktimersoftd/320:30:253
2977699555,8cyclictest33-21ksoftirqd/221:50:182
139391550,0ptp4l401ktimersoftd/300:00:203
139391540,1ptp4l401ktimersoftd/319:29:203
2977699534,8cyclictest33-21ksoftirqd/221:40:162
2977699533,6cyclictest33-21ksoftirqd/223:20:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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