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2026-07-13 - 05:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 13, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491239170,23phc2sys0-21swapper/319:09:493
51962206171,24sleep00-21swapper/019:09:240
51932206173,22sleep20-21swapper/219:09:222
31182203170,22sleep10-21swapper/119:05:101
1394918969,10phc2sys0-21swapper/319:10:003
553699577,7cyclictest4444-21tr22:30:141
5535995727,8cyclictest9-21ksoftirqd/023:25:320
82202560,1sleep20-21swapper/219:15:142
553699567,6cyclictest13132-21cpuspeed_turbos23:55:131
553699551,15cyclictest20156-21cat00:10:001
553699550,11cyclictest534-21sed00:35:181
139391550,1ptp4l401ktimersoftd/300:05:593
553699544,10cyclictest5844-21apt-key23:40:011
553699544,10cyclictest5844-21apt-key23:40:011
553699540,11cyclictest25493-21sed23:10:291
553699535,7cyclictest25216-21cpuspeed_turbos00:20:141
553699533,6cyclictest0-21swapper/120:30:191
553699530,10cyclictest17568-21phc2sys22:55:231
139391530,1ptp4l401ktimersoftd/322:05:503
553699525,9cyclictest28427-21cat00:25:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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