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2026-06-16 - 09:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 16, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
55502234167,22sleep30-21swapper/319:05:453
56712204171,21sleep10-21swapper/119:07:111
58762202169,22sleep00-21swapper/019:09:520
58842200170,20sleep20-21swapper/219:09:582
312062730,1sleep00-21swapper/020:00:200
139391720,1ptp4l401ktimersoftd/319:45:093
6181996622,4cyclictest25-21ksoftirqd/100:40:001
6181995917,4cyclictest25-21ksoftirqd/122:20:181
6181995613,7cyclictest25-21ksoftirqd/119:40:111
618199538,7cyclictest25-21ksoftirqd/119:30:161
6181995314,7cyclictest25-21ksoftirqd/123:05:171
139391520,1ptp4l401ktimersoftd/300:16:163
6181995119,5cyclictest25-21ksoftirqd/120:45:151
280082500,2sleep20-21swapper/223:15:272
6181994910,7cyclictest25-21ksoftirqd/123:40:251
618199487,5cyclictest25-21ksoftirqd/119:35:221
6180994828,8cyclictest9-21ksoftirqd/021:40:190
6183994740,4cyclictest16627-21turbostat.cron20:40:013
6181994710,7cyclictest25-21ksoftirqd/120:55:151
618199469,9cyclictest25-21ksoftirqd/120:00:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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