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2026-06-17 - 10:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jun 17, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491235168,22phc2sys0-21swapper/319:08:113
282052204171,22sleep00-21swapper/019:08:340
280112204170,23sleep20-21swapper/219:06:032
282612202169,22sleep10-21swapper/119:09:191
28610995120,6cyclictest41-21ksoftirqd/321:26:313
134342510,2sleep20-21swapper/223:05:282
2861099465,6cyclictest41-21ksoftirqd/320:05:003
2861099462,5cyclictest41-21ksoftirqd/322:55:263
2861099461,5cyclictest41-21ksoftirqd/321:10:243
2861099456,6cyclictest41-21ksoftirqd/300:20:253
2861099454,6cyclictest0-21swapper/320:25:143
28610994516,8cyclictest41-21ksoftirqd/322:36:313
2861099444,7cyclictest41-21ksoftirqd/322:45:173
28610994415,8cyclictest41-21ksoftirqd/322:21:273
2861099440,7cyclictest401ktimersoftd/300:00:263
139391440,0ptp4l401ktimersoftd/322:30:163
2861099433,5cyclictest0-21swapper/323:00:163
2861099432,5cyclictest41-21ksoftirqd/323:11:463
2861099432,5cyclictest41-21ksoftirqd/321:37:043
28610994316,8cyclictest41-21ksoftirqd/323:21:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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