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2025-12-06 - 12:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Dec 06, 2025 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191205171,22phc2sys0-21swapper/319:07:073
124672204170,22sleep10-21swapper/119:06:121
126182202169,22sleep20-21swapper/219:08:102
124612201168,22sleep00-21swapper/019:06:070
1096821770,7sleep01305399cyclictest21:20:000
13055996730,4cyclictest33-21ksoftirqd/220:05:002
136991660,1ptp4l401ktimersoftd/300:21:513
136991630,1ptp4l401ktimersoftd/321:48:453
13055996326,7cyclictest33-21ksoftirqd/222:30:262
13055996324,6cyclictest33-21ksoftirqd/221:45:002
134562610,2sleep10-21swapper/122:30:221
315732600,3sleep20-21swapper/200:15:212
13055995926,7cyclictest33-21ksoftirqd/200:05:242
13055995925,6cyclictest33-21ksoftirqd/219:20:002
13055995924,6cyclictest33-21ksoftirqd/200:05:002
13055995924,6cyclictest33-21ksoftirqd/200:05:002
13055995923,6cyclictest33-21ksoftirqd/222:20:182
13055995922,6cyclictest33-21ksoftirqd/222:25:172
136991580,1ptp4l401ktimersoftd/323:35:253
136991580,0ptp4l401ktimersoftd/320:42:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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