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2026-04-07 - 03:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Apr 07, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36662235169,21sleep10-21swapper/119:07:361
139491204171,22phc2sys0-21swapper/319:05:583
36872203169,23sleep20-21swapper/219:07:542
35282203171,22sleep00-21swapper/019:05:550
748021410,5sleep1414499cyclictest21:30:001
4146996028,8cyclictest41-21ksoftirqd/322:10:003
4146995827,6cyclictest41-21ksoftirqd/323:25:003
4146995826,4cyclictest41-21ksoftirqd/322:05:003
4146995626,6cyclictest41-21ksoftirqd/320:00:003
4146995527,3cyclictest41-21ksoftirqd/321:05:163
219672550,4sleep121965-21turbostat.cron00:15:001
219672550,4sleep121965-21turbostat.cron00:15:001
4146995424,7cyclictest41-21ksoftirqd/320:35:183
4146995424,3cyclictest41-21ksoftirqd/321:00:243
4146995423,3cyclictest41-21ksoftirqd/320:10:003
4146995422,4cyclictest41-21ksoftirqd/319:10:173
4146995422,3cyclictest41-21ksoftirqd/320:45:013
4146995328,6cyclictest41-21ksoftirqd/321:50:223
4146995325,3cyclictest41-21ksoftirqd/321:15:233
4146995321,4cyclictest41-21ksoftirqd/323:15:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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