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2026-04-21 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Apr 20, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205172,22phc2sys0-21swapper/307:06:593
204632200168,21sleep20-21swapper/207:07:572
204372200168,22sleep10-21swapper/107:07:351
203162197164,22sleep00-21swapper/007:06:020
3103621440,5sleep02092299cyclictest12:00:140
139491137111,14phc2sys0-21swapper/307:10:013
139391820,1ptp4l20781-21latency_hist11:40:013
2092499649,12cyclictest16718-21grep12:35:292
20924996412,9cyclictest18545-21latency_hist11:35:002
260732630,2sleep20-21swapper/209:35:152
2092499638,18cyclictest0-21swapper/209:40:262
20924996314,9cyclictest4348-21date11:05:002
20924996313,9cyclictest31993-21latency_hist08:40:012
20924996313,9cyclictest18313-21sed08:10:182
20924996313,9cyclictest13033-21sed09:05:262
20924996310,17cyclictest17263-21cat10:24:592
2092499629,10cyclictest11288-21sed07:55:192
2092499628,10cyclictest23176-21latency_hist11:45:002
20924996213,9cyclictest11795-21unixbench_multi10:10:272
20924996212,9cyclictest1230-21timerwakeupswit08:40:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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