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2026-07-23 - 21:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 23, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
213182227163,20sleep00-21swapper/007:06:470
213062226163,51sleep30-21swapper/307:06:383
213402200166,23sleep20-21swapper/207:07:052
212772200167,22sleep10-21swapper/107:06:161
2186799700,30cyclictest15257-21df_abs09:10:140
2186899620,3cyclictest6191-21seq09:58:211
21869996031,7cyclictest33-21ksoftirqd/210:40:002
21869995931,4cyclictest33-21ksoftirqd/212:00:142
21869995625,7cyclictest33-21ksoftirqd/207:20:002
2186799561,24cyclictest4657-21fschecks_time09:55:140
21869995527,6cyclictest33-21ksoftirqd/212:10:012
21869995526,7cyclictest33-21ksoftirqd/208:10:002
21869995517,10cyclictest33-21ksoftirqd/211:35:252
21869995417,6cyclictest33-21ksoftirqd/208:55:262
21869995323,3cyclictest33-21ksoftirqd/211:00:132
21869995322,4cyclictest33-21ksoftirqd/209:25:152
21869995318,7cyclictest33-21ksoftirqd/210:10:132
21869995316,8cyclictest33-21ksoftirqd/211:10:142
151462530,2sleep30-21swapper/309:10:143
21869995221,4cyclictest33-21ksoftirqd/209:05:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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