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2026-03-26 - 22:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 26, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205171,23phc2sys0-21swapper/307:07:333
114452203170,22sleep00-21swapper/007:07:390
114412202169,22sleep10-21swapper/107:07:361
114172201168,22sleep20-21swapper/207:07:172
388221610,7sleep21192999cyclictest09:05:252
1986421370,7sleep21192999cyclictest10:50:012
10272950,3sleep30-21swapper/312:25:123
1163628561,16sleep10-21swapper/107:10:011
221222720,3sleep122126-21latency09:45:211
1192999600,2cyclictest77982sleep208:08:582
275632580,2sleep10-21swapper/111:05:121
139391550,0ptp4l401ktimersoftd/311:50:173
1192799540,3cyclictest8770-21seq09:16:520
139391470,1ptp4l401ktimersoftd/310:19:493
139391440,1ptp4l401ktimersoftd/311:55:373
11930994440,2cyclictest41-21ksoftirqd/307:59:593
139391430,0ptp4l401ktimersoftd/312:24:423
139391420,0ptp4l401ktimersoftd/309:58:523
1192799417,21cyclictest25867-21seq07:39:190
139391400,32ptp4l0-21swapper/307:10:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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