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2026-09-23 - 21:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Sep 23, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
294032206173,22sleep10-21swapper/107:06:271
294272204170,22sleep30-21swapper/307:06:443
294662203169,22sleep20-21swapper/207:07:162
296422202169,22sleep00-21swapper/007:09:270
2436821310,3sleep32998299cyclictest11:25:203
45572740,4sleep34562-21latency08:30:203
75092600,4sleep3401ktimersoftd/307:30:153
75832530,3sleep12998099cyclictest09:45:131
32412530,1sleep00-21swapper/010:40:230
149532510,1sleep00-21swapper/011:05:230
2998199491,46cyclictest4170-21kworker/2:108:50:232
283902490,2sleep30-21swapper/311:35:153
29980994842,3cyclictest19172-21sh10:10:001
29980994740,4cyclictest2113-21awk07:20:011
29982994539,4cyclictest26607-21fschecks_count08:10:163
2997999431,39cyclictest12452-21fschecks_count09:55:160
139391420,1ptp4l401ktimersoftd/310:39:473
139391420,0ptp4l401ktimersoftd/309:07:163
139391410,1ptp4l401ktimersoftd/308:18:283
139391410,0ptp4l401ktimersoftd/311:17:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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