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2026-03-22 - 11:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 22, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2759223270,8sleep341-21ksoftirqd/319:05:263
282322203170,22sleep00-21swapper/019:09:250
281472203169,23sleep20-21swapper/219:08:192
279632202169,22sleep10-21swapper/119:06:011
83852740,3sleep0111rcuc/019:35:000
179762600,2sleep30-21swapper/319:55:003
28568995622,4cyclictest9-21ksoftirqd/023:35:190
28571995420,4cyclictest41-21ksoftirqd/300:30:013
28571994919,3cyclictest41-21ksoftirqd/323:10:223
28571994916,8cyclictest41-21ksoftirqd/319:45:003
28571994819,4cyclictest41-21ksoftirqd/323:40:163
28571994819,4cyclictest41-21ksoftirqd/322:05:183
28571994816,7cyclictest41-21ksoftirqd/322:45:113
28571994717,7cyclictest41-21ksoftirqd/323:20:013
28571994717,4cyclictest41-21ksoftirqd/322:40:223
28571994715,7cyclictest41-21ksoftirqd/323:35:273
28571994715,5cyclictest41-21ksoftirqd/322:10:123
28571994714,8cyclictest41-21ksoftirqd/320:40:243
2856899475,3cyclictest9-21ksoftirqd/000:40:010
28571994618,3cyclictest41-21ksoftirqd/323:30:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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