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2026-01-30 - 22:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jan 30, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299342220154,22sleep00-21swapper/007:09:220
298412203168,23sleep30-21swapper/307:08:183
299482202169,22sleep20-21swapper/207:09:322
298392202169,22sleep10-21swapper/107:08:161
3129321820,6sleep03027699cyclictest07:10:220
1012821640,6sleep33027999cyclictest10:55:223
2998528763,16sleep20-21swapper/207:10:002
1394918463,11phc2sys0-21swapper/307:10:013
79422760,7sleep13027799cyclictest12:00:131
31112760,5sleep13117-21cpuspeed_turbos09:35:121
139391700,1ptp4l401ktimersoftd/307:28:293
7122610,7sleep1241ktimersoftd/108:20:231
6062570,2sleep00-21swapper/008:20:220
139391560,1ptp4l401ktimersoftd/312:04:383
138262540,3sleep20-21swapper/209:55:242
139391520,1ptp4l401ktimersoftd/309:01:123
30278995115,10cyclictest33-21ksoftirqd/210:15:152
30279994439,3cyclictest41-21ksoftirqd/307:40:003
3027999440,2cyclictest121rcu_preempt08:10:003
139391440,5ptp4l3027999cyclictest09:47:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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