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2026-05-26 - 03:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue May 26, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
340822350,18sleep10-21swapper/119:05:121
139491229164,22phc2sys0-21swapper/319:07:433
50742204171,22sleep00-21swapper/019:06:540
50992203170,22sleep20-21swapper/219:07:082
139391710,1ptp4l401ktimersoftd/323:25:253
561699580,17cyclictest19888-21/usr/sbin/munin21:55:142
139391580,1ptp4l401ktimersoftd/323:02:263
139391580,1ptp4l401ktimersoftd/322:00:133
305642570,2sleep00-21swapper/020:00:210
5616995621,8cyclictest33-21ksoftirqd/219:32:092
561699553,19cyclictest23312-21latency_hist23:10:002
139391550,1ptp4l401ktimersoftd/300:05:193
561699528,10cyclictest14347-21expr20:35:152
5616995221,7cyclictest33-21ksoftirqd/223:28:212
5616995210,5cyclictest33-21ksoftirqd/221:15:052
561699520,9cyclictest32362-21cat00:35:002
5614995119,3cyclictest9-21ksoftirqd/023:04:090
5616994820,7cyclictest33-21ksoftirqd/222:23:582
561499484,6cyclictest8093-21awk23:45:000
561499482,5cyclictest31181-21strings00:30:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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