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2026-07-21 - 05:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jul 21, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
160572225162,51sleep00-21swapper/019:09:040
139491210177,22phc2sys0-21swapper/319:06:323
157842204172,21sleep10-21swapper/119:05:361
158472202168,23sleep20-21swapper/219:06:252
161302164124,14sleep00-21swapper/019:10:010
1792921590,2sleep11642399cyclictest21:25:241
1330121410,3sleep31642599cyclictest23:30:263
139391740,1ptp4l391rcuc/323:20:263
1642399720,70cyclictest0-21swapper/121:06:331
84602640,4sleep2321ktimersoftd/222:15:162
1642499636,17cyclictest0-21swapper/200:15:242
1642599629,27cyclictest9368-21latency_hist21:10:013
16424995811,12cyclictest22194-21kernelversion23:50:202
16422995829,19cyclictest9-21ksoftirqd/021:40:130
254402560,3sleep20-21swapper/221:40:302
1642499560,17cyclictest29214-21irqrtprio19:35:202
1642499560,16cyclictest4724-21grep21:00:132
1642499550,19cyclictest20342-21sed23:45:272
1642499550,16cyclictest25992-21egrep19:30:122
168732540,1sleep00-21swapper/022:30:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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