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2025-12-09 - 06:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Dec 09, 2025 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
220782205170,23sleep30-21swapper/319:06:093
223632204170,23sleep20-21swapper/219:09:432
220762203170,22sleep10-21swapper/119:06:071
220802200167,22sleep00-21swapper/019:06:110
2848121210,7sleep12268099cyclictest19:20:201
1371918363,11phc2sys0-21swapper/319:10:003
136991690,1ptp4l7320-21cpu19:45:123
22681996628,10cyclictest33-21ksoftirqd/220:59:592
22681996329,4cyclictest33-21ksoftirqd/221:50:002
22681996133,7cyclictest33-21ksoftirqd/223:45:002
136991600,1ptp4l401ktimersoftd/322:46:103
22681995830,4cyclictest33-21ksoftirqd/221:00:292
22681995829,4cyclictest33-21ksoftirqd/220:45:262
22681995825,4cyclictest33-21ksoftirqd/220:00:002
22681995824,5cyclictest33-21ksoftirqd/221:30:162
22681995630,4cyclictest33-21ksoftirqd/200:20:252
2267999561,25cyclictest1794-21iostat22:55:200
22681995529,7cyclictest33-21ksoftirqd/222:40:162
22681995524,7cyclictest33-21ksoftirqd/223:05:252
22681995524,7cyclictest33-21ksoftirqd/223:05:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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