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2026-04-04 - 12:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Apr 04, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205442204169,23sleep30-21swapper/319:05:403
207132203170,22sleep00-21swapper/019:07:450
205372203170,22sleep10-21swapper/119:05:331
208122201168,22sleep20-21swapper/219:09:032
1393911090,1ptp4l31650-21latency_hist22:55:013
2118199706,62cyclictest2804-21kworker/2:200:06:132
2118199655,57cyclictest17536-21kworker/2:020:00:332
279122620,2sleep30-21swapper/322:45:183
139391620,48ptp4l0-21swapper/319:10:013
21182996131,4cyclictest41-21ksoftirqd/320:50:143
21182996128,7cyclictest41-21ksoftirqd/320:45:183
21182996126,10cyclictest41-21ksoftirqd/319:50:143
21181996111,48cyclictest20645-21kworker/2:022:45:332
71002600,2sleep30-21swapper/320:55:153
21182996026,7cyclictest41-21ksoftirqd/320:29:593
21182995926,4cyclictest41-21ksoftirqd/319:30:153
21182995926,3cyclictest41-21ksoftirqd/323:15:013
21182995925,8cyclictest41-21ksoftirqd/321:55:013
294452580,2sleep10-21swapper/123:55:201
21182995827,4cyclictest41-21ksoftirqd/323:55:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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