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2026-01-17 - 14:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 17, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10172205172,22sleep10-21swapper/119:07:231
9232202168,23sleep20-21swapper/219:06:162
315002202171,20sleep00-21swapper/019:05:060
11832201166,23sleep30-21swapper/319:09:353
1532996926,4cyclictest9-21ksoftirqd/022:20:000
1532996662,2cyclictest9-21ksoftirqd/021:30:010
1534996128,4cyclictest33-21ksoftirqd/221:45:152
1534996125,5cyclictest33-21ksoftirqd/220:39:592
1532996121,5cyclictest9-21ksoftirqd/021:45:160
1532996120,5cyclictest9-21ksoftirqd/019:30:140
1532996116,4cyclictest9-21ksoftirqd/020:30:180
153599596,18cyclictest24300-21/usr/sbin/munin00:25:183
166642570,5sleep116668-21needreboot23:00:221
1534995728,5cyclictest33-21ksoftirqd/222:40:002
1534995721,5cyclictest33-21ksoftirqd/220:04:592
1534995625,7cyclictest33-21ksoftirqd/223:10:172
1532995622,4cyclictest9-21ksoftirqd/022:10:180
1534995524,4cyclictest33-21ksoftirqd/200:00:232
1534995520,6cyclictest33-21ksoftirqd/223:35:002
1534995424,4cyclictest33-21ksoftirqd/219:30:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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