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2026-09-17 - 11:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Sep 17, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1541423540,6sleep30-21swapper/319:09:213
75322710,5sleep2718-21sh19:08:282
1191622240,4sleep1241ktimersoftd/119:09:161
210022170,7sleep02108-21tee19:09:580
1878521430,2sleep3466699cyclictest19:11:593
3108321410,5sleep231088-21tee19:10:422
293372830,3sleep129295-21sh19:12:121
4665996520,4cyclictest33-21ksoftirqd/219:51:212
466399656,57cyclictest0-21swapper/121:00:331
236932630,6sleep3466699cyclictest00:30:153
4665996030,3cyclictest33-21ksoftirqd/219:45:252
4665996026,9cyclictest33-21ksoftirqd/220:25:132
299542600,2sleep00-21swapper/021:20:180
299542600,2sleep00-21swapper/021:20:180
4665995929,6cyclictest33-21ksoftirqd/219:30:142
4665995921,6cyclictest33-21ksoftirqd/200:35:222
4665995825,4cyclictest33-21ksoftirqd/200:05:302
4665995823,4cyclictest33-21ksoftirqd/222:20:212
285072580,1sleep00-21swapper/020:10:170
285072580,1sleep00-21swapper/020:10:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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