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2026-08-12 - 07:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Aug 12, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223872206172,22sleep10-21swapper/119:06:181
225682205172,22sleep20-21swapper/219:08:402
139491204169,23phc2sys0-21swapper/319:09:193
223322201167,23sleep00-21swapper/019:05:370
139391770,1ptp4l401ktimersoftd/322:05:243
139391670,1ptp4l401ktimersoftd/322:41:043
139391670,1ptp4l401ktimersoftd/319:21:163
22965996429,3cyclictest33-21ksoftirqd/221:30:002
22965996132,8cyclictest33-21ksoftirqd/222:55:002
22965996126,5cyclictest33-21ksoftirqd/222:50:002
22965995922,7cyclictest33-21ksoftirqd/223:05:262
22965995830,7cyclictest33-21ksoftirqd/220:55:242
22965995829,7cyclictest33-21ksoftirqd/223:25:192
139391580,1ptp4l401ktimersoftd/320:15:243
139391580,1ptp4l391rcuc/322:15:223
22965995725,4cyclictest33-21ksoftirqd/219:30:242
22965995724,4cyclictest33-21ksoftirqd/220:20:002
22965995723,4cyclictest33-21ksoftirqd/223:55:202
180712570,1sleep00-21swapper/023:30:010
129152570,6sleep09-21ksoftirqd/000:25:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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