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2026-06-26 - 23:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jun 26, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2449421820,6sleep2564199cyclictest07:25:502
767621810,6sleep1564099cyclictest07:12:181
3191221800,6sleep2564199cyclictest07:33:212
769521640,3sleep3564299cyclictest07:12:323
1501221610,6sleep0563999cyclictest07:30:070
5291210962,15sleep00-21swapper/007:09:170
5022210762,16sleep30-21swapper/307:06:003
5050210563,10sleep10-21swapper/107:06:221
650621040,3sleep3401ktimersoftd/307:33:313
500629167,16sleep20-21swapper/207:05:462
81422880,4sleep38146-21unixbench_multi08:30:263
289902790,7sleep1564099cyclictest07:26:311
76182760,7sleep2564199cyclictest07:11:472
139391700,1ptp4l391rcuc/308:45:243
77252680,3sleep07716-21execl07:12:410
323472660,3sleep10-21swapper/107:34:061
256442630,4sleep0563999cyclictest12:30:210
173882620,5sleep313265-21spawn07:25:003
173882620,5sleep313265-21spawn07:25:003
238402610,6sleep323848-21spawn07:25:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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