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2026-06-23 - 05:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 23, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28482235168,23sleep20-21swapper/219:08:162
139491206172,22phc2sys0-21swapper/319:08:583
28462205172,22sleep00-21swapper/019:08:140
26342205172,22sleep10-21swapper/119:05:351
139391770,1ptp4l391rcuc/320:05:183
327699584,6cyclictest8754-21sh20:30:003
327699567,5cyclictest41-21ksoftirqd/319:15:153
3276995510,5cyclictest41-21ksoftirqd/320:20:223
3276995510,5cyclictest41-21ksoftirqd/320:20:223
3275995522,4cyclictest33-21ksoftirqd/223:20:002
3276995418,4cyclictest41-21ksoftirqd/322:30:113
327399543,9cyclictest14400-21cpuspeed_turbos22:55:140
327399534,7cyclictest8036-21cut22:40:180
3273995220,3cyclictest9-21ksoftirqd/022:09:120
122262520,7sleep3327699cyclictest22:50:133
327699514,7cyclictest26963-21latency_hist20:00:003
3273995120,3cyclictest9-21ksoftirqd/019:58:310
3275995015,6cyclictest33-21ksoftirqd/200:20:002
3275995015,4cyclictest33-21ksoftirqd/219:25:002
57898490,12rtkit-daemon577-21rtkit-daemon23:02:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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