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2026-09-06 - 17:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Sep 06, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491213168,33phc2sys0-21swapper/307:09:533
77542203168,23sleep00-21swapper/007:08:230
75682203169,23sleep20-21swapper/207:06:002
77072202170,21sleep10-21swapper/107:07:481
2745521560,3sleep3823599cyclictest11:10:203
139391660,1ptp4l10082-21cat08:20:143
62822630,2sleep00-21swapper/010:25:240
225042590,6sleep0823299cyclictest07:40:130
199012570,5sleep3823599cyclictest09:49:593
139391550,1ptp4l401ktimersoftd/307:58:243
98732540,2sleep20-21swapper/209:25:242
27152520,4sleep2321ktimersoftd/208:05:132
114672490,3sleep011470-21fschecks_time11:45:150
139391480,1ptp4l401ktimersoftd/309:54:113
100492480,2sleep20-21swapper/208:20:132
139391450,1ptp4l401ktimersoftd/310:05:303
139391450,1ptp4l401ktimersoftd/308:09:573
139391450,0ptp4l401ktimersoftd/309:42:283
139391430,0ptp4l401ktimersoftd/312:04:453
139391420,0ptp4l401ktimersoftd/309:07:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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