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2026-01-31 - 18:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 31, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291372215171,32sleep10-21swapper/107:08:081
292232206173,23sleep30-21swapper/307:09:153
291652202168,23sleep20-21swapper/207:08:282
271482201168,22sleep00-21swapper/007:05:050
1394918965,15phc2sys0-21swapper/307:10:013
237492810,2sleep20-21swapper/212:35:142
139391780,1ptp4l391rcuc/308:35:253
139391720,1ptp4l391rcuc/310:05:363
106142690,6sleep32958499cyclictest09:50:253
2958499547,45cyclictest15955-21kworker/3:212:33:333
139391540,1ptp4l391rcuc/309:00:513
34972530,2sleep30-21swapper/308:30:123
2958499484,42cyclictest4957-21kworker/3:007:33:133
29583994531,12cyclictest33-21ksoftirqd/210:15:012
29582994537,5cyclictest20860-21dump-pmu-power10:15:001
134391440,8getstats2958499cyclictest08:27:143
139391430,0ptp4l401ktimersoftd/312:00:273
139391430,0ptp4l401ktimersoftd/309:47:363
139391420,0ptp4l401ktimersoftd/310:40:063
139391420,0ptp4l401ktimersoftd/308:46:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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