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2026-07-22 - 21:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jul 22, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227164,51phc2sys0-21swapper/307:07:223
25912204170,22sleep10-21swapper/107:09:021
23912204171,22sleep00-21swapper/007:07:080
26072199165,23sleep20-21swapper/207:09:142
57898920,71rtkit-daemon0-21swapper/307:10:003
123312720,1sleep10-21swapper/112:00:001
139391660,1ptp4l401ktimersoftd/309:43:333
17642650,2sleep10-21swapper/109:20:231
2960996330,6cyclictest9-21ksoftirqd/010:50:000
168802610,2sleep20-21swapper/211:00:172
2960996029,9cyclictest9-21ksoftirqd/010:00:150
2960996028,11cyclictest9-21ksoftirqd/011:25:140
273502590,2sleep10-21swapper/109:05:271
2961995721,5cyclictest25-21ksoftirqd/110:59:061
2961995714,9cyclictest25-21ksoftirqd/111:40:211
2960995733,2cyclictest9-21ksoftirqd/012:30:120
2960995728,10cyclictest9-21ksoftirqd/007:20:130
2960995727,9cyclictest9-21ksoftirqd/011:55:180
139391560,1ptp4l401ktimersoftd/307:56:593
296199555,9cyclictest25-21ksoftirqd/112:15:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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