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2025-08-29 - 14:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Aug 29, 2025 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112092231166,22sleep10-21swapper/119:08:521
112092231166,22sleep10-21swapper/119:08:511
137191208173,23phc2sys0-21swapper/319:08:543
137191208173,23phc2sys0-21swapper/319:08:543
110912203170,22sleep20-21swapper/219:07:192
110912203170,22sleep20-21swapper/219:07:192
112922202169,22sleep00-21swapper/019:09:550
112922202169,22sleep00-21swapper/019:09:540
1575621380,5sleep31159499cyclictest22:40:143
1130028163,10sleep20-21swapper/219:10:002
109302810,2sleep10-21swapper/123:35:251
109302810,2sleep10-21swapper/123:35:251
236402760,2sleep00-21swapper/021:50:000
11592996419,9cyclictest25-21ksoftirqd/123:40:221
11592996224,7cyclictest25-21ksoftirqd/100:29:031
11592996224,10cyclictest25-21ksoftirqd/119:55:281
136991610,1ptp4l401ktimersoftd/321:36:413
11592995923,4cyclictest25-21ksoftirqd/122:10:191
11592995822,8cyclictest25-21ksoftirqd/122:55:261
11592995822,4cyclictest25-21ksoftirqd/100:20:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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