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2026-07-10 - 15:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 10, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171172237191,35sleep20-21swapper/207:08:592
139491235197,28phc2sys0-21swapper/307:08:593
150602202169,22sleep10-21swapper/107:05:041
150592202169,22sleep00-21swapper/007:05:030
777521700,6sleep01748899cyclictest11:20:120
1719628162,10sleep30-21swapper/307:10:003
139391570,1ptp4l401ktimersoftd/309:54:373
74632560,5sleep0520-21cron11:20:000
137572560,35sleep125-21ksoftirqd/108:10:151
231202530,2sleep00-21swapper/011:50:220
139391530,1ptp4l401ktimersoftd/311:50:513
137112510,2sleep20-21swapper/209:15:232
17489995045,3cyclictest21737-21cat11:50:001
93682470,2sleep00-21swapper/008:00:150
139391460,1ptp4l401ktimersoftd/312:39:413
139391460,1ptp4l401ktimersoftd/312:39:403
139391430,1ptp4l401ktimersoftd/308:43:273
139391430,0ptp4l401ktimersoftd/308:48:173
17490994235,4cyclictest14595-21idleruntime-cro11:35:002
139391420,0ptp4l401ktimersoftd/311:49:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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