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2026-01-02 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jan 02, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26252234168,22sleep30-21swapper/307:08:173
27312207168,21sleep20-21swapper/207:09:332
27252202169,22sleep10-21swapper/107:09:281
24312201168,22sleep00-21swapper/007:06:210
3037521680,6sleep1306399cyclictest08:05:191
1766021590,6sleep3306599cyclictest09:55:013
644821390,6sleep2306499cyclictest09:30:152
325082650,3sleep10-21swapper/111:30:251
3064995535,3cyclictest10002-21perf07:25:002
284392520,2sleep00-21swapper/009:10:000
306399480,1cyclictest0-21swapper/111:10:241
3064994439,3cyclictest7586-21cron07:20:002
3064994438,4cyclictest1948-21cat10:30:012
3064994438,4cyclictest1948-21cat10:30:012
3064994329,12cyclictest12355-21cron07:30:002
139391430,0ptp4l401ktimersoftd/308:00:253
139391420,0ptp4l401ktimersoftd/312:15:423
139391420,0ptp4l401ktimersoftd/311:05:243
139391420,0ptp4l401ktimersoftd/310:45:483
139391420,0ptp4l401ktimersoftd/308:44:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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