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2026-08-29 - 14:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Aug 29, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208175,22phc2sys0-21swapper/319:08:203
190302207175,21sleep10-21swapper/119:07:521
190872201168,22sleep00-21swapper/019:08:360
191772196163,22sleep20-21swapper/219:09:462
1489021540,6sleep31949099cyclictest00:35:213
19487997034,6cyclictest9-21ksoftirqd/022:55:000
139391640,1ptp4l401ktimersoftd/323:06:563
19487996229,7cyclictest9-21ksoftirqd/022:00:270
19487996229,4cyclictest9-21ksoftirqd/023:25:230
19487996131,6cyclictest9-21ksoftirqd/021:50:260
19487996130,4cyclictest9-21ksoftirqd/019:35:120
19487996129,9cyclictest9-21ksoftirqd/023:45:220
19487996129,3cyclictest9-21ksoftirqd/023:25:000
19487996128,6cyclictest9-21ksoftirqd/023:35:140
19487996128,5cyclictest9-21ksoftirqd/000:30:170
19487996128,3cyclictest9-21ksoftirqd/023:55:230
19487996126,8cyclictest9-21ksoftirqd/019:30:160
19487996126,8cyclictest9-21ksoftirqd/019:30:160
19487996031,4cyclictest9-21ksoftirqd/021:00:010
19487996027,5cyclictest9-21ksoftirqd/000:25:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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