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2026-05-04 - 11:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon May 04, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133952206173,22sleep30-21swapper/319:09:343
133952206173,22sleep30-21swapper/319:09:343
133322203169,23sleep20-21swapper/219:08:462
133322203169,23sleep20-21swapper/219:08:462
133002202168,22sleep00-21swapper/019:08:190
133002202168,22sleep00-21swapper/019:08:190
132742202170,20sleep10-21swapper/119:07:591
132742202170,20sleep10-21swapper/119:07:591
139391540,1ptp4l401ktimersoftd/323:16:033
1394915336,10phc2sys0-21swapper/319:10:003
65532500,2sleep30-21swapper/323:25:153
89792470,3sleep28982-21idleruntime23:30:162
13724994627,8cyclictest41-21ksoftirqd/320:00:163
139391430,0ptp4l401ktimersoftd/321:29:513
139391430,0ptp4l401ktimersoftd/319:19:173
13721994327,5cyclictest9-21ksoftirqd/020:50:190
139391420,0ptp4l401ktimersoftd/322:03:133
139391420,0ptp4l401ktimersoftd/320:30:053
139391420,0ptp4l401ktimersoftd/300:22:163
139391410,0ptp4l401ktimersoftd/322:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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