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2026-04-28 - 21:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Apr 28, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206171,23phc2sys0-21swapper/307:09:053
324352205172,22sleep20-21swapper/207:06:462
323822205173,21sleep10-21swapper/107:06:051
325512204171,22sleep00-21swapper/007:08:160
2944021730,6sleep353299cyclictest10:23:263
104721640,6sleep153099cyclictest08:15:241
532997133,10cyclictest41-21ksoftirqd/310:50:253
532996522,10cyclictest41-21ksoftirqd/310:30:003
530996430,8cyclictest25-21ksoftirqd/110:15:001
532996321,4cyclictest41-21ksoftirqd/310:18:003
530996325,9cyclictest25-21ksoftirqd/112:10:131
530996325,8cyclictest25-21ksoftirqd/108:20:271
3722630,5sleep052999cyclictest10:30:170
532996227,10cyclictest41-21ksoftirqd/310:45:163
530996233,4cyclictest25-21ksoftirqd/110:05:281
530996220,9cyclictest25-21ksoftirqd/107:10:261
530996220,8cyclictest25-21ksoftirqd/111:15:141
530996126,7cyclictest25-21ksoftirqd/111:10:131
530996126,7cyclictest25-21ksoftirqd/110:45:011
530996121,7cyclictest25-21ksoftirqd/109:55:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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