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2026-01-10 - 07:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 10, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206172,22phc2sys0-21swapper/319:09:223
281682202169,22sleep20-21swapper/219:06:182
281672201168,22sleep10-21swapper/119:06:161
283302195162,22sleep00-21swapper/019:08:250
28749996630,4cyclictest33-21ksoftirqd/219:30:002
28747996630,9cyclictest9-21ksoftirqd/000:10:000
28747996530,7cyclictest9-21ksoftirqd/020:10:150
28747996428,7cyclictest9-21ksoftirqd/020:50:230
28747996426,6cyclictest9-21ksoftirqd/021:05:130
28747996330,5cyclictest9-21ksoftirqd/022:20:000
28747996329,6cyclictest9-21ksoftirqd/023:01:290
28747996328,7cyclictest9-21ksoftirqd/023:15:270
28747996328,7cyclictest9-21ksoftirqd/023:15:260
28747996327,6cyclictest9-21ksoftirqd/020:05:130
28747996325,6cyclictest9-21ksoftirqd/020:30:530
28749996233,4cyclictest33-21ksoftirqd/221:55:172
28749996230,9cyclictest33-21ksoftirqd/219:15:132
2874899629,12cyclictest28798-21cat23:40:001
28747996229,6cyclictest9-21ksoftirqd/022:45:010
28747996229,6cyclictest9-21ksoftirqd/022:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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