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2026-08-23 - 13:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Aug 23, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79282229164,21sleep20-21swapper/219:06:492
139491207173,23phc2sys0-21swapper/319:08:063
79312202168,22sleep00-21swapper/019:06:510
81462201168,22sleep10-21swapper/119:08:571
2917221750,6sleep2852199cyclictest23:15:132
139391990,1ptp4l5079-21tr20:10:123
822828663,15sleep00-21swapper/019:10:010
822828663,15sleep00-21swapper/019:10:010
139391570,6ptp4l852299cyclictest20:35:283
139391570,1ptp4l401ktimersoftd/321:10:413
200662550,1sleep00-21swapper/022:55:160
283752520,2sleep20-21swapper/200:20:152
283752520,2sleep20-21swapper/200:20:152
134391510,3getstats8518-21cyclictest22:10:113
139391460,0ptp4l401ktimersoftd/320:50:163
139391440,1ptp4l401ktimersoftd/319:50:203
139391440,0ptp4l401ktimersoftd/322:00:333
139391430,0ptp4l401ktimersoftd/300:37:273
57898420,9rtkit-daemon0-21swapper/119:28:341
139391420,0ptp4l401ktimersoftd/323:32:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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