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2026-05-23 - 04:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat May 23, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,23phc2sys0-21swapper/319:08:473
41892205172,22sleep00-21swapper/019:05:400
44302203170,22sleep20-21swapper/219:08:432
43772203170,22sleep10-21swapper/119:08:011
4824997436,7cyclictest41-21ksoftirqd/321:50:013
4824996630,7cyclictest41-21ksoftirqd/321:50:243
4824996338,3cyclictest41-21ksoftirqd/322:24:263
297442630,4sleep1482299cyclictest22:10:251
4824996228,4cyclictest41-21ksoftirqd/323:10:003
4824996126,4cyclictest41-21ksoftirqd/320:30:013
4824996029,4cyclictest41-21ksoftirqd/322:05:183
4824996028,4cyclictest41-21ksoftirqd/321:35:183
4824996025,5cyclictest41-21ksoftirqd/300:25:233
176042600,4sleep11-21systemd21:49:551
217882590,2sleep20-21swapper/219:45:012
4824995830,7cyclictest41-21ksoftirqd/320:05:003
4824995825,4cyclictest41-21ksoftirqd/321:10:153
281972580,2sleep1231rcuc/100:24:591
4824995726,6cyclictest41-21ksoftirqd/320:10:153
4824995629,3cyclictest41-21ksoftirqd/319:50:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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