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2026-01-24 - 14:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 24, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491211167,33phc2sys0-21swapper/319:06:063
319862203169,23sleep20-21swapper/219:08:032
318382201168,22sleep10-21swapper/119:06:131
318152201168,22sleep00-21swapper/019:05:550
1249521200,6sleep03242599cyclictest20:40:230
139391700,1ptp4l401ktimersoftd/323:49:323
139391660,1ptp4l401ktimersoftd/300:35:163
110822550,3sleep311088-21irqrtprio21:45:173
139391500,1ptp4l391rcuc/323:55:383
139391430,0ptp4l401ktimersoftd/322:00:013
139391430,0ptp4l401ktimersoftd/319:50:083
139391420,0ptp4l401ktimersoftd/320:40:183
139391410,1ptp4l0-21swapper/322:20:263
32427994020,18cyclictest33-21ksoftirqd/220:25:002
32427993826,11cyclictest33-21ksoftirqd/221:05:002
32427993729,5cyclictest33-21ksoftirqd/219:24:112
32426993732,3cyclictest25-21ksoftirqd/120:20:011
32426993632,3cyclictest25-21ksoftirqd/120:40:131
32426993631,3cyclictest25-21ksoftirqd/120:00:101
32426993631,3cyclictest25-21ksoftirqd/119:45:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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