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2026-08-01 - 19:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Aug 01, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190232235167,22sleep10-21swapper/107:08:241
139491210175,23phc2sys0-21swapper/307:09:063
190892208174,23sleep00-21swapper/007:09:160
190142205172,22sleep20-21swapper/207:08:172
229092670,5sleep341-21ksoftirqd/307:15:203
223292670,3sleep20-21swapper/207:15:152
19449996130,4cyclictest33-21ksoftirqd/209:20:002
19449995922,6cyclictest33-21ksoftirqd/211:45:002
231792580,2sleep30-21swapper/310:40:153
129782580,1sleep30-21swapper/312:35:013
129782580,1sleep30-21swapper/312:35:013
19449995524,3cyclictest33-21ksoftirqd/207:10:212
19449995423,3cyclictest33-21ksoftirqd/212:24:592
19449995420,8cyclictest33-21ksoftirqd/208:25:272
139391540,1ptp4l401ktimersoftd/309:19:433
139391540,1ptp4l391rcuc/312:05:053
67942530,2sleep20-21swapper/208:55:282
139391530,1ptp4l401ktimersoftd/309:28:513
127702530,3sleep2311rcuc/210:15:272
127702530,3sleep2311rcuc/210:15:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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