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2026-02-14 - 13:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 14, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172072206172,23sleep10-21swapper/119:06:421
171872204169,23sleep30-21swapper/319:06:283
171422202170,21sleep20-21swapper/219:05:562
171892200167,22sleep00-21swapper/019:06:300
737821640,5sleep21775399cyclictest22:10:002
60021550,6sleep31775499cyclictest23:00:243
2854721520,5sleep11775299cyclictest22:50:261
3205821330,5sleep11775299cyclictest21:50:251
1775199618,11cyclictest26997-21sed20:35:180
1775199594,11cyclictest879-21cat20:50:000
257462570,2sleep00-21swapper/021:40:130
1775199574,11cyclictest3320-21sort22:00:170
1775199564,17cyclictest31492-21cat00:05:170
1775199557,11cyclictest22591-21open_inodes23:45:220
1775199556,10cyclictest15265-21/usr/sbin/munin20:10:180
1775199555,17cyclictest1-21systemd20:20:250
1775199554,12cyclictest14055-21cpu23:30:120
1775199544,15cyclictest13891-21cat23:30:010
1775199544,11cyclictest653-21sed21:55:140
1775199538,10cyclictest17986-21awk20:15:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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