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2026-01-25 - 03:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jan 25, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69682207172,24sleep20-21swapper/219:09:142
48462204171,22sleep10-21swapper/119:05:021
139491203169,22phc2sys0-21swapper/319:06:473
68162202168,23sleep00-21swapper/019:07:150
2254321530,5sleep3732499cyclictest19:40:183
732299710,69cyclictest0-21swapper/123:40:331
325712560,5sleep125-21ksoftirqd/122:15:011
7324995533,19cyclictest207-21systemd-journal23:40:003
732199545,22cyclictest10630-21taskset20:21:200
202572520,1sleep10-21swapper/100:00:271
116172500,2sleep00-21swapper/021:30:150
116172500,2sleep00-21swapper/021:30:150
732299490,1cyclictest0-21swapper/121:15:331
7321994812,25cyclictest26024-21seq23:05:340
7322994734,10cyclictest25-21ksoftirqd/123:40:001
7322994616,28cyclictest0-21swapper/120:40:231
732499457,36cyclictest5295-21kworker/3:223:41:123
732299440,42cyclictest0-21swapper/120:25:231
7323994336,4cyclictest523-21cron00:30:002
703024232,4sleep10-21swapper/119:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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