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2026-07-11 - 16:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 11, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327632207172,24sleep30-21swapper/307:06:303
3622204170,22sleep00-21swapper/007:07:150
5242203170,22sleep20-21swapper/207:09:182
327362203170,22sleep10-21swapper/107:06:081
2715521770,3sleep191099cyclictest08:05:011
2861321470,3sleep291199cyclictest09:15:142
2026221360,3sleep291199cyclictest08:55:242
23052580,1sleep30-21swapper/309:25:263
267652570,4sleep026764-21unixbench_multi12:30:290
139391550,1ptp4l391rcuc/307:55:153
90999542,2cyclictest5475-21seq11:48:320
139391540,1ptp4l401ktimersoftd/312:35:213
139391540,1ptp4l401ktimersoftd/308:29:273
139391540,1ptp4l401ktimersoftd/308:29:263
139391530,1ptp4l401ktimersoftd/309:58:473
139391500,1ptp4l391rcuc/307:40:363
3052490,2sleep30-21swapper/308:15:183
91199470,45cyclictest0-21swapper/209:50:232
139391460,0ptp4l401ktimersoftd/312:09:123
134391460,1getstats0-21swapper/309:30:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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