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2026-08-03 - 12:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 03, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88072232172,48sleep30-21swapper/319:09:033
86542227162,21sleep10-21swapper/119:07:041
87432204171,22sleep20-21swapper/219:08:152
86262202170,22sleep00-21swapper/019:06:440
2388121240,2sleep00-21swapper/021:55:160
9175997011,17cyclictest16443-21turbostat23:54:592
9173996832,10cyclictest9-21ksoftirqd/023:15:140
139391680,1ptp4l401ktimersoftd/300:25:183
917599660,26cyclictest0-21swapper/223:15:162
917599630,22cyclictest26693-21idleruntime-cro23:10:002
917599620,20cyclictest11490-21latency_hist19:15:012
917599620,20cyclictest11490-21latency_hist19:15:012
9173996226,5cyclictest9-21ksoftirqd/000:00:000
9173996225,4cyclictest9-21ksoftirqd/020:10:170
917599610,21cyclictest28028-21sed00:15:282
917599610,20cyclictest3411-21date00:35:012
917599600,21cyclictest21873-21cut19:35:172
917599600,21cyclictest18945-21date00:00:002
289072600,2sleep20-21swapper/222:05:172
917599590,26cyclictest11365-21cat21:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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