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2025-12-15 - 18:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 15, 2025 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
191782217186,21sleep10-21swapper/107:08:241
192912213180,22sleep20-21swapper/207:09:552
192302212179,22sleep30-21swapper/307:09:073
191772211178,22sleep00-21swapper/007:08:240
1279221310,6sleep11959599cyclictest08:00:481
1930228262,11sleep00-21swapper/007:10:010
244652580,5sleep01959499cyclictest11:50:000
72002550,1sleep10-21swapper/112:20:381
19595995347,3cyclictest207-21systemd-journal12:05:011
139391480,1ptp4l401ktimersoftd/307:47:133
19597994741,3cyclictest15781-21sh08:10:013
19596994437,4cyclictest25636-21cron10:45:012
139391440,0ptp4l401ktimersoftd/310:05:053
19595994338,3cyclictest25-21ksoftirqd/108:20:001
139391430,1ptp4l401ktimersoftd/310:04:073
139391430,0ptp4l401ktimersoftd/309:16:363
1959499411,37cyclictest6011-21cron07:50:000
19594994035,3cyclictest9-21ksoftirqd/012:00:000
139391400,0ptp4l401ktimersoftd/309:20:493
19595993935,2cyclictest25-21ksoftirqd/107:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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