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2026-01-02 - 07:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jan 02, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491231164,23phc2sys0-21swapper/319:07:143
68962202170,22sleep20-21swapper/219:09:152
68132202168,22sleep10-21swapper/119:08:081
67392197164,22sleep00-21swapper/019:07:120
210821390,7sleep0724999cyclictest22:20:130
1394918464,11phc2sys0-21swapper/319:10:013
7249996427,6cyclictest9-21ksoftirqd/019:35:160
7249996329,6cyclictest9-21ksoftirqd/019:55:280
139391630,1ptp4l401ktimersoftd/323:03:453
7249996231,7cyclictest9-21ksoftirqd/020:15:000
7249996230,4cyclictest9-21ksoftirqd/021:40:000
7249996226,6cyclictest9-21ksoftirqd/020:05:250
7249996226,6cyclictest9-21ksoftirqd/020:05:250
7249996126,6cyclictest9-21ksoftirqd/023:45:010
7249996126,5cyclictest9-21ksoftirqd/000:15:180
109902610,1sleep30-21swapper/319:15:243
7249996029,5cyclictest9-21ksoftirqd/023:25:230
7249996028,4cyclictest9-21ksoftirqd/000:30:260
7249996026,4cyclictest9-21ksoftirqd/000:35:160
7249996024,6cyclictest9-21ksoftirqd/022:10:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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