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2026-02-09 - 16:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 09, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491229163,22phc2sys0-21swapper/307:09:593
215362204170,22sleep20-21swapper/207:09:472
212412201168,22sleep00-21swapper/007:05:590
212072200169,21sleep10-21swapper/107:05:331
2772821830,6sleep12185099cyclictest10:45:231
2760121700,5sleep32185299cyclictest07:20:183
215572162124,13sleep30-21swapper/307:10:013
977021550,2sleep00-21swapper/009:00:010
139391870,1ptp4l2635-21/usr/sbin/munin08:45:263
21849996424,6cyclictest9-21ksoftirqd/008:10:170
21849996324,6cyclictest9-21ksoftirqd/008:35:270
21849996323,7cyclictest9-21ksoftirqd/010:55:240
21849996323,7cyclictest9-21ksoftirqd/007:35:160
21849996229,6cyclictest9-21ksoftirqd/010:45:000
21849996224,4cyclictest9-21ksoftirqd/011:50:210
21849996223,6cyclictest9-21ksoftirqd/011:00:170
21849996222,6cyclictest9-21ksoftirqd/007:15:160
21849996127,6cyclictest9-21ksoftirqd/009:45:150
21849996126,8cyclictest9-21ksoftirqd/012:20:180
21849996125,7cyclictest9-21ksoftirqd/009:25:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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