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2026-04-24 - 05:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Apr 24, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
227792206174,21sleep00-21swapper/019:07:420
227772204170,23sleep30-21swapper/319:07:413
227542203170,22sleep20-21swapper/219:07:242
226112202170,22sleep10-21swapper/119:05:381
987521380,5sleep22342999cyclictest00:15:242
23425996431,4cyclictest9-21ksoftirqd/020:30:010
23429996126,6cyclictest33-21ksoftirqd/223:45:142
23425996025,4cyclictest9-21ksoftirqd/021:29:480
23425995932,4cyclictest9-21ksoftirqd/000:25:000
23425995928,4cyclictest9-21ksoftirqd/000:30:000
23425995923,5cyclictest9-21ksoftirqd/022:41:360
23425995831,6cyclictest9-21ksoftirqd/021:10:010
23425995831,6cyclictest9-21ksoftirqd/021:10:000
23425995828,4cyclictest9-21ksoftirqd/000:15:170
23429995722,5cyclictest33-21ksoftirqd/220:00:112
23425995723,7cyclictest9-21ksoftirqd/021:20:230
23425995722,3cyclictest9-21ksoftirqd/023:40:190
23425995720,8cyclictest9-21ksoftirqd/022:00:130
23425995717,6cyclictest9-21ksoftirqd/023:20:210
23425995715,8cyclictest9-21ksoftirqd/020:00:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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