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2026-08-14 - 22:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Aug 14, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491209176,22phc2sys0-21swapper/307:09:173
261332206174,21sleep20-21swapper/207:09:172
258412204170,22sleep10-21swapper/107:05:351
258392204170,23sleep00-21swapper/007:05:330
26480996623,6cyclictest9-21ksoftirqd/008:35:300
26480996225,7cyclictest9-21ksoftirqd/010:05:190
139391610,1ptp4l401ktimersoftd/309:01:543
26480995933,4cyclictest9-21ksoftirqd/009:55:230
26481995824,7cyclictest25-21ksoftirqd/108:15:001
26480995831,5cyclictest9-21ksoftirqd/010:25:170
26480995826,7cyclictest9-21ksoftirqd/011:35:160
26480995428,4cyclictest9-21ksoftirqd/007:15:200
26480995420,6cyclictest9-21ksoftirqd/010:45:170
139391540,1ptp4l401ktimersoftd/308:05:223
2648199535,9cyclictest25-21ksoftirqd/112:30:261
2648199535,9cyclictest25-21ksoftirqd/110:25:181
26481995321,4cyclictest25-21ksoftirqd/112:23:031
26480995324,9cyclictest9-21ksoftirqd/010:50:200
26480995321,5cyclictest9-21ksoftirqd/011:00:150
26480995316,4cyclictest9-21ksoftirqd/008:55:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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