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2026-08-11 - 16:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Aug 11, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491220158,51phc2sys0-21swapper/307:09:183
179422206173,22sleep20-21swapper/207:05:272
182842203170,22sleep10-21swapper/107:09:431
181102203170,22sleep00-21swapper/007:07:340
139391550,1ptp4l401ktimersoftd/312:15:433
139391480,1ptp4l401ktimersoftd/311:10:033
139391440,0ptp4l401ktimersoftd/312:14:433
139391440,0ptp4l401ktimersoftd/307:55:003
139391420,0ptp4l401ktimersoftd/309:25:013
1830624132,3sleep20-21swapper/207:10:012
139391410,0ptp4l401ktimersoftd/310:03:243
18771994035,3cyclictest25-21ksoftirqd/111:00:001
18771994034,3cyclictest25-21ksoftirqd/111:40:001
139391400,1ptp4l401ktimersoftd/311:52:173
57898390,8rtkit-daemon0-21swapper/011:45:050
18774993931,5cyclictest41-21ksoftirqd/308:05:013
18773993925,12cyclictest33-21ksoftirqd/208:59:392
18771993932,4cyclictest7573-21cron10:10:001
139391390,0ptp4l401ktimersoftd/309:42:323
18771993832,4cyclictest25-21ksoftirqd/109:45:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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