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2026-09-18 - 04:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Sep 18, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94232221154,22sleep10-21swapper/119:09:541
139491207172,23phc2sys0-21swapper/319:06:463
93992203170,22sleep00-21swapper/019:09:370
93092203170,22sleep20-21swapper/219:08:262
2410521410,3sleep3986099cyclictest00:07:023
139391730,0ptp4l391rcuc/323:35:243
12632700,2sleep00-21swapper/023:20:170
318122620,1sleep00-21swapper/022:10:130
118392620,4sleep311827-21turbostat21:30:003
9860995828,7cyclictest41-21ksoftirqd/323:55:013
9860995822,7cyclictest41-21ksoftirqd/323:45:223
986099574,5cyclictest0-21swapper/323:31:523
9860995729,3cyclictest41-21ksoftirqd/300:10:283
9860995728,7cyclictest41-21ksoftirqd/321:40:273
9860995728,7cyclictest41-21ksoftirqd/300:35:273
9860995722,11cyclictest41-21ksoftirqd/320:00:283
9860995721,7cyclictest41-21ksoftirqd/319:30:173
9860995525,10cyclictest41-21ksoftirqd/322:50:003
9860995521,9cyclictest41-21ksoftirqd/322:15:233
9860995429,7cyclictest41-21ksoftirqd/319:55:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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