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2025-11-24 - 16:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Nov 24, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12182248191,46sleep20-21swapper/207:09:582
137191221154,22phc2sys0-21swapper/307:08:433
10202204171,22sleep10-21swapper/107:07:291
9672201168,22sleep00-21swapper/007:06:470
101242640,4sleep10-21swapper/107:25:261
206202610,2sleep20-21swapper/212:20:002
136991600,1ptp4l6467-1kworker/3:2H08:50:283
136991530,2ptp4l401ktimersoftd/309:27:183
1536994336,4cyclictest481-21rs:main2
136991430,0ptp4l401ktimersoftd/310:35:233
136991430,0ptp4l401ktimersoftd/310:35:233
136991430,0ptp4l401ktimersoftd/307:13:443
136991410,0ptp4l401ktimersoftd/312:05:263
136991410,0ptp4l401ktimersoftd/310:15:113
290122400,4sleep10-21swapper/112:35:231
136991400,0ptp4l401ktimersoftd/312:25:223
153699398,30cyclictest8321-21kworker/2:108:33:482
153699398,30cyclictest8321-21kworker/2:108:33:472
1534993935,2cyclictest481-21rs:main0
1534993933,3cyclictest9-21ksoftirqd/009:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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