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2026-08-17 - 12:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 17, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131152234169,22sleep10-21swapper/119:05:391
139491207173,23phc2sys0-21swapper/319:06:183
132722205171,23sleep20-21swapper/219:07:402
131142203169,23sleep00-21swapper/019:05:370
13747996229,4cyclictest41-21ksoftirqd/321:50:253
13747996128,7cyclictest41-21ksoftirqd/300:05:213
13747996126,7cyclictest41-21ksoftirqd/322:15:283
13747996126,4cyclictest41-21ksoftirqd/321:20:263
13747996027,7cyclictest41-21ksoftirqd/321:25:203
13747996027,7cyclictest41-21ksoftirqd/300:35:293
13747996027,6cyclictest41-21ksoftirqd/320:10:223
13747996020,7cyclictest41-21ksoftirqd/319:10:283
13747995929,10cyclictest41-21ksoftirqd/300:10:133
13747995927,4cyclictest41-21ksoftirqd/321:15:123
13745995926,5cyclictest25-21ksoftirqd/100:05:011
179512580,6sleep31374799cyclictest20:25:193
13747995828,9cyclictest41-21ksoftirqd/323:35:263
13747995828,4cyclictest41-21ksoftirqd/320:55:003
13747995826,4cyclictest41-21ksoftirqd/319:55:003
13747995826,11cyclictest41-21ksoftirqd/321:35:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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