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2026-01-08 - 12:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jan 08, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230164,22phc2sys0-21swapper/319:06:023
184442203171,21sleep20-21swapper/219:09:322
182792202168,23sleep10-21swapper/119:07:211
182782201168,22sleep00-21swapper/019:07:210
2554421330,4sleep31877899cyclictest22:45:153
265962630,4sleep1231rcuc/123:55:001
265962630,4sleep1231rcuc/123:55:001
18778996033,3cyclictest41-21ksoftirqd/300:40:013
18778995520,8cyclictest41-21ksoftirqd/322:05:013
18778995519,8cyclictest41-21ksoftirqd/322:10:003
139391550,1ptp4l401ktimersoftd/322:21:303
18778995324,6cyclictest41-21ksoftirqd/322:20:013
18778995322,3cyclictest41-21ksoftirqd/321:15:003
18778995122,4cyclictest41-21ksoftirqd/323:45:003
18778995119,7cyclictest41-21ksoftirqd/320:55:003
18778995021,4cyclictest41-21ksoftirqd/322:25:263
18778995019,8cyclictest41-21ksoftirqd/300:20:003
18778995018,6cyclictest41-21ksoftirqd/319:45:243
1877899497,9cyclictest41-21ksoftirqd/320:40:253
18778994922,7cyclictest41-21ksoftirqd/321:30:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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