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2026-02-19 - 16:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Feb 19, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264452203170,22sleep10-21swapper/107:08:161
139491203169,23phc2sys0-21swapper/307:05:283
264442202169,22sleep00-21swapper/007:08:150
265822201168,23sleep20-21swapper/207:09:582
1393911350,1ptp4l19096-21ps10:15:193
2659028363,11sleep10-21swapper/107:10:011
50312690,4sleep10-21swapper/110:50:481
139391650,1ptp4l401ktimersoftd/308:13:593
229972600,5sleep122993-21latency_hist10:25:001
26882995930,3cyclictest25-21ksoftirqd/108:35:231
139391590,1ptp4l401ktimersoftd/310:30:223
139391580,1ptp4l401ktimersoftd/309:53:243
7232560,2sleep1730-21fschecks_time08:30:151
26882995626,4cyclictest25-21ksoftirqd/107:45:151
314142550,2sleep00-21swapper/009:35:010
26882995529,4cyclictest25-21ksoftirqd/111:40:001
26882995420,4cyclictest25-21ksoftirqd/112:15:231
26882995419,3cyclictest25-21ksoftirqd/111:05:241
26882995417,4cyclictest25-21ksoftirqd/110:10:201
26882995327,8cyclictest25-21ksoftirqd/111:25:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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