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2026-03-20 - 17:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Mar 20, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491222180,34phc2sys0-21swapper/307:05:063
311492197164,22sleep10-21swapper/107:08:111
311632196163,22sleep20-21swapper/207:08:122
310682194161,22sleep00-21swapper/007:07:220
1430121580,6sleep23164199cyclictest07:23:082
2126721540,6sleep33164299cyclictest07:50:123
265652780,5sleep326475-21multi.sh07:24:123
17052720,5sleep21718-21od07:25:102
17052720,5sleep21718-21od07:25:102
93132680,3sleep09254-21sh07:25:200
93132680,3sleep09254-21sh07:25:200
3163999660,1cyclictest0-21swapper/011:05:130
77772650,6sleep23164199cyclictest07:19:592
162032630,4sleep116120-21sh07:25:301
162032630,4sleep116120-21sh07:25:291
174672620,11sleep017440-21multi.sh07:23:570
12082620,4sleep11204-21sort07:21:221
139391600,0ptp4l401ktimersoftd/311:25:173
3164199593,11cyclictest19782-21ptp4l-jitter10:00:242
304782590,5sleep230481-21needreboot09:15:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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