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2026-05-30 - 09:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat May 30, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174542235169,22sleep00-21swapper/019:07:570
139491235169,22phc2sys0-21swapper/319:08:093
174602206172,23sleep10-21swapper/119:08:021
175282203172,20sleep20-21swapper/219:08:562
1682921670,8sleep11790499cyclictest20:15:131
139391710,0ptp4l391rcuc/322:25:233
17906996429,8cyclictest41-21ksoftirqd/300:35:143
17906995426,7cyclictest41-21ksoftirqd/300:10:293
17906995327,9cyclictest41-21ksoftirqd/321:00:183
17906995325,8cyclictest41-21ksoftirqd/323:30:183
17906995325,8cyclictest41-21ksoftirqd/323:30:183
1790699522,8cyclictest41-21ksoftirqd/322:57:323
17906995219,8cyclictest41-21ksoftirqd/322:10:003
17906995125,9cyclictest41-21ksoftirqd/323:20:223
17906995125,8cyclictest41-21ksoftirqd/321:55:123
1790699493,5cyclictest0-21swapper/321:30:253
17906994927,8cyclictest41-21ksoftirqd/323:25:133
17906994923,9cyclictest41-21ksoftirqd/320:15:183
17906994923,9cyclictest41-21ksoftirqd/319:40:183
1790699482,6cyclictest41-21ksoftirqd/323:55:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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