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2026-01-27 - 07:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 27, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51712209176,22sleep00-21swapper/019:05:430
139491207173,22phc2sys0-21swapper/319:06:393
53612204171,22sleep20-21swapper/219:08:062
53552203171,21sleep10-21swapper/119:08:021
2357821280,2sleep2580199cyclictest22:00:202
1393911060,0ptp4l391rcuc/319:50:203
5802996824,7cyclictest41-21ksoftirqd/320:32:033
5802996432,4cyclictest41-21ksoftirqd/319:55:273
5802996429,9cyclictest41-21ksoftirqd/323:30:003
5802996332,4cyclictest41-21ksoftirqd/321:00:193
5802996329,9cyclictest41-21ksoftirqd/322:25:233
5800996320,5cyclictest25-21ksoftirqd/123:00:231
88122620,2sleep38813-21fschecks_time23:45:153
5802996228,5cyclictest41-21ksoftirqd/322:05:263
5802996227,8cyclictest41-21ksoftirqd/323:35:223
5802996131,11cyclictest41-21ksoftirqd/323:10:183
5802996129,8cyclictest41-21ksoftirqd/300:15:013
5802996129,4cyclictest41-21ksoftirqd/322:25:013
5802996128,10cyclictest41-21ksoftirqd/319:25:133
5802996126,8cyclictest41-21ksoftirqd/320:50:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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