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2026-05-27 - 15:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed May 27, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159472217156,50sleep00-21swapper/007:07:030
139491206173,22phc2sys0-21swapper/307:08:163
160112204169,23sleep20-21swapper/207:07:532
160462203170,22sleep10-21swapper/107:08:211
1688921770,4sleep21647799cyclictest07:10:132
1481521770,7sleep11647699cyclictest08:10:261
3008521340,6sleep01647599cyclictest12:05:210
2407721300,6sleep21647799cyclictest11:55:122
16478997032,11cyclictest41-21ksoftirqd/310:19:593
16478996427,4cyclictest41-21ksoftirqd/312:05:183
16478996331,4cyclictest41-21ksoftirqd/309:40:003
16478996327,4cyclictest41-21ksoftirqd/311:30:003
16478996326,4cyclictest41-21ksoftirqd/311:05:103
16478996232,4cyclictest41-21ksoftirqd/307:35:013
16478996229,4cyclictest41-21ksoftirqd/308:45:263
16478996228,4cyclictest41-21ksoftirqd/308:05:233
16478996131,10cyclictest41-21ksoftirqd/311:00:003
16478996130,3cyclictest41-21ksoftirqd/312:20:003
16478996129,4cyclictest41-21ksoftirqd/308:10:223
16478996032,3cyclictest41-21ksoftirqd/307:15:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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