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2026-04-15 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Apr 15, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6862209176,22sleep20-21swapper/207:05:592
139491206171,23phc2sys0-21swapper/307:08:583
6842201168,22sleep00-21swapper/007:05:570
6802200166,22sleep10-21swapper/107:05:541
1821321590,4sleep1130799cyclictest10:00:001
1394918864,16phc2sys0-21swapper/307:10:003
39952590,2sleep20-21swapper/208:20:242
139391590,1ptp4l401ktimersoftd/308:45:233
1310995810,10cyclictest41-21ksoftirqd/310:30:003
134491570,7getstats131099cyclictest11:33:163
1310995621,2cyclictest41-21ksoftirqd/308:00:263
90552520,2sleep20-21swapper/208:30:272
1310995014,10cyclictest41-21ksoftirqd/309:50:013
131099489,9cyclictest41-21ksoftirqd/311:55:143
131099488,10cyclictest41-21ksoftirqd/312:35:133
1310994813,4cyclictest41-21ksoftirqd/308:00:013
1305994528,5cyclictest9-21ksoftirqd/009:25:200
139391430,0ptp4l401ktimersoftd/312:28:373
131099439,10cyclictest41-21ksoftirqd/308:35:003
1310994332,9cyclictest41-21ksoftirqd/312:30:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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