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2026-06-22 - 17:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jun 22, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147052234169,22sleep10-21swapper/107:06:191
139491231169,50phc2sys0-21swapper/307:06:043
146962205172,22sleep20-21swapper/207:06:122
149492203170,22sleep00-21swapper/007:09:270
36092530,3sleep20-21swapper/210:05:222
1499725236,8sleep10-21swapper/107:10:001
139391460,39ptp4l0-21swapper/307:10:013
226102420,1sleep30-21swapper/307:25:143
139391420,0ptp4l401ktimersoftd/309:53:103
139391420,0ptp4l401ktimersoftd/308:36:363
139391410,0ptp4l401ktimersoftd/312:00:273
15288994035,3cyclictest2079-21cron10:05:000
139391400,0ptp4l401ktimersoftd/312:25:253
15291993833,3cyclictest41-21ksoftirqd/307:50:013
15291993731,4cyclictest41-21ksoftirqd/309:45:343
15290993731,4cyclictest33-21ksoftirqd/211:00:242
15290993731,4cyclictest33-21ksoftirqd/209:30:322
15289993731,3cyclictest551-21rs:main1
249282360,2chrt0-21swapper/109:45:121
15290993631,3cyclictest33-21ksoftirqd/211:13:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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