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2026-07-05 - 20:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jul 05, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1508022460,15sleep00-21swapper/007:05:170
139491207173,23phc2sys0-21swapper/307:09:543
164362203171,22sleep10-21swapper/107:07:161
163552203169,22sleep20-21swapper/207:06:122
2405121450,3sleep00-21swapper/010:45:220
869221320,3sleep31710499cyclictest11:20:233
29912700,7sleep01710199cyclictest08:55:140
17104996011,9cyclictest11364-21cat11:25:243
1710499587,7cyclictest19067-21perl08:20:153
1710499575,16cyclictest0-21swapper/307:15:233
139391560,1ptp4l391rcuc/307:20:213
1710499548,9cyclictest2518-21gnome-shell11:03:593
1710499538,14cyclictest13804-21ps11:30:223
1710499538,10cyclictest29386-21rt-features08:40:243
1710499537,9cyclictest2518-21gnome-shell08:02:593
1710499528,15cyclictest19902-21timerwakeupswit10:35:273
1710499519,14cyclictest5173-21latency_hist09:00:003
1710499515,17cyclictest0-21swapper/307:35:213
1710499508,15cyclictest1229-21irqstats11:05:203
1710499508,15cyclictest1229-21irqstats11:05:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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