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2026-08-21 - 08:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Aug 21, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76222232168,21sleep10-21swapper/119:06:071
77202227164,51sleep30-21swapper/319:07:183
77912205171,23sleep20-21swapper/219:08:132
79092204171,22sleep00-21swapper/019:09:440
299121410,7sleep0822199cyclictest21:10:260
139391600,1ptp4l401ktimersoftd/323:00:183
310052580,1sleep00-21swapper/000:25:140
70462560,2sleep2311rcuc/223:35:182
139391540,1ptp4l391rcuc/321:55:493
139391540,1ptp4l391rcuc/320:46:173
307002530,3sleep20-21swapper/223:15:242
217062530,1sleep10-21swapper/120:45:111
139391520,1ptp4l391rcuc/320:37:513
41832500,2sleep20-21swapper/222:20:252
8224994641,3cyclictest30158-21latency_hist22:10:003
139391460,0ptp4l401ktimersoftd/322:10:133
139391460,0ptp4l401ktimersoftd/300:08:443
1394914533,5phc2sys0-21swapper/319:10:013
822399444,38cyclictest25386-21kworker/2:121:55:122
139391440,0ptp4l401ktimersoftd/321:40:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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