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2025-11-09 - 11:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Nov 09, 2025 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341521410,3sleep03421-21cpuspeed_turbos19:10:140
13719113083,39phc2sys0-21swapper/319:09:353
711212064,13sleep00-21swapper/019:05:130
2678210582,13sleep10-21swapper/119:06:511
282829674,12sleep20-21swapper/219:08:402
136991760,1ptp4l401ktimersoftd/319:53:003
136991700,1ptp4l401ktimersoftd/320:16:293
3228996424,5cyclictest33-21ksoftirqd/223:30:272
136991640,1ptp4l401ktimersoftd/319:33:413
125022630,7sleep1322799cyclictest21:43:261
322899624,56cyclictest26460-21kworker/2:019:32:072
322899617,52cyclictest23932-21kworker/2:221:37:272
3228996126,4cyclictest33-21ksoftirqd/219:45:002
3228996125,8cyclictest33-21ksoftirqd/200:00:232
3228996123,4cyclictest33-21ksoftirqd/220:30:262
3228996121,11cyclictest33-21ksoftirqd/219:35:222
3228996118,9cyclictest33-21ksoftirqd/222:05:142
136991610,2ptp4l401ktimersoftd/322:20:153
136991610,1ptp4l401ktimersoftd/300:39:033
136991610,1ptp4l401ktimersoftd/300:39:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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