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2026-07-20 - 14:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 20, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491240173,22phc2sys0-21swapper/319:08:103
295262230170,50sleep20-21swapper/219:07:022
294722205172,22sleep10-21swapper/119:06:191
296272202168,22sleep00-21swapper/019:07:470
139491163124,13phc2sys0-21swapper/319:10:003
1803121550,4sleep13008999cyclictest00:20:191
857621410,7sleep13008999cyclictest19:30:231
2853521340,7sleep03008899cyclictest23:35:160
30090997336,5cyclictest33-21ksoftirqd/222:45:002
139391710,1ptp4l391rcuc/321:45:183
3008999676,59cyclictest0-21swapper/123:25:531
3008999655,57cyclictest0-21swapper/122:05:531
30090996030,4cyclictest33-21ksoftirqd/220:25:182
271902590,5sleep227194-21irqrtprio20:10:192
44752580,3sleep20-21swapper/222:45:162
14292560,3sleep20-21swapper/223:45:212
139391560,1ptp4l401ktimersoftd/321:50:013
139391550,1ptp4l401ktimersoftd/323:31:193
30090995423,4cyclictest33-21ksoftirqd/219:15:012
30090995322,6cyclictest33-21ksoftirqd/221:45:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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