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2026-02-17 - 23:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 17, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491234166,23phc2sys0-21swapper/307:05:323
314122207172,24sleep20-21swapper/207:05:062
8882201169,21sleep10-21swapper/107:06:571
10612200166,23sleep00-21swapper/007:09:050
1717521480,7sleep3144199cyclictest07:40:253
2446121330,2sleep3144199cyclictest09:05:133
113128363,11sleep20-21swapper/207:10:012
1439996822,9cyclictest25-21ksoftirqd/110:55:231
1439996630,4cyclictest25-21ksoftirqd/107:20:191
1439996327,8cyclictest25-21ksoftirqd/107:35:221
165242620,6sleep216519-21ps07:40:202
1439996227,5cyclictest25-21ksoftirqd/107:10:171
1439996125,7cyclictest25-21ksoftirqd/108:25:261
139391610,1ptp4l401ktimersoftd/309:45:143
1439996029,7cyclictest25-21ksoftirqd/111:05:151
1439995928,4cyclictest25-21ksoftirqd/109:40:171
1439995927,10cyclictest25-21ksoftirqd/111:45:221
1439995926,7cyclictest25-21ksoftirqd/111:35:001
1439995926,7cyclictest25-21ksoftirqd/108:55:171
1439995922,7cyclictest25-21ksoftirqd/108:30:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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