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2026-02-22 - 16:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Feb 22, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206171,23phc2sys0-21swapper/307:09:163
139491206171,23phc2sys0-21swapper/307:09:163
326122202169,22sleep20-21swapper/207:09:432
326122202169,22sleep20-21swapper/207:09:432
324112202169,23sleep00-21swapper/007:07:120
324112202169,23sleep00-21swapper/007:07:120
325162201170,20sleep10-21swapper/107:08:341
325162201170,20sleep10-21swapper/107:08:341
472996029,4cyclictest41-21ksoftirqd/312:00:173
472995927,4cyclictest41-21ksoftirqd/311:15:213
472995720,8cyclictest41-21ksoftirqd/307:20:013
472995524,4cyclictest41-21ksoftirqd/310:45:163
472995522,8cyclictest41-21ksoftirqd/309:15:253
472995425,4cyclictest41-21ksoftirqd/309:05:133
472995424,7cyclictest41-21ksoftirqd/309:45:143
472995324,3cyclictest41-21ksoftirqd/311:10:173
472995322,8cyclictest41-21ksoftirqd/309:10:183
472995320,4cyclictest41-21ksoftirqd/308:25:003
99532520,3sleep2311rcuc/210:50:252
472995127,7cyclictest41-21ksoftirqd/310:25:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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