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2026-06-06 - 14:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jun 06, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65242204171,22sleep30-21swapper/319:09:383
62592201168,22sleep20-21swapper/219:06:112
62322201168,22sleep10-21swapper/119:05:501
62312201168,22sleep00-21swapper/019:05:480
1394919576,10phc2sys0-21swapper/319:10:013
1394919576,10phc2sys0-21swapper/319:10:013
124492660,1sleep10-21swapper/119:20:181
184192610,5sleep018424-21unixbench_multi00:00:250
6848995913,24cyclictest25896-21/usr/sbin/munin19:50:163
320212570,2sleep20-21swapper/221:10:102
306672560,3sleep030668-21latency_hist20:00:000
6845995246,3cyclictest14922-21cron22:50:000
6845994942,4cyclictest10114-21cron22:40:010
6845994942,4cyclictest10114-21cron22:40:010
141742460,2sleep30-21swapper/319:25:133
6846994538,4cyclictest14119-21cron23:54:591
684799430,41cyclictest0-21swapper/223:45:232
139391420,0ptp4l401ktimersoftd/323:21:553
139391420,0ptp4l401ktimersoftd/322:04:493
139391420,0ptp4l401ktimersoftd/320:03:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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