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2026-08-07 - 12:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Aug 07, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185812208175,22sleep20-21swapper/219:09:042
185812208175,22sleep20-21swapper/219:09:042
183462206172,22sleep30-21swapper/319:06:073
183462206172,22sleep30-21swapper/319:06:073
185942204170,23sleep00-21swapper/019:09:140
185942204170,23sleep00-21swapper/019:09:140
185232204171,22sleep10-21swapper/119:08:181
185232204171,22sleep10-21swapper/119:08:181
1903021690,6sleep21894799cyclictest20:15:222
1812621410,7sleep01894599cyclictest23:35:260
139391660,1ptp4l25875-21ls22:45:213
1894599630,20cyclictest32390-21df_abs20:45:150
1894599621,21cyclictest23656-21latency_hist19:20:010
1894599621,21cyclictest16205-21date21:20:000
1894599570,20cyclictest7298-21timerandwakeup00:20:270
1894599560,22cyclictest24180-21cat19:20:140
139391550,1ptp4l401ktimersoftd/321:49:423
156542530,3sleep00-21swapper/022:25:180
156542530,3sleep00-21swapper/022:25:180
1894599471,42cyclictest18496-21cron21:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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