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2026-08-19 - 15:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Aug 19, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2146222570,7sleep10-21swapper/107:05:131
2146222570,7sleep10-21swapper/107:05:121
139491227164,51phc2sys0-21swapper/307:07:333
139491227164,51phc2sys0-21swapper/307:07:333
233772205172,22sleep00-21swapper/007:09:470
233772205172,22sleep00-21swapper/007:09:470
231152204170,23sleep20-21swapper/207:06:282
231152204170,23sleep20-21swapper/207:06:282
522521370,7sleep32368999cyclictest12:05:273
4912630,6sleep22368899cyclictest08:35:172
4912630,6sleep22368899cyclictest08:35:172
139391600,1ptp4l401ktimersoftd/308:20:473
2368799472,41cyclictest11687-21awk09:00:001
139391440,0ptp4l401ktimersoftd/307:25:173
139391430,0ptp4l401ktimersoftd/311:30:123
139391430,0ptp4l401ktimersoftd/311:10:153
139391430,0ptp4l401ktimersoftd/310:06:293
139391430,0ptp4l401ktimersoftd/307:49:023
23689994230,9cyclictest41-21ksoftirqd/312:30:203
139391420,0ptp4l401ktimersoftd/309:21:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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