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2026-07-14 - 06:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jul 14, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
191892209164,33sleep30-21swapper/319:07:423
192342206172,23sleep10-21swapper/119:08:161
190812204171,22sleep00-21swapper/019:06:180
171832204171,22sleep20-21swapper/219:05:122
133692610,6sleep21965999cyclictest20:05:012
129572590,3sleep09-21ksoftirqd/021:10:170
1965999551,3cyclictest10952-21chrt22:14:502
1965999550,4cyclictest32317-21taskset22:59:152
1965999540,3cyclictest5076-21chrt20:55:022
1965999540,3cyclictest21592-21taskset23:43:522
318022530,2sleep10-21swapper/100:05:161
104502530,6sleep11965899cyclictest21:05:171
1965999520,4cyclictest237202chrt23:45:532
1965999500,4cyclictest15766-21taskset00:36:232
1965999490,3cyclictest20252-21chrt20:18:332
1965999490,3cyclictest14269-21taskset21:14:042
1965999490,3cyclictest1163-21chrt00:08:022
1965799497,5cyclictest9-21ksoftirqd/020:20:120
1965999480,3cyclictest3494-21chrt21:58:172
1965999480,3cyclictest3494-21chrt21:58:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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