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2026-06-29 - 15:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jun 29, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110042236173,51sleep30-21swapper/307:08:323
110042236173,51sleep30-21swapper/307:08:313
109812232167,22sleep00-21swapper/007:08:110
109812232167,22sleep00-21swapper/007:08:110
108582207173,22sleep20-21swapper/207:06:372
108582207173,22sleep20-21swapper/207:06:372
110022204172,21sleep10-21swapper/107:08:291
110022204172,21sleep10-21swapper/107:08:291
823821740,4sleep21142299cyclictest10:25:182
11421995928,4cyclictest25-21ksoftirqd/107:20:001
11421995727,3cyclictest25-21ksoftirqd/112:10:131
86172560,2sleep00-21swapper/011:35:000
11421995626,4cyclictest25-21ksoftirqd/110:25:141
11421995625,8cyclictest25-21ksoftirqd/110:45:281
11421995524,7cyclictest25-21ksoftirqd/112:20:011
139391540,1ptp4l401ktimersoftd/308:55:273
11421995426,7cyclictest25-21ksoftirqd/111:45:001
11421995425,8cyclictest25-21ksoftirqd/110:30:141
11421995417,5cyclictest25-21ksoftirqd/110:25:011
176082530,3sleep30-21swapper/310:45:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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