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2026-05-18 - 23:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon May 18, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205172,22phc2sys0-21swapper/307:06:413
279912201168,22sleep10-21swapper/107:07:201
279902201168,22sleep00-21swapper/007:07:190
279972200168,21sleep20-21swapper/207:07:252
2127521450,4sleep32850199cyclictest12:30:183
129682550,1sleep10-21swapper/108:50:211
28499995319,4cyclictest25-21ksoftirqd/107:40:211
28412530,2sleep00-21swapper/007:20:260
28499995219,8cyclictest25-21ksoftirqd/108:30:161
28499995219,7cyclictest25-21ksoftirqd/108:40:251
28499995219,4cyclictest25-21ksoftirqd/109:15:141
28499995218,4cyclictest25-21ksoftirqd/107:20:251
28499995218,3cyclictest25-21ksoftirqd/107:45:261
28499995213,7cyclictest25-21ksoftirqd/110:55:191
28499995213,7cyclictest25-21ksoftirqd/110:55:191
102972520,3sleep30-21swapper/311:00:173
28499995119,3cyclictest25-21ksoftirqd/109:00:261
28499995117,8cyclictest25-21ksoftirqd/107:30:191
28499995117,4cyclictest25-21ksoftirqd/108:25:001
28499995117,4cyclictest25-21ksoftirqd/108:24:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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