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2026-09-24 - 23:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Sep 24, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322242230163,23sleep20-21swapper/207:08:232
321932228199,19sleep30-21swapper/307:07:583
322002203171,22sleep00-21swapper/007:08:030
320792199165,22sleep10-21swapper/107:06:281
1856421210,1sleep20-21swapper/212:15:232
174142540,4sleep017418-21unixbench_multi11:05:280
214562520,2sleep10-21swapper/109:00:211
214562520,2sleep10-21swapper/109:00:211
32650994415,27cyclictest0-21swapper/209:15:232
3265099430,42cyclictest0-21swapper/208:05:232
3265099430,1cyclictest0-21swapper/210:50:222
139391430,0ptp4l401ktimersoftd/309:20:153
32650994236,3cyclictest29963-21ls11:35:002
139391420,0ptp4l401ktimersoftd/311:10:183
139391420,0ptp4l401ktimersoftd/311:05:173
139391410,0ptp4l401ktimersoftd/308:50:253
139391400,32ptp4l0-21swapper/307:10:003
139391400,32ptp4l0-21swapper/307:10:003
32651993922,15cyclictest41-21ksoftirqd/309:05:133
32649993934,3cyclictest25-21ksoftirqd/112:19:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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