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2026-03-05 - 19:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 05, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491226160,22phc2sys0-21swapper/307:05:333
109572205171,22sleep10-21swapper/107:06:461
108712205172,22sleep20-21swapper/207:05:392
109562203170,22sleep00-21swapper/007:06:450
1121828263,10sleep20-21swapper/207:10:012
1121828263,10sleep20-21swapper/207:10:012
139391670,1ptp4l12411-21apt-get10:35:103
11509996330,7cyclictest9-21ksoftirqd/007:30:120
11509996328,6cyclictest9-21ksoftirqd/011:20:130
11509996328,10cyclictest9-21ksoftirqd/009:00:000
11509996227,6cyclictest9-21ksoftirqd/010:30:010
11509996127,4cyclictest9-21ksoftirqd/011:15:120
11509996126,7cyclictest9-21ksoftirqd/009:15:150
11509996126,6cyclictest9-21ksoftirqd/011:10:260
11509996046,3cyclictest9-21ksoftirqd/007:59:590
11509996030,6cyclictest9-21ksoftirqd/008:30:010
11509996029,4cyclictest9-21ksoftirqd/007:15:010
11509996029,4cyclictest9-21ksoftirqd/007:15:010
11509996028,6cyclictest9-21ksoftirqd/011:40:140
11509996028,6cyclictest9-21ksoftirqd/010:05:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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