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2026-01-29 - 22:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jan 29, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
202062202169,22sleep30-21swapper/307:05:593
204582200167,22sleep00-21swapper/007:09:140
203672198165,22sleep20-21swapper/207:08:032
203662196164,22sleep10-21swapper/107:08:021
263721320,5sleep32082199cyclictest08:45:203
20820997030,6cyclictest33-21ksoftirqd/207:55:002
20820996935,8cyclictest33-21ksoftirqd/211:20:002
20820996932,6cyclictest33-21ksoftirqd/211:05:002
20820996732,5cyclictest33-21ksoftirqd/211:50:002
20820996731,6cyclictest33-21ksoftirqd/208:35:002
20820996631,6cyclictest33-21ksoftirqd/212:40:002
139391660,1ptp4l401ktimersoftd/308:08:573
20820996531,6cyclictest33-21ksoftirqd/208:25:002
20820996530,5cyclictest33-21ksoftirqd/208:40:002
20820996530,5cyclictest33-21ksoftirqd/207:45:172
15572650,2sleep20-21swapper/207:35:232
20820996430,8cyclictest33-21ksoftirqd/209:10:172
20820996430,6cyclictest33-21ksoftirqd/209:35:012
139391640,1ptp4l401ktimersoftd/311:21:333
20820996331,5cyclictest33-21ksoftirqd/210:25:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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