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2026-09-12 - 14:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Sep 12, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491211164,36phc2sys0-21swapper/319:08:243
78122205172,22sleep10-21swapper/119:07:241
78182204171,22sleep00-21swapper/019:07:270
77012204171,22sleep20-21swapper/219:05:562
139491163124,13phc2sys0-21swapper/319:10:013
2543921590,6sleep3831099cyclictest20:50:193
1952621440,6sleep0830799cyclictest21:45:240
150112590,4sleep2830999cyclictest21:35:272
132262590,1sleep20-21swapper/220:25:192
139391540,1ptp4l401ktimersoftd/300:07:323
139391440,1ptp4l401ktimersoftd/321:33:563
139391440,0ptp4l401ktimersoftd/323:05:223
139391400,0ptp4l401ktimersoftd/321:20:183
139391400,0ptp4l401ktimersoftd/321:18:243
8309993831,5cyclictest33-21ksoftirqd/219:19:352
8308993832,4cyclictest25-21ksoftirqd/123:30:511
8308993832,4cyclictest25-21ksoftirqd/121:44:001
57898380,8rtkit-daemon0-21swapper/021:37:040
8309993732,3cyclictest33-21ksoftirqd/223:50:002
8309993732,3cyclictest33-21ksoftirqd/223:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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