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2025-11-27 - 05:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Nov 27, 2025 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191205171,22phc2sys0-21swapper/319:08:143
137191205171,22phc2sys0-21swapper/319:08:133
325892203169,23sleep20-21swapper/219:08:142
325892203169,23sleep20-21swapper/219:08:142
305882201168,22sleep00-21swapper/019:05:030
305882201168,22sleep00-21swapper/019:05:030
324352198165,22sleep10-21swapper/119:06:151
324352198165,22sleep10-21swapper/119:06:151
584996311,11cyclictest6190-21awk23:55:222
584996211,12cyclictest29626-21vmstat23:35:262
58499618,12cyclictest19862-21threads23:15:242
58499618,11cyclictest28513-21awk20:05:232
583995928,4cyclictest25-21ksoftirqd/120:50:251
583995927,7cyclictest25-21ksoftirqd/122:30:171
584995811,12cyclictest4235-21awk19:15:202
583995823,4cyclictest25-21ksoftirqd/119:35:171
583995727,8cyclictest25-21ksoftirqd/119:34:591
583995725,8cyclictest25-21ksoftirqd/123:25:011
583995723,8cyclictest25-21ksoftirqd/119:40:191
583995723,8cyclictest25-21ksoftirqd/100:10:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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