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2026-02-23 - 16:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 23, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207172,24phc2sys0-21swapper/307:08:333
271912204171,22sleep00-21swapper/007:08:160
272602201168,22sleep20-21swapper/207:09:102
270182201168,21sleep10-21swapper/107:06:011
2733428864,16sleep00-21swapper/007:10:010
27628996626,9cyclictest41-21ksoftirqd/312:40:013
27628996626,9cyclictest41-21ksoftirqd/312:40:003
27628996529,4cyclictest41-21ksoftirqd/308:55:003
27628996526,10cyclictest41-21ksoftirqd/308:55:273
27628996429,7cyclictest41-21ksoftirqd/307:50:013
27628996428,4cyclictest41-21ksoftirqd/309:35:003
27628996332,4cyclictest41-21ksoftirqd/312:15:173
27628996329,4cyclictest41-21ksoftirqd/309:50:013
27628996326,4cyclictest41-21ksoftirqd/309:25:193
27628996324,4cyclictest41-21ksoftirqd/307:25:253
27628996229,4cyclictest41-21ksoftirqd/309:15:193
44872610,1sleep00-21swapper/011:55:250
27628996128,6cyclictest41-21ksoftirqd/312:25:003
27628996127,4cyclictest41-21ksoftirqd/307:55:003
27628996122,4cyclictest41-21ksoftirqd/311:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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