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2026-08-02 - 22:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Aug 02, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305152213179,23sleep20-21swapper/207:07:162
307222207174,22sleep00-21swapper/007:09:520
305142206173,22sleep10-21swapper/107:07:161
139491206172,23phc2sys0-21swapper/307:05:103
3073428262,11sleep10-21swapper/107:10:021
3102799810,79cyclictest0-21swapper/109:26:131
31027997118,51cyclictest0-21swapper/109:46:331
3102799680,66cyclictest0-21swapper/111:21:331
139391640,1ptp4l401ktimersoftd/309:59:343
94362610,2sleep00-21swapper/009:45:240
3102799596,51cyclictest0-21swapper/109:31:341
321682560,4sleep332170-21needreboot07:10:233
56132550,2sleep2311rcuc/209:40:012
31028995522,4cyclictest33-21ksoftirqd/209:20:262
139391550,1ptp4l401ktimersoftd/311:30:193
31028995424,4cyclictest33-21ksoftirqd/210:25:162
3102799540,52cyclictest0-21swapper/109:50:531
31028995223,4cyclictest33-21ksoftirqd/208:25:152
31028995220,4cyclictest33-21ksoftirqd/210:55:262
31028995220,4cyclictest33-21ksoftirqd/209:55:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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