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2025-05-03 - 01:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri May 02, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191227200,18phc2sys0-21swapper/307:09:133
63982205171,23sleep10-21swapper/107:06:421
65492203170,22sleep20-21swapper/207:08:412
64602203170,22sleep00-21swapper/007:07:310
1351421480,3sleep2694699cyclictest07:20:272
201002730,2sleep30-21swapper/309:50:243
136991580,1ptp4l391rcuc/312:28:163
118182570,3sleep10-21swapper/108:25:291
6945994842,3cyclictest11510-21awk07:20:001
6946994425,17cyclictest33-21ksoftirqd/212:29:592
136991430,0ptp4l401ktimersoftd/309:58:163
6944994238,3cyclictest27159-21apt09:00:000
136991420,0ptp4l401ktimersoftd/308:40:243
136991410,0ptp4l401ktimersoftd/309:40:023
136991410,0ptp4l401ktimersoftd/309:05:243
6946994034,4cyclictest33-21ksoftirqd/211:40:002
59298400,2rtkit-daemon0-21swapper/008:07:050
6946993934,3cyclictest33-21ksoftirqd/209:25:002
694599392,34cyclictest11653-21cron09:35:001
136991390,0ptp4l401ktimersoftd/311:30:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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