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2026-06-02 - 15:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 02, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207174,22phc2sys0-21swapper/319:06:023
20362205170,23sleep20-21swapper/219:09:422
18482203170,22sleep10-21swapper/119:07:231
17592203168,23sleep00-21swapper/019:06:180
302021710,6sleep2235499cyclictest21:25:002
1276921710,5sleep2235499cyclictest00:00:132
139491167129,13phc2sys0-21swapper/319:10:003
1932621410,6sleep1235399cyclictest20:50:171
104852740,5sleep2235499cyclictest20:30:242
235499619,3cyclictest30539-21apt23:30:102
139391600,1ptp4l401ktimersoftd/322:55:403
140092590,3sleep20-21swapper/221:45:222
320992570,1sleep332102-21grep22:25:143
139391550,1ptp4l401ktimersoftd/321:18:533
139391550,1ptp4l401ktimersoftd/300:34:253
207252530,2sleep220729-21irqrtprio22:00:192
221482510,3sleep30-21swapper/323:10:243
139391490,1ptp4l401ktimersoftd/321:37:233
139391490,1ptp4l401ktimersoftd/321:37:223
2354994514,29cyclictest28302-21kworker/2:121:10:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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