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2026-02-09 - 09:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 09, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491202169,22phc2sys0-21swapper/319:09:533
257292201169,22sleep10-21swapper/119:05:501
257282201168,22sleep00-21swapper/019:05:490
257252198164,23sleep20-21swapper/219:05:472
26349997029,6cyclictest9-21ksoftirqd/021:30:180
26349996629,7cyclictest9-21ksoftirqd/021:25:130
26349996324,7cyclictest9-21ksoftirqd/023:15:220
116422630,8sleep22635199cyclictest20:50:252
26349996227,8cyclictest9-21ksoftirqd/023:25:130
26349996227,8cyclictest9-21ksoftirqd/021:20:200
26349996221,11cyclictest9-21ksoftirqd/020:35:180
26349996221,11cyclictest9-21ksoftirqd/020:35:180
26349996216,8cyclictest9-21ksoftirqd/022:00:360
26349996126,4cyclictest9-21ksoftirqd/023:10:120
26349996123,9cyclictest9-21ksoftirqd/019:25:170
26349996122,4cyclictest9-21ksoftirqd/020:20:130
26349996120,5cyclictest9-21ksoftirqd/023:45:190
26349996026,7cyclictest9-21ksoftirqd/021:00:190
26349996023,11cyclictest9-21ksoftirqd/022:10:120
26349995955,2cyclictest111rcuc/020:15:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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