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2026-05-22 - 02:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu May 21, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157642207173,22sleep30-21swapper/307:08:143
156322204170,23sleep20-21swapper/207:06:322
158962203170,22sleep00-21swapper/007:09:510
156312203169,22sleep10-21swapper/107:06:321
139391570,1ptp4l401ktimersoftd/308:32:403
139391560,1ptp4l401ktimersoftd/309:50:283
89522550,5sleep08956-21kernelversion12:30:200
211072530,2sleep021109-21tr09:35:130
159592490,2sleep00-21swapper/010:30:210
213882480,1sleep00-21swapper/011:50:120
139391450,0ptp4l401ktimersoftd/312:05:163
16203994438,4cyclictest9792-21cron08:05:002
139391440,1ptp4l0-21swapper/310:07:473
139391440,0ptp4l401ktimersoftd/308:28:093
139391430,0ptp4l401ktimersoftd/311:41:023
139391420,0ptp4l401ktimersoftd/308:55:413
16203994134,4cyclictest9972-21cron10:20:002
16204994035,3cyclictest41-21ksoftirqd/312:35:013
16204994029,3cyclictest41-21ksoftirqd/311:35:003
139391400,0ptp4l401ktimersoftd/307:25:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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