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2026-09-03 - 02:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Sep 02, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208171,25phc2sys0-21swapper/307:08:533
308642206173,22sleep20-21swapper/207:06:142
310232205172,22sleep10-21swapper/107:08:171
309192202169,22sleep00-21swapper/007:06:560
1101421710,7sleep03159899cyclictest12:05:140
1394918564,11phc2sys0-21swapper/307:10:003
284122680,2sleep30-21swapper/308:10:163
31601996027,4cyclictest41-21ksoftirqd/308:10:003
31601995823,7cyclictest41-21ksoftirqd/310:10:123
31601995822,8cyclictest41-21ksoftirqd/310:55:243
31601995728,8cyclictest41-21ksoftirqd/310:15:143
31601995728,8cyclictest41-21ksoftirqd/309:20:003
31601995726,9cyclictest41-21ksoftirqd/308:55:153
31601995726,9cyclictest41-21ksoftirqd/308:55:153
31601995723,8cyclictest41-21ksoftirqd/310:50:003
31601995723,8cyclictest41-21ksoftirqd/308:45:013
31601995720,7cyclictest41-21ksoftirqd/311:05:223
31601995718,8cyclictest41-21ksoftirqd/311:39:033
152332570,4sleep23160099cyclictest11:05:182
31601995628,8cyclictest41-21ksoftirqd/311:15:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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