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2026-03-19 - 12:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 19, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
293632205172,22sleep20-21swapper/219:08:192
291592204170,23sleep00-21swapper/019:05:390
293062203169,23sleep30-21swapper/319:07:353
292152202168,23sleep10-21swapper/119:06:251
29795997110,59cyclictest0-21swapper/100:00:531
150412630,2sleep30-21swapper/320:50:283
2979499629,10cyclictest4114-21awk21:35:260
2979699591,17cyclictest13231-21grep20:49:592
2979699565,7cyclictest16518-21cut20:55:192
2979699546,6cyclictest11011-21sed23:00:152
2979599540,52cyclictest0-21swapper/121:30:331
29794995411,11cyclictest24287-21threads21:10:260
139391540,1ptp4l401ktimersoftd/321:36:203
2979699536,6cyclictest19188-21date00:25:002
139391530,1ptp4l401ktimersoftd/322:20:323
139391530,1ptp4l401ktimersoftd/320:57:173
2979699526,7cyclictest12023-21date00:10:012
2979699521,10cyclictest22532-21sed00:30:182
2979699516,11cyclictest16886-21fschecks_count19:50:162
2979699512,9cyclictest25086-21ps20:05:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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