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2026-07-05 - 00:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 04, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491211176,23phc2sys0-21swapper/307:05:503
148872205171,23sleep20-21swapper/207:08:062
145392202169,22sleep00-21swapper/007:06:550
144262202170,22sleep10-21swapper/107:05:301
1145821370,3sleep31533799cyclictest11:30:213
139391880,0ptp4l401ktimersoftd/310:35:173
15336997315,12cyclictest7181-21/usr/sbin/munin11:20:262
15336996912,12cyclictest16124-21irqrtprio11:40:192
15336996712,16cyclictest18173-21if_enp1s011:45:172
15336996615,9cyclictest22017-21sed07:20:252
15336996612,16cyclictest18243-21grep08:20:272
15336996612,10cyclictest7179-21df_abs10:15:152
15336996611,18cyclictest20306-21df_abs11:50:142
15336996515,11cyclictest9684-21ls11:25:272
15336996511,11cyclictest24217-21irqrtprio10:50:182
15336996511,11cyclictest24217-21irqrtprio10:50:182
139391650,1ptp4l401ktimersoftd/311:50:173
1533699648,15cyclictest0-21swapper/208:50:292
1533699648,15cyclictest0-21swapper/208:50:292
1533699648,15cyclictest0-21swapper/207:10:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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