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2026-09-01 - 18:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Sep 01, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231852235169,22sleep20-21swapper/207:06:542
139491208174,23phc2sys0-21swapper/307:07:333
230972207174,22sleep10-21swapper/107:05:451
232862203169,22sleep00-21swapper/007:08:130
234332152113,27sleep30-21swapper/307:10:023
23728996911,11cyclictest1768-21sh08:40:002
23728996313,9cyclictest13696-21cut12:25:182
139391630,0ptp4l401ktimersoftd/312:35:273
23728996213,10cyclictest14971-21sed10:15:002
2372899618,16cyclictest0-21swapper/208:05:122
23728996113,9cyclictest22443-21date08:15:012
23728996112,8cyclictest18245-21grep11:25:252
23728996110,10cyclictest7192-21/usr/sbin/munin11:05:242
2372899609,16cyclictest3819-21/usr/sbin/munin09:50:192
2372899607,18cyclictest0-21swapper/208:50:132
23728996010,11cyclictest4429-21latency_hist11:00:002
23728995911,17cyclictest10687-21grep12:20:102
23726995925,6cyclictest9-21ksoftirqd/008:20:130
2372899589,14cyclictest0-21swapper/211:10:172
2372899587,17cyclictest0-21swapper/211:50:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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