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2026-06-18 - 14:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jun 18, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174232206173,22sleep30-21swapper/319:07:333
174932205172,22sleep10-21swapper/119:08:281
173382205172,22sleep00-21swapper/019:06:260
173302203170,22sleep20-21swapper/219:06:202
2935421650,5sleep21790499cyclictest20:40:192
2935421650,5sleep21790499cyclictest20:40:192
46942630,3sleep10-21swapper/123:10:251
139391610,1ptp4l401ktimersoftd/300:00:223
100152560,4sleep341-21ksoftirqd/320:00:173
312392510,4sleep031238-21sed23:00:130
1790299513,44cyclictest23529-21turbostat22:45:020
221892500,2sleep00-21swapper/021:35:000
1790299487,10cyclictest9-21ksoftirqd/019:20:260
17902994816,6cyclictest9-21ksoftirqd/023:25:210
17902994816,4cyclictest9-21ksoftirqd/023:05:210
139391480,1ptp4l401ktimersoftd/300:32:343
1790299473,3cyclictest121rcu_preempt22:25:000
17902994717,7cyclictest9-21ksoftirqd/023:45:000
1790599463,15cyclictest121rcu_preempt20:35:203
17902994641,2cyclictest5500-21wc21:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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