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2025-11-23 - 15:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Nov 23, 2025 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137191210176,22phc2sys0-21swapper/307:08:333
248692205172,22sleep20-21swapper/207:05:402
251162203169,23sleep00-21swapper/007:08:480
251172202170,21sleep10-21swapper/107:08:491
61462670,2sleep30-21swapper/308:45:143
64752580,2sleep30-21swapper/312:05:193
136991570,49ptp4l0-21swapper/307:10:013
25510995622,5cyclictest9-21ksoftirqd/010:15:210
266102550,2sleep10-21swapper/107:10:201
25510995020,4cyclictest9-21ksoftirqd/011:20:130
25510994920,4cyclictest9-21ksoftirqd/007:45:250
25510994920,4cyclictest9-21ksoftirqd/007:45:250
25510994812,5cyclictest9-21ksoftirqd/011:45:260
25510994718,3cyclictest9-21ksoftirqd/009:45:280
25510994518,3cyclictest9-21ksoftirqd/011:10:150
25510994511,7cyclictest9-21ksoftirqd/007:25:150
25510994511,4cyclictest9-21ksoftirqd/010:35:270
2551099449,6cyclictest9-21ksoftirqd/010:45:250
25510994418,6cyclictest9-21ksoftirqd/011:10:010
25510994414,4cyclictest9-21ksoftirqd/008:35:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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