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2026-05-31 - 15:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun May 31, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288292214182,22sleep20-21swapper/207:08:262
286512208174,23sleep30-21swapper/307:06:053
268312207174,22sleep10-21swapper/107:05:111
286832202168,22sleep00-21swapper/007:06:300
2121121510,6sleep12925399cyclictest10:15:021
2104821220,2sleep10-21swapper/111:20:171
54572770,5sleep12925399cyclictest10:49:591
29254996510,19cyclictest23504-21latency_hist08:05:002
139391580,1ptp4l401ktimersoftd/307:45:253
139391560,1ptp4l401ktimersoftd/308:10:003
139391560,0ptp4l401ktimersoftd/309:21:543
29252995211,22cyclictest1317-21runrttasks10:42:330
139391520,1ptp4l391rcuc/307:24:383
2925299496,2cyclictest8811-21seq12:01:230
139391460,0ptp4l401ktimersoftd/312:30:243
29252994510,20cyclictest18631-21seq10:10:030
139391450,0ptp4l401ktimersoftd/311:45:153
139391450,0ptp4l401ktimersoftd/309:56:363
139391450,0ptp4l401ktimersoftd/309:56:353
139391440,0ptp4l401ktimersoftd/311:27:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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