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2026-02-10 - 12:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 10, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
220942229165,52sleep10-21swapper/119:07:161
221592205170,24sleep30-21swapper/319:08:063
222552203170,22sleep00-21swapper/019:09:210
222252200168,21sleep20-21swapper/219:08:592
2259899727,27cyclictest16179-21timerandwakeup00:30:271
2259899630,3cyclictest96532chrt00:20:011
22599995727,5cyclictest33-21ksoftirqd/220:00:172
22599995722,6cyclictest33-21ksoftirqd/223:20:182
2259899574,22cyclictest13614-21taskset22:13:151
22597995723,10cyclictest9-21ksoftirqd/000:25:240
22599995624,6cyclictest33-21ksoftirqd/222:55:152
22599995521,5cyclictest33-21ksoftirqd/221:50:162
22599995421,5cyclictest33-21ksoftirqd/221:14:522
22599995421,5cyclictest33-21ksoftirqd/220:20:172
22599995325,8cyclictest33-21ksoftirqd/220:35:252
22599995319,5cyclictest33-21ksoftirqd/221:25:152
22599995227,8cyclictest33-21ksoftirqd/223:39:592
22599995226,6cyclictest33-21ksoftirqd/221:30:112
22599995220,5cyclictest33-21ksoftirqd/200:35:272
2259899520,3cyclictest140982sleep120:00:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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