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2026-06-30 - 16:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 30, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206171,23phc2sys0-21swapper/307:06:093
217622204171,22sleep20-21swapper/207:05:512
217562204169,23sleep10-21swapper/107:05:471
220572203170,22sleep00-21swapper/007:09:350
831421710,4sleep32238699cyclictest07:45:243
899321430,5sleep32238699cyclictest12:15:223
22384996128,10cyclictest25-21ksoftirqd/109:15:211
281912580,4sleep228194-21latency07:20:202
22384995827,3cyclictest121rcu_preempt09:50:001
22383995625,3cyclictest9-21ksoftirqd/008:35:190
2238599551,15cyclictest30513-21latency_hist08:35:012
22384995522,10cyclictest25-21ksoftirqd/108:55:201
22384995434,2cyclictest25-21ksoftirqd/109:35:191
22384995417,5cyclictest25-21ksoftirqd/108:35:131
22384995415,8cyclictest25-21ksoftirqd/108:15:211
22383995324,3cyclictest9-21ksoftirqd/012:30:230
22384995215,10cyclictest25-21ksoftirqd/109:05:201
237992510,2sleep20-21swapper/209:25:242
22384995120,10cyclictest25-21ksoftirqd/110:15:281
22384995119,9cyclictest25-21ksoftirqd/111:20:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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