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2026-07-09 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 09, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491209175,23phc2sys0-21swapper/319:06:593
222342205172,22sleep20-21swapper/219:09:112
220532204170,23sleep10-21swapper/119:06:501
222892203170,22sleep00-21swapper/019:09:540
222972163125,13sleep20-21swapper/219:10:002
96622680,2sleep10-21swapper/123:10:191
22592996830,5cyclictest41-21ksoftirqd/322:00:243
22592996328,7cyclictest41-21ksoftirqd/321:35:013
22592996120,8cyclictest41-21ksoftirqd/321:50:213
22592996025,10cyclictest41-21ksoftirqd/319:10:133
22592996024,9cyclictest41-21ksoftirqd/319:45:003
22592995929,4cyclictest41-21ksoftirqd/320:00:213
22592995928,8cyclictest41-21ksoftirqd/320:40:123
22592995928,4cyclictest41-21ksoftirqd/321:10:213
22592995927,3cyclictest41-21ksoftirqd/322:25:003
22592995926,8cyclictest41-21ksoftirqd/323:45:183
22592995926,8cyclictest41-21ksoftirqd/319:20:193
22592995925,8cyclictest41-21ksoftirqd/323:54:593
22592995925,4cyclictest41-21ksoftirqd/323:25:003
22592995830,4cyclictest41-21ksoftirqd/320:55:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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