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2026-06-24 - 21:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jun 24, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207172,23phc2sys0-21swapper/307:06:253
63652205172,22sleep20-21swapper/207:07:442
64912203171,21sleep10-21swapper/107:09:241
62262201168,22sleep00-21swapper/007:06:000
139491138113,13phc2sys0-21swapper/307:10:023
14232580,2sleep10-21swapper/112:35:011
272642560,2sleep30-21swapper/312:20:143
139391560,1ptp4l401ktimersoftd/307:42:393
6835995520,8cyclictest41-21ksoftirqd/311:44:593
6835995319,8cyclictest41-21ksoftirqd/308:00:013
6833995246,4cyclictest10832-21cron08:25:001
6833995246,4cyclictest10832-21cron08:24:591
6835995119,9cyclictest41-21ksoftirqd/311:00:003
6835995117,8cyclictest41-21ksoftirqd/309:10:183
6835995116,4cyclictest41-21ksoftirqd/310:35:003
6835995115,9cyclictest41-21ksoftirqd/310:55:013
6835995020,8cyclictest41-21ksoftirqd/311:30:123
6835995019,3cyclictest41-21ksoftirqd/307:50:223
6835995019,3cyclictest41-21ksoftirqd/307:50:213
6835995018,8cyclictest41-21ksoftirqd/312:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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