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2026-03-17 - 15:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Mar 17, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2478922600,6sleep20-21swapper/207:05:122
139491231164,22phc2sys0-21swapper/307:08:533
267312204171,22sleep00-21swapper/007:08:250
266782203170,22sleep10-21swapper/107:07:501
863821570,5sleep02714699cyclictest09:55:000
15772780,1sleep10-21swapper/109:40:001
68312610,5sleep16835-21switchtime10:55:261
59672570,4sleep12714799cyclictest07:30:281
2714799550,4cyclictest13177-21seq10:00:581
237462550,4sleep10-21swapper/109:15:261
139391540,1ptp4l401ktimersoftd/308:20:233
27147994711,21cyclictest18137-21seq12:25:361
139391470,1ptp4l401ktimersoftd/307:27:093
135052460,2sleep213506-21irqrtprio08:55:212
139391430,1ptp4l0-21swapper/312:01:563
2714799420,4cyclictest30225-21taskset08:24:451
139391420,0ptp4l401ktimersoftd/309:59:503
139391420,0ptp4l401ktimersoftd/308:55:233
2714799410,4cyclictest5003-21taskset10:53:151
2714799410,3cyclictest31400-21seq07:16:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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