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2026-08-28 - 00:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 27, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34802207174,22sleep00-21swapper/007:08:020
139491207173,22phc2sys0-21swapper/307:06:013
33122203170,22sleep20-21swapper/207:05:502
34932201168,22sleep10-21swapper/107:08:111
1564421700,6sleep1407699cyclictest10:55:211
2558221390,3sleep0407599cyclictest11:15:260
1460021390,4sleep0407599cyclictest12:00:220
2566221270,5sleep3407899cyclictest09:00:253
120342620,7sleep2407799cyclictest09:40:202
139391570,1ptp4l18537-21ls08:45:253
139391530,1ptp4l401ktimersoftd/312:05:453
139391520,1ptp4l401ktimersoftd/310:18:553
139391520,1ptp4l401ktimersoftd/310:18:543
139391510,1ptp4l0-21swapper/308:01:433
4078994413,7cyclictest41-21ksoftirqd/307:15:003
4078994410,3cyclictest41-21ksoftirqd/309:20:003
139391430,0ptp4l401ktimersoftd/311:43:453
4078994213,4cyclictest41-21ksoftirqd/308:40:013
4078994211,7cyclictest41-21ksoftirqd/310:25:013
4077994236,3cyclictest207-21systemd-journal09:25:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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