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2025-11-22 - 13:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Nov 22, 2025 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37682207173,23sleep30-21swapper/319:08:433
35422204171,22sleep10-21swapper/119:05:561
36432203170,22sleep20-21swapper/219:07:052
35212201168,22sleep00-21swapper/019:05:380
455521330,7sleep2416399cyclictest20:15:252
25352610,2sleep10-21swapper/121:20:181
136991560,1ptp4l401ktimersoftd/323:28:273
41492530,2sleep10-21swapper/122:30:231
141962520,3sleep00-21swapper/020:35:280
136991520,1ptp4l401ktimersoftd/319:17:403
4163994942,4cyclictest25460-21cron22:10:002
4163994942,4cyclictest25460-21cron22:10:002
236242490,1sleep30-21swapper/322:05:143
236242490,1sleep30-21swapper/322:05:133
39182480,2sleep30-21swapper/322:30:213
136991480,1ptp4l401ktimersoftd/323:52:483
136991460,1ptp4l401ktimersoftd/322:29:233
136991450,0ptp4l401ktimersoftd/300:25:443
213792440,2sleep30-21swapper/319:45:133
136991440,0ptp4l401ktimersoftd/320:01:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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