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2026-05-25 - 19:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon May 25, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216852230163,22sleep00-21swapper/007:06:420
218762219155,21sleep10-21swapper/107:09:121
139491204170,22phc2sys0-21swapper/307:05:303
218522200166,22sleep20-21swapper/207:08:532
2194728765,12sleep10-21swapper/107:10:011
2194728765,12sleep10-21swapper/107:10:001
139391720,1ptp4l21094-21irqstats11:35:173
22240996710,18cyclictest0-21swapper/211:00:262
2224099659,11cyclictest4301-21awk12:10:012
22240996510,11cyclictest2332-21tr09:50:142
2224099647,12cyclictest8552-21ls10:00:272
2224099647,11cyclictest1918-21perf09:50:002
2224099639,11cyclictest23777-21awk10:35:012
2224099638,11cyclictest23441-21cut11:40:192
2224099637,11cyclictest26506-21tr10:40:132
2224099627,16cyclictest20221-21gzip08:10:232
2224099619,10cyclictest5587-21ls08:50:002
2224099619,10cyclictest18190-21awk08:05:272
2224099618,18cyclictest9175-21latency_hist12:20:012
2224099618,18cyclictest23049-21sed07:10:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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