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2026-09-02 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Sep 02, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
146652207181,17sleep10-21swapper/119:09:591
144282205171,23sleep20-21swapper/219:06:532
145812203170,22sleep00-21swapper/019:08:520
143182203168,23sleep30-21swapper/319:05:353
3228921560,7sleep11495899cyclictest23:05:261
244432760,8sleep01495799cyclictest22:50:210
14960995322,3cyclictest41-21ksoftirqd/322:35:273
139391530,1ptp4l401ktimersoftd/320:30:533
14960995221,3cyclictest41-21ksoftirqd/322:44:593
14960995220,9cyclictest41-21ksoftirqd/300:00:203
14960995220,9cyclictest41-21ksoftirqd/300:00:203
14960995219,4cyclictest41-21ksoftirqd/323:15:003
126062510,2sleep30-21swapper/320:10:213
14960995014,8cyclictest41-21ksoftirqd/319:49:593
65962490,2sleep00-21swapper/020:00:120
14960994920,7cyclictest41-21ksoftirqd/319:25:013
14960994920,6cyclictest41-21ksoftirqd/322:10:003
14960994919,4cyclictest41-21ksoftirqd/322:50:153
14960994919,4cyclictest41-21ksoftirqd/321:45:143
14960994916,7cyclictest41-21ksoftirqd/321:35:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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