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2026-04-20 - 02:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Apr 19, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,23phc2sys0-21swapper/307:07:473
103862204129,41sleep20-21swapper/207:05:102
103802204171,22sleep10-21swapper/107:05:041
123052202168,23sleep00-21swapper/007:07:250
1819021410,7sleep01280699cyclictest07:20:170
2242221330,3sleep31280999cyclictest09:45:003
139391900,1ptp4l6220-21ls10:15:263
139391850,1ptp4l391rcuc/309:50:253
1394918464,10phc2sys0-21swapper/307:10:003
263322630,2sleep10-21swapper/112:05:231
232322610,7sleep11280799cyclictest12:00:181
139391580,1ptp4l391rcuc/309:55:163
139391550,1ptp4l391rcuc/309:30:253
217472540,3sleep00-21swapper/008:35:170
119652510,2sleep20-21swapper/209:20:242
139391440,0ptp4l401ktimersoftd/308:29:293
12807994422,3cyclictest25-21ksoftirqd/110:10:011
139391430,0ptp4l401ktimersoftd/311:25:303
12807994313,4cyclictest25-21ksoftirqd/108:25:001
57898420,1rtkit-daemon0-21swapper/009:24:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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