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2026-07-11 - 03:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 11, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12342230169,49sleep10-21swapper/119:07:401
139491225159,22phc2sys0-21swapper/319:08:083
12032204169,23sleep20-21swapper/219:07:182
11552204171,22sleep00-21swapper/019:06:400
139491163123,31phc2sys0-21swapper/319:10:003
1729996631,4cyclictest25-21ksoftirqd/121:45:001
1729996431,8cyclictest25-21ksoftirqd/121:20:011
173099638,11cyclictest28434-21cut21:10:182
1729996330,7cyclictest25-21ksoftirqd/120:45:141
1729996326,4cyclictest25-21ksoftirqd/120:15:151
1729996322,10cyclictest25-21ksoftirqd/119:55:211
173099627,16cyclictest0-21swapper/220:30:242
173099624,17cyclictest0-21swapper/221:20:142
1729996228,7cyclictest25-21ksoftirqd/120:35:171
1729996226,4cyclictest25-21ksoftirqd/120:10:281
1729996220,8cyclictest25-21ksoftirqd/122:50:281
139391620,1ptp4l401ktimersoftd/300:08:543
1729996129,7cyclictest25-21ksoftirqd/120:40:131
1729996129,6cyclictest25-21ksoftirqd/120:00:141
1729996127,8cyclictest25-21ksoftirqd/121:05:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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