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2026-01-09 - 16:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jan 09, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
103832203170,22sleep20-21swapper/207:09:522
100892198165,22sleep30-21swapper/307:06:083
103212197163,23sleep00-21swapper/007:09:020
103822196163,22sleep10-21swapper/107:09:511
2436621550,5sleep31069099cyclictest12:05:253
2812221480,4sleep21068999cyclictest10:00:172
2000821390,4sleep11068899cyclictest08:35:191
3207921190,3sleep11068899cyclictest12:22:451
10690996526,5cyclictest41-21ksoftirqd/311:15:143
10690996526,5cyclictest41-21ksoftirqd/311:15:143
130522640,5sleep10-21swapper/108:20:221
10689996131,22cyclictest33-21ksoftirqd/208:59:592
301372590,3sleep00-21swapper/012:20:100
10690995623,7cyclictest41-21ksoftirqd/307:15:263
10690995621,7cyclictest41-21ksoftirqd/310:55:263
10690995424,7cyclictest41-21ksoftirqd/311:40:193
10690995424,7cyclictest41-21ksoftirqd/310:25:263
10690995328,9cyclictest41-21ksoftirqd/309:30:283
10690995317,4cyclictest41-21ksoftirqd/308:10:013
10690995315,10cyclictest41-21ksoftirqd/308:19:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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