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2026-07-28 - 18:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jul 28, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186392204172,21sleep20-21swapper/207:05:462
187862203170,22sleep00-21swapper/007:07:410
187272203170,22sleep10-21swapper/107:06:531
139491203170,22phc2sys0-21swapper/307:06:233
2254021530,5sleep31926999cyclictest10:35:283
19268996524,5cyclictest33-21ksoftirqd/210:00:162
19268996326,6cyclictest33-21ksoftirqd/211:25:142
19268996223,6cyclictest33-21ksoftirqd/208:20:152
1926899616,4cyclictest16385-21cron09:20:002
19268996130,9cyclictest33-21ksoftirqd/211:55:252
19268996025,11cyclictest33-21ksoftirqd/207:57:032
19268996022,6cyclictest33-21ksoftirqd/209:40:152
19268995930,5cyclictest33-21ksoftirqd/212:15:132
19268995827,11cyclictest33-21ksoftirqd/211:22:232
19268995826,5cyclictest33-21ksoftirqd/210:55:132
19268995822,5cyclictest33-21ksoftirqd/210:15:282
19268995728,9cyclictest33-21ksoftirqd/212:35:152
19268995728,9cyclictest33-21ksoftirqd/212:35:142
19268995726,7cyclictest33-21ksoftirqd/211:10:202
19268995723,6cyclictest33-21ksoftirqd/210:35:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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