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2025-12-29 - 19:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 29, 2025 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205171,23phc2sys0-21swapper/307:07:473
115282204169,24sleep00-21swapper/007:09:340
112412202168,23sleep20-21swapper/207:05:502
113272199166,22sleep10-21swapper/107:06:561
235421360,7sleep21186499cyclictest12:25:212
1941221180,3sleep31186599cyclictest11:55:133
11862997134,6cyclictest9-21ksoftirqd/011:20:000
11862996935,5cyclictest9-21ksoftirqd/012:40:000
11862996833,5cyclictest9-21ksoftirqd/007:40:000
11862996831,6cyclictest9-21ksoftirqd/010:30:000
11865996524,10cyclictest41-21ksoftirqd/308:50:003
11862996532,5cyclictest9-21ksoftirqd/012:00:000
11862996531,4cyclictest9-21ksoftirqd/008:09:590
11865996428,7cyclictest41-21ksoftirqd/310:10:003
11865996427,7cyclictest41-21ksoftirqd/308:55:183
11865996427,7cyclictest41-21ksoftirqd/308:55:173
11864996423,4cyclictest33-21ksoftirqd/207:15:222
11865996331,7cyclictest41-21ksoftirqd/307:25:203
11865996331,3cyclictest41-21ksoftirqd/311:05:123
11862996328,6cyclictest9-21ksoftirqd/009:54:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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