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2026-09-23 - 04:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Sep 23, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
103672226159,23sleep00-21swapper/019:05:450
139491214147,22phc2sys0-21swapper/319:09:483
103462202168,22sleep10-21swapper/119:05:311
105392199167,21sleep20-21swapper/219:07:522
537721730,6sleep31099799cyclictest20:05:173
1264221640,6sleep21099699cyclictest21:25:282
10997997035,3cyclictest41-21ksoftirqd/320:20:003
10997996629,8cyclictest41-21ksoftirqd/320:40:013
10997996327,11cyclictest41-21ksoftirqd/322:30:003
1099599630,25cyclictest6748-21grep00:35:261
267232620,3sleep30-21swapper/300:10:243
10997996226,4cyclictest41-21ksoftirqd/323:30:003
277462610,4sleep11099599cyclictest23:05:241
10997996129,8cyclictest41-21ksoftirqd/319:20:003
10997996129,4cyclictest41-21ksoftirqd/323:05:213
10997996126,10cyclictest41-21ksoftirqd/323:50:253
10997996124,9cyclictest41-21ksoftirqd/323:30:173
10997996123,8cyclictest41-21ksoftirqd/322:05:253
1099499614,18cyclictest8918-21date22:25:270
10997996026,7cyclictest41-21ksoftirqd/320:05:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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