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2025-12-19 - 23:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Dec 19, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172322204172,21sleep10-21swapper/107:08:101
139491204170,23phc2sys0-21swapper/307:07:343
172362203170,22sleep00-21swapper/007:08:140
171162202168,23sleep20-21swapper/207:06:392
17674996729,7cyclictest25-21ksoftirqd/112:35:191
17675996624,4cyclictest33-21ksoftirqd/209:10:252
17675996329,5cyclictest33-21ksoftirqd/208:45:172
17675996223,4cyclictest33-21ksoftirqd/209:55:172
17675996114,11cyclictest33-21ksoftirqd/212:25:232
17673996133,4cyclictest9-21ksoftirqd/011:15:210
17673996130,6cyclictest9-21ksoftirqd/011:00:180
17673996129,7cyclictest9-21ksoftirqd/012:30:000
17673996124,9cyclictest9-21ksoftirqd/007:40:300
134391610,7getstats1767699cyclictest10:48:513
17674996019,5cyclictest25-21ksoftirqd/110:20:171
17673996032,7cyclictest9-21ksoftirqd/011:10:230
17673996032,7cyclictest9-21ksoftirqd/007:50:120
17675995926,4cyclictest33-21ksoftirqd/211:05:252
17675995919,7cyclictest33-21ksoftirqd/207:10:232
17673995932,7cyclictest9-21ksoftirqd/008:55:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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