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2026-02-08 - 13:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Feb 08, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308302204169,23sleep20-21swapper/219:06:552
310152203170,22sleep10-21swapper/119:09:181
308312203171,22sleep30-21swapper/319:06:553
307632196163,22sleep00-21swapper/019:06:090
2283621470,4sleep23136199cyclictest23:20:152
139391830,1ptp4l25039-21df21:10:143
3136099679,11cyclictest16081-21latency_hist22:00:011
3136099669,12cyclictest12016-21grep22:55:261
3136099669,12cyclictest10616-21tr20:40:131
3136099647,10cyclictest12164-21df00:05:141
46042630,6sleep13136099cyclictest22:40:231
63632620,2sleep30-21swapper/319:25:133
3136099629,17cyclictest28373-21df_abs20:10:141
3136099627,12cyclictest16563-21latency_hist00:15:011
3136099618,12cyclictest8726-21sed22:50:181
3136099618,10cyclictest17591-21/usr/sbin/munin20:55:221
31360996110,11cyclictest16015-21apt-config19:45:011
3136099608,12cyclictest23327-21egrep20:00:121
3136099608,11cyclictest9959-21sed21:45:191
3136099608,11cyclictest21762-21cut19:55:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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