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2026-07-24 - 09:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 24, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214732207173,23sleep20-21swapper/219:06:372
216562202169,22sleep00-21swapper/019:09:000
215372202169,22sleep30-21swapper/319:07:263
214722202168,22sleep10-21swapper/119:06:361
1707321360,5sleep02202699cyclictest23:25:250
139391560,1ptp4l401ktimersoftd/323:21:193
22029995523,7cyclictest41-21ksoftirqd/323:20:013
22029995420,4cyclictest41-21ksoftirqd/322:50:013
139391530,1ptp4l401ktimersoftd/320:54:023
22029995020,6cyclictest41-21ksoftirqd/300:34:593
139391500,1ptp4l401ktimersoftd/322:55:153
270482470,1sleep30-21swapper/321:35:013
22029994717,4cyclictest41-21ksoftirqd/320:50:013
22029994714,8cyclictest41-21ksoftirqd/319:25:003
22029994616,4cyclictest41-21ksoftirqd/319:35:013
22029994616,3cyclictest41-21ksoftirqd/320:25:213
22029994615,4cyclictest41-21ksoftirqd/321:55:193
22029994615,3cyclictest41-21ksoftirqd/320:00:293
22029994615,3cyclictest41-21ksoftirqd/320:00:293
2202999457,11cyclictest41-21ksoftirqd/300:20:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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