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2026-03-18 - 11:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Mar 18, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491204170,23phc2sys0-21swapper/319:06:593
106502203171,21sleep20-21swapper/219:07:372
106262202169,22sleep00-21swapper/019:07:190
105962202169,22sleep10-21swapper/119:06:551
1083428263,11sleep10-21swapper/119:10:001
139391610,1ptp4l401ktimersoftd/321:08:233
10982570,4sleep31100-21latency19:55:193
139391560,1ptp4l401ktimersoftd/322:01:273
211642550,7sleep01112599cyclictest20:35:270
57898440,8rtkit-daemon0-21swapper/100:25:391
139391440,0ptp4l401ktimersoftd/319:34:593
57898430,7rtkit-daemon0-21swapper/120:38:331
139391430,0ptp4l401ktimersoftd/320:41:023
11125994314,7cyclictest9-21ksoftirqd/023:50:000
139391420,1ptp4l401ktimersoftd/320:56:053
139391420,0ptp4l401ktimersoftd/323:56:113
139391420,0ptp4l401ktimersoftd/323:47:073
139391420,0ptp4l401ktimersoftd/323:08:313
139391420,0ptp4l401ktimersoftd/319:50:303
11125994236,3cyclictest9-21ksoftirqd/021:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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