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2026-04-20 - 08:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Apr 20, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37882217151,22sleep00-21swapper/019:06:110
40452205172,22sleep20-21swapper/219:09:272
40762204169,23sleep30-21swapper/319:09:523
39152202168,22sleep10-21swapper/119:07:451
3128221520,6sleep1438499cyclictest20:05:181
139391810,1ptp4l391rcuc/300:35:253
139391560,1ptp4l391rcuc/323:15:313
4312520,2sleep30-21swapper/320:10:013
139391500,1ptp4l391rcuc/322:34:163
438599491,45cyclictest18590-21kworker/2:119:55:232
409124937,6sleep00-21swapper/019:10:010
164482490,2sleep10-21swapper/119:35:001
4385994516,27cyclictest0-21swapper/222:40:332
4384994540,3cyclictest25726-21sh19:55:001
438599440,43cyclictest0-21swapper/223:00:232
438599440,43cyclictest0-21swapper/223:00:232
139391440,0ptp4l401ktimersoftd/319:16:153
139391430,0ptp4l401ktimersoftd/323:33:403
139391430,0ptp4l401ktimersoftd/322:23:283
139391430,0ptp4l401ktimersoftd/321:53:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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