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2025-12-31 - 22:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Dec 31, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1608921880,6sleep0949999cyclictest07:30:220
1386521770,5sleep3950299cyclictest07:16:213
369521660,5sleep3950299cyclictest10:35:263
1400621620,2sleep1950099cyclictest07:17:391
1337421580,6sleep3950299cyclictest08:40:253
1393911270,1ptp4l13658-21df12:05:133
13949110364,31phc2sys0-21swapper/307:08:063
139391990,1ptp4l2533-21spawn07:30:583
905829269,15sleep20-21swapper/207:08:112
885429268,16sleep10-21swapper/107:05:331
888029166,16sleep00-21swapper/007:05:520
139702890,2sleep213967-21execl07:17:122
211262690,5sleep221145-21spawn07:30:122
193362640,6sleep019349-21rm07:38:210
192892640,4sleep20-21swapper/207:36:142
150132640,3sleep115021-21spawn07:29:391
288552620,5sleep128767-21multi.sh07:39:221
139391620,1ptp4l7846-21cut10:45:163
123502620,6sleep0949999cyclictest09:45:330
139122610,5sleep013905-21execl07:16:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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