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2026-08-18 - 12:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Aug 18, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491204170,23phc2sys0-21swapper/319:05:113
275562203169,22sleep20-21swapper/219:06:112
278512202170,21sleep10-21swapper/119:09:561
275592201168,22sleep00-21swapper/019:06:130
1393911290,0ptp4l391rcuc/323:00:193
139391890,1ptp4l17777-21cat22:10:143
57898640,51rtkit-daemon0-21swapper/019:10:010
139391610,1ptp4l401ktimersoftd/321:08:183
177342590,2sleep02815199cyclictest21:00:290
165252570,5sleep2311rcuc/200:20:262
139391540,1ptp4l401ktimersoftd/320:53:423
139391530,0ptp4l401ktimersoftd/321:22:133
28152995223,4cyclictest25-21ksoftirqd/121:35:211
2815199527,3cyclictest9-21ksoftirqd/020:48:180
2815199527,3cyclictest9-21ksoftirqd/020:48:180
28152995122,3cyclictest25-21ksoftirqd/123:00:271
28152995020,4cyclictest25-21ksoftirqd/122:55:211
28154994925,15cyclictest41-21ksoftirqd/300:00:153
28152994919,3cyclictest25-21ksoftirqd/121:25:261
28152994919,3cyclictest25-21ksoftirqd/121:25:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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