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2026-07-25 - 23:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 25, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491205171,22phc2sys0-21swapper/307:09:273
221182202170,21sleep10-21swapper/107:08:531
219562202169,22sleep00-21swapper/007:06:470
219312202167,24sleep20-21swapper/207:06:292
22507998019,59cyclictest0-21swapper/109:40:331
22507997515,58cyclictest0-21swapper/111:40:341
139391680,1ptp4l391rcuc/310:45:503
139391610,1ptp4l401ktimersoftd/308:25:483
311612590,4sleep331164-21df_abs08:35:163
2250799560,1cyclictest0-21swapper/110:50:331
139391560,1ptp4l401ktimersoftd/310:09:533
22508995525,4cyclictest33-21ksoftirqd/208:20:172
22508995422,4cyclictest33-21ksoftirqd/209:40:262
22508995323,4cyclictest33-21ksoftirqd/211:30:172
22508995323,4cyclictest33-21ksoftirqd/209:40:002
22508995320,4cyclictest33-21ksoftirqd/210:40:012
22508995320,4cyclictest33-21ksoftirqd/210:40:012
2250699510,3cyclictest23471-21runrttasks08:20:060
139391510,1ptp4l391rcuc/307:45:233
22508995018,3cyclictest33-21ksoftirqd/208:35:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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