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2026-01-24 - 23:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 24, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208173,23phc2sys0-21swapper/307:08:083
127822203170,22sleep00-21swapper/007:08:310
126282203170,22sleep10-21swapper/107:06:321
126242203170,22sleep20-21swapper/207:06:282
2741621160,2sleep00-21swapper/008:45:190
13193997311,19cyclictest12511-21awk11:35:270
13195996428,4cyclictest33-21ksoftirqd/211:35:272
13193996410,13cyclictest6275-21cut09:10:130
13195996321,6cyclictest33-21ksoftirqd/207:20:162
13195996224,8cyclictest33-21ksoftirqd/212:15:262
1319399629,11cyclictest22470-21chrt10:50:180
13195996129,4cyclictest33-21ksoftirqd/209:55:132
13195996125,4cyclictest33-21ksoftirqd/210:45:132
13195996125,4cyclictest33-21ksoftirqd/210:45:122
1319399619,10cyclictest1-21systemd08:15:240
13195996027,9cyclictest33-21ksoftirqd/212:05:272
13195996027,10cyclictest33-21ksoftirqd/210:00:192
13195996025,7cyclictest33-21ksoftirqd/210:25:012
1319399609,12cyclictest15036-21awk09:25:260
1319399608,10cyclictest14832-21df_abs08:20:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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