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2026-01-29 - 08:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jan 29, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
261562211164,35sleep30-21swapper/319:09:473
260332203170,22sleep00-21swapper/019:08:110
260352202170,21sleep20-21swapper/219:08:122
259722201167,22sleep10-21swapper/119:07:241
1626121250,3sleep126465-21cyclictest19:55:161
82322580,2sleep00-21swapper/000:09:120
27952560,4sleep20-21swapper/221:40:252
139391560,1ptp4l401ktimersoftd/323:36:543
139391560,1ptp4l401ktimersoftd/322:15:193
139391560,1ptp4l401ktimersoftd/319:25:213
139391540,1ptp4l401ktimersoftd/321:38:453
139391540,1ptp4l401ktimersoftd/300:27:463
139391540,1ptp4l401ktimersoftd/300:13:043
139391530,1ptp4l401ktimersoftd/321:17:053
139391510,1ptp4l391rcuc/322:29:103
26468995033,3cyclictest33-21ksoftirqd/221:15:012
139391420,0ptp4l401ktimersoftd/320:07:523
139391410,0ptp4l401ktimersoftd/321:42:063
26467994033,4cyclictest13209-21cron22:05:001
178452400,1sleep20-21swapper/221:05:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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