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2026-06-04 - 21:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jun 04, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158242205171,22sleep10-21swapper/107:08:171
157572204170,23sleep20-21swapper/207:07:262
139491204170,23phc2sys0-21swapper/307:06:413
156362197165,21sleep00-21swapper/007:05:510
2050821680,4sleep31626199cyclictest10:40:153
1669021290,2sleep31626199cyclictest11:40:173
1669021290,2sleep31626199cyclictest11:40:163
16260996811,22cyclictest12002-21head10:20:242
1626099658,11cyclictest1456-21sed10:00:182
1626099637,11cyclictest25793-21latency_hist07:30:012
16260996310,10cyclictest30713-21sed07:40:012
1626099619,10cyclictest16056-21cut08:15:172
1626099618,16cyclictest30595-21grep11:00:202
1626099617,17cyclictest7061-21df_abs09:05:132
1626099617,16cyclictest31680-21latency_hist08:50:012
1626099616,11cyclictest23137-21latency_hist09:40:012
16260996111,10cyclictest26534-21iwlist09:45:172
16260996110,9cyclictest18418-21cut08:20:182
1626099609,10cyclictest19868-21ps09:30:222
1626099607,15cyclictest15239-21egrep10:30:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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