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2026-07-09 - 01:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jul 08, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13222208175,21sleep10-21swapper/107:05:461
139491205171,23phc2sys0-21swapper/307:08:303
14602204171,22sleep20-21swapper/207:07:232
319382201168,22sleep00-21swapper/007:05:040
16752163125,13sleep20-21swapper/207:10:012
139491163124,13phc2sys0-21swapper/307:10:013
2605921530,7sleep1196899cyclictest10:15:001
1969997116,53cyclictest1559-21kworker/2:112:30:132
196999702,65cyclictest11027-21kworker/2:108:10:332
287472650,6sleep2196999cyclictest12:35:132
240642630,2sleep20-21swapper/212:25:152
139391610,1ptp4l401ktimersoftd/307:55:183
156332550,2sleep10-21swapper/111:00:131
142302550,2sleep20-21swapper/210:55:252
139391550,1ptp4l401ktimersoftd/311:02:173
196999491,45cyclictest0-21swapper/211:50:232
1969994617,27cyclictest0-21swapper/207:30:232
196899464,9cyclictest25-21ksoftirqd/112:20:261
196899455,3cyclictest25-21ksoftirqd/112:30:181
196999443,39cyclictest18545-21ls12:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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