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2026-06-12 - 13:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jun 12, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278832222160,50sleep30-21swapper/319:08:383
278502202170,21sleep20-21swapper/219:08:122
277602201168,22sleep00-21swapper/019:07:010
277982200168,21sleep10-21swapper/119:07:301
174521650,1sleep00-21swapper/020:30:010
139491160123,13phc2sys0-21swapper/319:10:013
2973421340,5sleep32828499cyclictest23:40:233
2828499671,28cyclictest13501-21/usr/sbin/munin00:15:263
2828499670,24cyclictest18090-21taskset22:10:143
2828499660,22cyclictest2407-21wc21:35:273
28283996525,6cyclictest33-21ksoftirqd/221:20:132
2828499640,24cyclictest2869-21chrt23:50:263
2828499640,21cyclictest20226-21ls21:05:233
2828499640,21cyclictest20226-21ls21:05:233
28283996428,6cyclictest33-21ksoftirqd/219:20:002
28283996427,7cyclictest33-21ksoftirqd/200:30:282
2828499630,25cyclictest0-21swapper/322:40:253
2828499630,25cyclictest0-21swapper/322:40:253
28283996329,9cyclictest33-21ksoftirqd/200:04:592
28283996328,6cyclictest33-21ksoftirqd/221:00:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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