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2026-04-12 - 17:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Apr 12, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76372206173,22sleep00-21swapper/007:06:250
76982203169,22sleep10-21swapper/107:07:131
78062202169,22sleep30-21swapper/307:08:363
77852201169,21sleep20-21swapper/207:08:182
292121370,4sleep2821899cyclictest08:05:182
2134821360,6sleep0821699cyclictest07:35:240
8217995854,2cyclictest231rcuc/110:56:521
8217995754,2cyclictest231rcuc/110:52:021
139391570,1ptp4l401ktimersoftd/307:45:163
8217995653,2cyclictest231rcuc/111:52:281
8217995653,2cyclictest231rcuc/110:27:471
8217995653,2cyclictest231rcuc/108:10:561
8217995622,6cyclictest25-21ksoftirqd/107:25:231
8217995553,1cyclictest231rcuc/107:14:441
8217995552,2cyclictest231rcuc/112:01:461
8217995552,2cyclictest231rcuc/111:47:141
8217995552,2cyclictest231rcuc/109:41:181
145892550,2sleep10-21swapper/108:30:161
139391550,1ptp4l401ktimersoftd/311:31:493
821799545,9cyclictest25-21ksoftirqd/109:05:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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