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2026-08-13 - 08:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 13, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491209175,23phc2sys0-21swapper/319:07:583
317592207173,23sleep00-21swapper/019:09:230
315102203170,22sleep20-21swapper/219:06:072
316732202169,22sleep10-21swapper/119:08:161
139391670,1ptp4l401ktimersoftd/321:15:263
130922610,4sleep213093-21irqrtprio21:50:192
134491600,7getstats3211099cyclictest00:27:063
139391590,8ptp4l401ktimersoftd/321:56:123
3210999560,15cyclictest14500-21/usr/sbin/munin23:00:172
139391560,1ptp4l401ktimersoftd/319:24:593
3210999547,6cyclictest14811-21tr21:55:142
3210999541,11cyclictest23279-21latency00:25:192
3210999522,17cyclictest4176-21df_abs22:40:132
3210999520,20cyclictest1759-21switchtime21:25:262
264782520,3sleep20-21swapper/220:05:012
3210999512,10cyclictest9209-21awk21:40:262
3210999511,10cyclictest19642-21/usr/sbin/munin19:50:142
3210999507,6cyclictest22851-21date22:10:202
3210999506,5cyclictest20754-21date23:15:012
3210999500,10cyclictest7233-21/usr/sbin/munin22:45:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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