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2026-05-05 - 07:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue May 05, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249282226163,20sleep20-21swapper/219:09:142
139491207173,22phc2sys0-21swapper/319:07:513
248602202169,22sleep10-21swapper/119:08:211
248542200167,22sleep00-21swapper/019:08:150
3198521640,5sleep12528099cyclictest21:40:001
25279996228,4cyclictest9-21ksoftirqd/020:00:000
25280996113,11cyclictest16357-21sed23:20:181
25279996129,6cyclictest9-21ksoftirqd/019:20:280
296982600,2sleep10-21swapper/120:25:181
2528099590,18cyclictest0-21swapper/120:00:251
25279995925,5cyclictest9-21ksoftirqd/023:05:000
25279995924,5cyclictest9-21ksoftirqd/023:15:000
25279995923,8cyclictest9-21ksoftirqd/021:40:020
326652580,2sleep10-21swapper/119:25:131
25279995828,4cyclictest9-21ksoftirqd/019:30:010
25279995825,4cyclictest9-21ksoftirqd/021:35:010
25279995825,4cyclictest9-21ksoftirqd/020:35:000
25279995822,7cyclictest9-21ksoftirqd/022:15:210
25279995822,5cyclictest9-21ksoftirqd/000:40:010
25279995722,7cyclictest9-21ksoftirqd/023:20:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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