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2026-07-24 - 22:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 24, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
169662206172,23sleep20-21swapper/207:07:492
139491206173,22phc2sys0-21swapper/307:06:023
168502202170,21sleep10-21swapper/107:06:201
168492202169,22sleep00-21swapper/007:06:180
1743499692,22cyclictest28351-21grep10:55:142
1743499690,26cyclictest1992-21grep08:50:232
1743499650,29cyclictest2987-21date11:10:012
1743499640,24cyclictest16377-21date08:15:002
1743499611,21cyclictest2877-21missed_timers12:15:202
1743499590,23cyclictest6329-21awk07:50:292
237342570,2sleep20-21swapper/211:50:272
1743499570,23cyclictest23648-21awk07:20:262
139391550,1ptp4l401ktimersoftd/311:13:193
17432995249,2cyclictest111rcuc/011:45:140
17432995224,9cyclictest9-21ksoftirqd/007:55:170
17432995219,5cyclictest9-21ksoftirqd/008:17:070
128132510,2sleep20-21swapper/211:30:132
1743299505,8cyclictest9-21ksoftirqd/011:25:180
17432994924,8cyclictest9-21ksoftirqd/008:45:140
17432994916,7cyclictest9-21ksoftirqd/011:20:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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