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2026-03-15 - 10:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 15, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491225197,18phc2sys0-21swapper/319:07:593
322112206173,22sleep00-21swapper/019:06:280
321762202169,22sleep20-21swapper/219:06:012
324002199167,21sleep10-21swapper/119:08:501
1914021600,5sleep331999cyclictest20:55:173
2056421470,7sleep131799cyclictest00:20:141
2764921310,4sleep231899cyclictest20:05:172
3249328163,10sleep00-21swapper/019:10:000
318996629,8cyclictest33-21ksoftirqd/200:00:012
139391660,1ptp4l401ktimersoftd/322:41:383
318996529,4cyclictest33-21ksoftirqd/223:20:002
318996429,5cyclictest33-21ksoftirqd/220:50:172
318996428,5cyclictest33-21ksoftirqd/221:45:002
318996428,5cyclictest33-21ksoftirqd/220:25:012
318996428,5cyclictest33-21ksoftirqd/220:25:012
318996427,7cyclictest33-21ksoftirqd/221:45:222
318996328,6cyclictest33-21ksoftirqd/200:35:002
318996327,5cyclictest33-21ksoftirqd/221:05:012
318996327,5cyclictest33-21ksoftirqd/219:24:592
318996326,8cyclictest33-21ksoftirqd/222:30:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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