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2026-06-21 - 16:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jun 21, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
252782236171,22sleep10-21swapper/107:08:371
139491207172,23phc2sys0-21swapper/307:09:253
253752205172,22sleep20-21swapper/207:09:482
252102205172,22sleep00-21swapper/007:07:450
986821640,7sleep12568599cyclictest11:05:221
25687997327,5cyclictest41-21ksoftirqd/308:45:013
25687997024,5cyclictest41-21ksoftirqd/309:50:193
25687996534,9cyclictest41-21ksoftirqd/311:45:003
25687996324,11cyclictest41-21ksoftirqd/310:55:163
25687996323,12cyclictest41-21ksoftirqd/310:30:223
25687996321,11cyclictest41-21ksoftirqd/309:55:173
25687996321,11cyclictest41-21ksoftirqd/309:55:173
25687996313,10cyclictest41-21ksoftirqd/309:45:153
25685996332,7cyclictest25-21ksoftirqd/112:10:131
25687996227,5cyclictest41-21ksoftirqd/309:29:593
25687996226,5cyclictest41-21ksoftirqd/307:55:003
25687996224,5cyclictest41-21ksoftirqd/307:15:253
25687996129,4cyclictest41-21ksoftirqd/308:30:243
25687996129,10cyclictest41-21ksoftirqd/308:45:133
25687996126,9cyclictest41-21ksoftirqd/308:25:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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