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2026-08-17 - 00:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Aug 16, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491232168,53phc2sys0-21swapper/307:06:493
190942213147,22sleep10-21swapper/107:07:511
191002205171,23sleep20-21swapper/207:07:572
189272202168,23sleep00-21swapper/007:05:420
1253621690,6sleep01955999cyclictest08:00:240
2800421640,5sleep31956299cyclictest07:25:263
2774221520,6sleep01955999cyclictest10:50:140
173052680,7sleep01955999cyclictest11:35:150
19560996733,4cyclictest25-21ksoftirqd/110:05:001
19560996528,9cyclictest25-21ksoftirqd/108:05:191
19560996430,7cyclictest25-21ksoftirqd/108:50:001
19560996429,4cyclictest25-21ksoftirqd/109:25:011
139391640,1ptp4l401ktimersoftd/312:29:123
19560996332,8cyclictest25-21ksoftirqd/111:55:281
19560996330,4cyclictest25-21ksoftirqd/111:05:001
19560996327,7cyclictest25-21ksoftirqd/107:30:261
19560996228,4cyclictest25-21ksoftirqd/107:55:001
19560996222,6cyclictest25-21ksoftirqd/107:20:241
19560996220,8cyclictest25-21ksoftirqd/111:40:141
19560996129,4cyclictest25-21ksoftirqd/109:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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