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2026-07-17 - 11:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jul 17, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305732206173,22sleep20-21swapper/219:07:382
307092205171,22sleep10-21swapper/119:09:261
139491205170,23phc2sys0-21swapper/319:09:483
307202202169,22sleep00-21swapper/019:09:330
224621360,4sleep13104599cyclictest19:15:231
31045997518,55cyclictest0-21swapper/122:47:131
31046996231,3cyclictest33-21ksoftirqd/220:25:192
31046996227,11cyclictest33-21ksoftirqd/222:15:152
31046996226,5cyclictest33-21ksoftirqd/221:50:252
31046996129,4cyclictest33-21ksoftirqd/222:10:262
31046996126,4cyclictest33-21ksoftirqd/220:45:242
31046996028,4cyclictest33-21ksoftirqd/200:05:002
31046995929,9cyclictest33-21ksoftirqd/221:20:242
31046995924,4cyclictest33-21ksoftirqd/222:35:222
31046995924,4cyclictest33-21ksoftirqd/222:35:212
31046995828,4cyclictest33-21ksoftirqd/221:30:332
3104799574,12cyclictest1195-21sed21:30:003
31046995726,9cyclictest33-21ksoftirqd/219:25:222
31046995722,4cyclictest33-21ksoftirqd/223:00:172
3104799568,11cyclictest20667-21awk23:15:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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