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2026-05-28 - 18:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu May 28, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4442242197,34sleep30-21swapper/307:10:003
326662204171,22sleep20-21swapper/207:07:002
325772204170,23sleep00-21swapper/007:05:500
326652201168,22sleep10-21swapper/107:06:591
139391620,1ptp4l0-21swapper/309:40:233
139391590,1ptp4l401ktimersoftd/309:20:333
279362540,5sleep09-21ksoftirqd/012:35:160
77999515,42cyclictest12685-21turbostat12:05:013
139391500,0ptp4l401ktimersoftd/308:44:023
777994337,4cyclictest27107-21cron12:34:591
776994325,15cyclictest9-21ksoftirqd/008:35:120
139391430,0ptp4l401ktimersoftd/308:09:433
77799421,39cyclictest0-21swapper/111:56:031
139391420,35ptp4l0-21swapper/307:10:013
139391420,0ptp4l401ktimersoftd/311:30:183
139391410,0ptp4l401ktimersoftd/311:13:303
139391400,0ptp4l401ktimersoftd/311:45:153
139391400,0ptp4l401ktimersoftd/308:10:373
778993934,3cyclictest12488-21cron09:50:002
139391390,0ptp4l401ktimersoftd/312:20:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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