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2026-09-16 - 23:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Sep 16, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230163,23phc2sys0-21swapper/307:08:553
13512204170,23sleep20-21swapper/207:05:412
14452202169,22sleep00-21swapper/007:06:480
13452202169,22sleep10-21swapper/107:05:371
139391570,1ptp4l401ktimersoftd/308:08:103
130942570,3sleep013098-21irqrtprio12:00:170
139391550,1ptp4l401ktimersoftd/308:15:153
293912540,6sleep2200599cyclictest12:35:142
139391540,1ptp4l401ktimersoftd/310:57:293
139391490,8ptp4l401ktimersoftd/309:04:223
200599474,8cyclictest0-21swapper/212:25:222
2004994741,3cyclictest3795-21grep10:35:011
200599465,8cyclictest0-21swapper/209:00:172
2004994628,3cyclictest25-21ksoftirqd/108:10:001
200599445,4cyclictest33-21ksoftirqd/210:45:122
2005994412,6cyclictest33-21ksoftirqd/212:35:012
200599435,6cyclictest33-21ksoftirqd/210:35:012
200599433,6cyclictest33-21ksoftirqd/208:25:192
200599433,6cyclictest33-21ksoftirqd/208:25:192
200599432,4cyclictest33-21ksoftirqd/210:07:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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