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2026-08-18 - 00:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 17, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230164,22phc2sys0-21swapper/307:06:223
313392205172,22sleep00-21swapper/007:08:510
313472204171,22sleep10-21swapper/107:08:561
312802204170,23sleep20-21swapper/207:08:042
2373421360,6sleep33173499cyclictest11:20:253
3143928262,11sleep20-21swapper/207:10:012
139391710,1ptp4l401ktimersoftd/308:50:223
139391700,1ptp4l401ktimersoftd/310:24:583
139391640,1ptp4l401ktimersoftd/312:21:053
139391570,1ptp4l401ktimersoftd/307:18:223
139391560,1ptp4l401ktimersoftd/312:38:383
141842550,2sleep10-21swapper/109:55:191
31732995414,3cyclictest25-21ksoftirqd/111:12:021
31732995414,3cyclictest25-21ksoftirqd/111:12:021
31732995414,3cyclictest25-21ksoftirqd/109:20:431
31732995414,3cyclictest25-21ksoftirqd/109:20:431
91182530,3sleep23173399cyclictest09:45:132
3173299533,15cyclictest10887-21cron12:05:001
3173299527,7cyclictest23628-21/usr/sbin/munin09:05:241
31732995214,6cyclictest25-21ksoftirqd/108:45:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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