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2026-03-27 - 12:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Mar 27, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206173,22phc2sys0-21swapper/319:09:343
296152203169,23sleep10-21swapper/119:08:341
296712201168,22sleep00-21swapper/019:09:180
295022201168,22sleep20-21swapper/219:07:072
526721670,1sleep20-21swapper/220:30:272
2019921590,7sleep13001699cyclictest23:40:001
326482930,8sleep1241ktimersoftd/100:05:161
326482930,8sleep1241ktimersoftd/100:05:151
30018996832,4cyclictest41-21ksoftirqd/322:35:003
208032650,4sleep30-21swapper/323:40:143
30018996228,5cyclictest41-21ksoftirqd/319:20:223
30018996130,4cyclictest41-21ksoftirqd/323:35:173
30018996027,4cyclictest41-21ksoftirqd/322:25:203
30018995927,8cyclictest41-21ksoftirqd/320:55:013
30018995926,6cyclictest41-21ksoftirqd/319:35:183
294622590,4sleep00-21swapper/022:50:160
30018995830,4cyclictest41-21ksoftirqd/321:20:193
30018995827,8cyclictest41-21ksoftirqd/323:45:203
30018995826,4cyclictest41-21ksoftirqd/320:40:003
30018995826,4cyclictest41-21ksoftirqd/319:15:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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