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2026-03-16 - 15:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 16, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491229163,22phc2sys0-21swapper/307:06:193
92752206173,22sleep10-21swapper/107:07:251
92182206141,22sleep00-21swapper/007:06:380
94162205171,23sleep20-21swapper/207:09:142
1696221630,6sleep1977999cyclictest08:30:191
2749421420,6sleep2978099cyclictest07:45:192
2006221400,5sleep0977899cyclictest10:50:270
948627055,7sleep00-21swapper/007:10:000
70082610,6sleep0101ktimersoftd/011:30:260
977999555,18cyclictest5240-21sed10:20:261
238492530,3sleep223850-21latency_hist09:55:012
284832520,1sleep30-21swapper/312:15:263
9779995044,3cyclictest32687-21dump-pmu-power11:20:001
977999492,9cyclictest26901-21ssh08:50:251
977999491,45cyclictest0-21swapper/107:50:241
978099481,45cyclictest0-21swapper/208:10:242
977999483,9cyclictest4099-21/usr/sbin/munin12:35:141
977999483,8cyclictest15214-21df_inode11:50:141
977999482,9cyclictest887-21cat12:25:251
977999472,16cyclictest14450-21cut08:25:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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