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2026-08-20 - 05:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 20, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182472223196,18sleep00-21swapper/019:07:580
139491206171,23phc2sys0-21swapper/319:05:463
183062202168,23sleep20-21swapper/219:08:442
182432202169,22sleep10-21swapper/119:07:561
2592821810,5sleep21869799cyclictest20:30:202
2141221790,6sleep01869599cyclictest21:30:150
756521520,7sleep11869699cyclictest21:00:191
1588421350,7sleep11869699cyclictest20:10:171
1601621280,7sleep31869899cyclictest23:30:253
1601621280,7sleep31869899cyclictest23:30:253
488921250,6sleep21869799cyclictest23:10:142
18698996231,4cyclictest41-21ksoftirqd/323:15:253
18698996126,4cyclictest41-21ksoftirqd/322:00:013
18698996029,4cyclictest41-21ksoftirqd/323:50:003
18698995929,4cyclictest41-21ksoftirqd/321:45:003
18698995929,4cyclictest41-21ksoftirqd/320:55:233
18698995928,4cyclictest41-21ksoftirqd/319:15:213
18698995828,4cyclictest41-21ksoftirqd/322:50:003
18698995826,4cyclictest41-21ksoftirqd/320:20:233
18698995826,4cyclictest41-21ksoftirqd/319:40:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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