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2026-03-29 - 20:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Mar 29, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121042222159,51sleep20-21swapper/207:09:552
139491210176,22phc2sys0-21swapper/307:08:063
119752204171,22sleep00-21swapper/007:08:200
119302201168,22sleep10-21swapper/107:07:441
12408996332,4cyclictest41-21ksoftirqd/312:00:173
12408996331,7cyclictest41-21ksoftirqd/311:50:163
12408996230,7cyclictest41-21ksoftirqd/308:45:003
12408996230,4cyclictest41-21ksoftirqd/312:05:273
12408996230,4cyclictest41-21ksoftirqd/310:05:003
12408996229,7cyclictest41-21ksoftirqd/308:00:233
12408996228,4cyclictest41-21ksoftirqd/310:35:233
106662620,2sleep20-21swapper/209:20:192
12408996131,8cyclictest41-21ksoftirqd/311:30:003
12408996131,4cyclictest41-21ksoftirqd/310:45:143
12408996131,4cyclictest41-21ksoftirqd/309:25:183
12408996131,4cyclictest41-21ksoftirqd/307:35:243
12408996130,4cyclictest41-21ksoftirqd/308:45:223
12408996128,4cyclictest41-21ksoftirqd/311:15:013
12408996128,4cyclictest41-21ksoftirqd/308:55:123
12408996128,4cyclictest41-21ksoftirqd/307:20:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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