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2026-03-13 - 02:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 12, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2123022950,7sleep30-21swapper/307:05:153
226902203170,22sleep00-21swapper/007:07:220
227212202169,22sleep10-21swapper/107:07:471
226602202170,21sleep20-21swapper/207:06:592
3077621620,5sleep32319599cyclictest10:45:183
1124921320,6sleep32319599cyclictest07:50:213
134391610,6getstats2319599cyclictest09:39:003
139391570,1ptp4l401ktimersoftd/311:37:323
139391560,1ptp4l401ktimersoftd/309:30:173
23193995521,8cyclictest25-21ksoftirqd/110:25:251
23193995520,8cyclictest25-21ksoftirqd/107:20:231
23193995516,7cyclictest25-21ksoftirqd/111:30:171
29072540,2sleep30-21swapper/307:35:123
2319399547,3cyclictest25-21ksoftirqd/111:45:231
23193995421,3cyclictest25-21ksoftirqd/109:17:591
139391540,1ptp4l401ktimersoftd/310:22:043
2319499537,44cyclictest16051-21kworker/2:009:28:532
2319499537,44cyclictest16051-21kworker/2:009:28:532
23193995320,10cyclictest25-21ksoftirqd/109:05:141
23193995319,8cyclictest25-21ksoftirqd/108:35:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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