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2026-01-27 - 21:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 27, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
222572204170,23sleep10-21swapper/107:05:391
222932203170,22sleep20-21swapper/207:06:092
222562203169,23sleep00-21swapper/007:05:390
139491203168,23phc2sys0-21swapper/307:07:303
145112630,2sleep20-21swapper/208:00:012
133592540,2sleep30-21swapper/310:10:223
139391530,1ptp4l401ktimersoftd/307:58:133
22894995218,8cyclictest33-21ksoftirqd/207:48:032
139391520,1ptp4l401ktimersoftd/310:59:013
139391520,1ptp4l401ktimersoftd/307:47:363
22894995019,4cyclictest33-21ksoftirqd/209:30:252
2289499473,8cyclictest6162-21date08:50:002
2289599469,35cyclictest7426-21kworker/3:008:56:533
2289499463,5cyclictest321ktimersoftd/211:25:192
2289399459,10cyclictest25-21ksoftirqd/111:20:001
139391450,0ptp4l401ktimersoftd/312:25:013
2289499446,5cyclictest33-21ksoftirqd/208:50:232
2289499441,6cyclictest6996-21irqrtprio11:05:182
139391440,0ptp4l401ktimersoftd/309:28:223
139391430,0ptp4l401ktimersoftd/310:25:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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