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2026-01-25 - 16:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jan 25, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491236169,22phc2sys0-21swapper/307:06:053
285422210177,22sleep20-21swapper/207:09:402
282092207163,32sleep10-21swapper/107:05:251
284872201168,23sleep00-21swapper/007:08:580
139391660,1ptp4l401ktimersoftd/311:32:263
139391640,1ptp4l401ktimersoftd/312:27:423
139391610,0ptp4l401ktimersoftd/309:05:403
139391590,1ptp4l401ktimersoftd/312:35:383
139391560,1ptp4l401ktimersoftd/309:18:043
139391540,1ptp4l401ktimersoftd/309:55:183
2886199530,14cyclictest1300-21snmpd09:48:102
28861995214,5cyclictest33-21ksoftirqd/207:29:512
139391510,1ptp4l391rcuc/309:52:063
261402500,2sleep20-21swapper/210:25:192
2886099496,22cyclictest14384-21seq08:55:081
2886099488,29cyclictest7812-21seq09:47:231
2886099481,45cyclictest0-21swapper/107:20:231
2886099470,45cyclictest0-21swapper/108:36:121
2886199461,11cyclictest31062-21awk08:20:202
2886199460,11cyclictest6062-21grep07:30:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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