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2026-01-28 - 19:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jan 28, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
315422202169,22sleep30-21swapper/307:07:353
315462200168,21sleep20-21swapper/207:07:382
315442200167,22sleep00-21swapper/007:07:360
315402197165,21sleep10-21swapper/107:07:321
234021510,6sleep33203299cyclictest08:20:233
139391710,1ptp4l391rcuc/309:25:283
32032996228,7cyclictest41-21ksoftirqd/307:30:243
32032996126,4cyclictest41-21ksoftirqd/312:15:123
32032996120,9cyclictest41-21ksoftirqd/310:50:013
32032995620,4cyclictest41-21ksoftirqd/311:30:223
32032995528,10cyclictest41-21ksoftirqd/309:50:273
32032995518,7cyclictest41-21ksoftirqd/307:45:233
3203299544,6cyclictest21158-21cat07:54:593
32032995018,4cyclictest41-21ksoftirqd/311:20:213
32031995030,16cyclictest33-21ksoftirqd/209:55:002
32032994917,7cyclictest41-21ksoftirqd/309:10:203
32032994816,9cyclictest41-21ksoftirqd/310:45:163
254342480,1sleep30-21swapper/308:00:263
230172460,1sleep223021-21sed12:25:252
32031994530,12cyclictest33-21ksoftirqd/207:55:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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