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2026-03-09 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 09, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206171,23phc2sys0-21swapper/307:06:233
70012205172,22sleep10-21swapper/107:09:351
67402201169,21sleep20-21swapper/207:06:112
66642201168,22sleep00-21swapper/007:05:290
1588621500,2sleep0733299cyclictest08:35:140
885921360,2sleep3733599cyclictest07:10:243
7334997715,60cyclictest11551-21kworker/2:208:55:332
7334997714,61cyclictest11329-21kworker/2:212:15:342
139391690,1ptp4l401ktimersoftd/310:24:413
7334996415,47cyclictest11551-21kworker/2:207:40:332
157222580,2sleep30-21swapper/310:50:163
157222580,2sleep30-21swapper/310:50:163
733499574,51cyclictest5470-21kworker/2:111:25:322
139391570,1ptp4l391rcuc/310:10:273
139391550,1ptp4l401ktimersoftd/309:10:003
139391530,8ptp4l401ktimersoftd/312:02:283
139391500,1ptp4l23424-1kworker/3:1H07:52:153
139391420,0ptp4l401ktimersoftd/310:48:443
139391420,0ptp4l401ktimersoftd/310:43:083
139391420,0ptp4l401ktimersoftd/310:39:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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