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2026-05-15 - 09:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri May 15, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138992204171,22sleep00-21swapper/019:06:250
139272202169,22sleep20-21swapper/219:06:472
139262201168,22sleep10-21swapper/119:06:461
139022201168,22sleep30-21swapper/319:06:283
1086321720,5sleep01447699cyclictest20:09:550
475021600,6sleep21447899cyclictest21:00:272
14476996932,7cyclictest9-21ksoftirqd/020:25:000
14476996932,7cyclictest9-21ksoftirqd/020:25:000
14477996524,7cyclictest25-21ksoftirqd/122:45:141
139391650,1ptp4l401ktimersoftd/321:13:353
14477996422,3cyclictest25-21ksoftirqd/122:25:171
14476996431,7cyclictest9-21ksoftirqd/000:00:100
14476996431,4cyclictest9-21ksoftirqd/000:35:000
14476996428,3cyclictest9-21ksoftirqd/020:20:010
14477996332,4cyclictest25-21ksoftirqd/120:15:121
14477996331,4cyclictest25-21ksoftirqd/100:30:201
14477996329,4cyclictest25-21ksoftirqd/122:15:001
14477996329,4cyclictest25-21ksoftirqd/122:14:591
14476996328,7cyclictest9-21ksoftirqd/019:35:260
14476996326,7cyclictest9-21ksoftirqd/022:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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