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2026-03-26 - 01:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Mar 25, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206171,23phc2sys0-21swapper/307:09:283
187822201168,22sleep00-21swapper/007:08:260
186192201169,21sleep20-21swapper/207:06:192
187332199166,22sleep10-21swapper/107:07:461
3070721560,6sleep01920499cyclictest12:00:250
1394918363,10phc2sys0-21swapper/307:10:013
139391620,1ptp4l401ktimersoftd/309:52:443
19205996027,4cyclictest25-21ksoftirqd/110:35:011
19205995729,5cyclictest25-21ksoftirqd/110:55:171
19205995623,3cyclictest25-21ksoftirqd/108:55:011
139391550,1ptp4l401ktimersoftd/308:55:203
139391550,1ptp4l401ktimersoftd/308:36:353
19205995321,4cyclictest25-21ksoftirqd/109:30:211
19205995224,4cyclictest25-21ksoftirqd/108:40:151
19205995120,8cyclictest25-21ksoftirqd/107:40:221
19205995120,4cyclictest25-21ksoftirqd/112:35:011
19205995117,4cyclictest25-21ksoftirqd/109:20:011
19205995023,7cyclictest25-21ksoftirqd/107:55:241
19205995021,7cyclictest25-21ksoftirqd/110:20:181
19205995021,4cyclictest25-21ksoftirqd/110:35:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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