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2026-01-26 - 07:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jan 26, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217882206173,22sleep10-21swapper/119:05:561
217882206173,22sleep10-21swapper/119:05:551
220592203169,23sleep20-21swapper/219:09:232
220592203169,23sleep20-21swapper/219:09:222
217902203169,22sleep30-21swapper/319:05:583
217902203169,22sleep30-21swapper/319:05:583
217822199166,22sleep00-21swapper/019:05:510
217822199166,22sleep00-21swapper/019:05:510
140362550,1sleep10-21swapper/121:05:211
25312520,1sleep20-21swapper/219:35:172
22403994337,3cyclictest24617-21ls19:15:011
139391420,0ptp4l401ktimersoftd/323:25:493
139391420,0ptp4l401ktimersoftd/320:55:223
139391400,8ptp4l401ktimersoftd/320:28:323
22405993932,4cyclictest10454-21cron23:15:003
22404993934,3cyclictest33-21ksoftirqd/220:10:192
22404993934,3cyclictest33-21ksoftirqd/200:30:012
22404993833,3cyclictest33-21ksoftirqd/221:05:012
22404993832,3cyclictest33-21ksoftirqd/219:15:132
22402993832,4cyclictest9-21ksoftirqd/020:40:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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