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2026-06-19 - 03:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Jun 19, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95582207173,22sleep20-21swapper/219:05:472
139491206172,23phc2sys0-21swapper/319:07:113
98352204171,22sleep00-21swapper/019:09:150
97542203171,21sleep10-21swapper/119:08:111
1394918863,16phc2sys0-21swapper/319:10:003
10184997426,4cyclictest25-21ksoftirqd/120:55:001
10184997127,7cyclictest25-21ksoftirqd/123:20:001
231882680,5sleep123190-21rt-features22:55:251
10184996627,10cyclictest25-21ksoftirqd/119:25:171
1018599651,23cyclictest22690-21latency_hist21:50:002
1018599650,24cyclictest17492-21awk23:50:232
10186996311,11cyclictest16400-21cut19:20:213
1018499615,9cyclictest25-21ksoftirqd/123:59:591
10184996119,10cyclictest25-21ksoftirqd/123:40:271
1018599608,20cyclictest112772chrt20:19:242
10184996027,7cyclictest25-21ksoftirqd/121:25:151
75932590,2sleep20-21swapper/220:10:182
1018699599,11cyclictest6718-21irqstats00:35:213
1018599591,22cyclictest15696-21awk22:40:222
10184995724,7cyclictest25-21ksoftirqd/119:15:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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