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2026-09-04 - 16:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Sep 04, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2651023100,49sleep10-21swapper/107:09:121
1960522200,4sleep219624-21sort07:08:542
3202022170,8sleep00-21swapper/007:08:180
139491205171,23phc2sys0-21swapper/307:08:583
682121410,4sleep22173999cyclictest11:55:162
234362880,2sleep20-21swapper/210:15:152
2173899695,23cyclictest30010-21cron10:30:001
2173899661,26cyclictest11284-21/usr/sbin/munin08:40:221
2173899611,26cyclictest22774-21chrt12:28:521
2173899590,3cyclictest27542-21chrt12:39:201
2173899590,26cyclictest11868-21df_inode07:35:121
2173899571,24cyclictest18913-21idleruntime12:20:181
2173899570,3cyclictest27893-21chrt08:09:461
2173899570,2cyclictest62102chrt07:24:061
2173899570,2cyclictest226922sleep110:12:331
2173899570,25cyclictest8372-21seq09:42:081
2173899561,25cyclictest6661-21dpkg07:25:001
2173899550,24cyclictest21372-21vmstat09:00:261
139391550,1ptp4l401ktimersoftd/309:14:083
2173899541,25cyclictest29696-21awk09:20:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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