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2026-04-13 - 17:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Apr 13, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491221155,23phc2sys0-21swapper/307:06:013
122932203169,23sleep00-21swapper/007:07:340
122122203171,21sleep10-21swapper/107:06:291
122952200168,21sleep20-21swapper/207:07:362
42112530,3sleep2321ktimersoftd/212:25:272
263982520,2sleep20-21swapper/208:45:112
139391500,1ptp4l401ktimersoftd/311:10:393
12943994715,7cyclictest25-21ksoftirqd/112:20:001
139391430,0ptp4l401ktimersoftd/311:23:153
1294399435,3cyclictest25-21ksoftirqd/110:50:211
12943994313,4cyclictest25-21ksoftirqd/107:10:151
139391420,0ptp4l401ktimersoftd/312:00:163
139391420,0ptp4l401ktimersoftd/309:07:273
1294399426,2cyclictest25-21ksoftirqd/109:50:161
12943994212,8cyclictest25-21ksoftirqd/110:05:281
12943994212,8cyclictest25-21ksoftirqd/110:05:271
12943994212,7cyclictest25-21ksoftirqd/108:30:201
12942994212,3cyclictest9-21ksoftirqd/008:20:000
139391410,0ptp4l401ktimersoftd/308:57:083
12945994135,3cyclictest41-21ksoftirqd/307:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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