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2026-07-15 - 07:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jul 15, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18752213168,33sleep30-21swapper/319:09:333
15932206173,22sleep20-21swapper/219:05:552
18002205172,22sleep00-21swapper/019:08:340
18012204171,22sleep10-21swapper/119:08:351
19102163125,13sleep20-21swapper/219:10:012
2241421580,6sleep3221299cyclictest22:05:283
220999640,4cyclictest26666-21cut00:30:130
142682610,1sleep00-21swapper/022:55:270
1394915538,10phc2sys0-21swapper/319:10:023
139391550,1ptp4l401ktimersoftd/322:56:503
139391550,1ptp4l401ktimersoftd/321:20:143
139391520,0ptp4l401ktimersoftd/320:03:103
2211994843,3cyclictest21030-21ls19:50:002
139391480,1ptp4l401ktimersoftd/323:22:073
139391480,1ptp4l401ktimersoftd/323:22:073
139391450,1ptp4l401ktimersoftd/321:46:263
2210994438,3cyclictest25-21ksoftirqd/122:00:001
2209994438,4cyclictest16569-21sh00:10:000
2210994238,2cyclictest25-21ksoftirqd/120:40:001
139391420,0ptp4l401ktimersoftd/322:10:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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