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2025-10-24 - 20:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Oct 24, 2025 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242862247201,36sleep10-21swapper/107:09:581
242542203169,22sleep00-21swapper/007:09:330
241922203170,22sleep20-21swapper/207:08:552
240282203168,23sleep30-21swapper/307:06:473
1752221860,4sleep12457999cyclictest10:15:161
383521620,1sleep00-21swapper/010:55:150
24580996413,12cyclictest23432-21tail10:25:282
24580996410,11cyclictest14906-21cstates10:10:152
24580996314,12cyclictest5402-21tail10:55:282
24580996310,16cyclictest20989-21if_enp4s011:30:212
24580996211,11cyclictest9673-21cat07:45:132
24580996210,10cyclictest30106-21cstates09:35:152
132691620,2getstats0-21swapper/309:15:163
2458099619,15cyclictest12922-21taskset11:14:022
24580996111,17cyclictest25635-21cat10:30:272
24580996111,17cyclictest25635-21cat10:30:272
24580996012,15cyclictest27500-21sensors08:20:262
24580996011,11cyclictest610-21vmstat10:45:282
2458199590,3cyclictest212612chrt10:21:443
2458199590,2cyclictest165222sleep312:29:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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