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2026-01-22 - 08:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jan 22, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,23phc2sys0-21swapper/319:09:523
59422204171,22sleep10-21swapper/119:05:021
78842203169,23sleep20-21swapper/219:07:252
79252200167,22sleep00-21swapper/019:07:550
97702530,1sleep00-21swapper/019:10:230
8382995043,4cyclictest23877-21dump-pmu-power20:50:003
8380994842,3cyclictest23007-21perf00:10:001
838199441,40cyclictest22418-21cron19:40:002
8381994338,3cyclictest17344-21sshd19:25:482
139391430,0ptp4l401ktimersoftd/323:38:403
808724233,3sleep10-21swapper/119:10:011
838099400,2cyclictest121rcu_preempt20:10:011
8382993929,8cyclictest139391ptp4l22:59:153
8379993934,3cyclictest9-21ksoftirqd/023:10:010
8381993833,3cyclictest33-21ksoftirqd/200:00:002
8380993834,2cyclictest25-21ksoftirqd/120:20:001
8380993833,3cyclictest25-21ksoftirqd/122:20:001
8380993833,3cyclictest25-21ksoftirqd/119:20:001
8380993833,3cyclictest25-21ksoftirqd/100:25:001
8379993833,3cyclictest9-21ksoftirqd/000:29:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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