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2026-02-09 - 01:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Feb 08, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227199,19phc2sys0-21swapper/307:06:583
28752202169,22sleep10-21swapper/107:09:101
28212201168,22sleep20-21swapper/207:08:262
26932201168,22sleep00-21swapper/007:06:510
644021570,7sleep2323799cyclictest07:15:192
3236996625,4cyclictest25-21ksoftirqd/111:15:141
3236996425,10cyclictest25-21ksoftirqd/111:05:251
3236996423,10cyclictest25-21ksoftirqd/110:10:261
3236996221,10cyclictest25-21ksoftirqd/111:00:191
3236996120,9cyclictest25-21ksoftirqd/107:30:001
3235996131,4cyclictest9-21ksoftirqd/007:20:180
3235996130,4cyclictest9-21ksoftirqd/007:15:190
3235996126,7cyclictest9-21ksoftirqd/011:30:010
3235996032,3cyclictest9-21ksoftirqd/009:45:220
3236995922,9cyclictest25-21ksoftirqd/110:00:171
3236995922,9cyclictest25-21ksoftirqd/110:00:171
3236995922,10cyclictest25-21ksoftirqd/112:25:241
3235995930,3cyclictest9-21ksoftirqd/011:40:190
3235995928,9cyclictest9-21ksoftirqd/012:39:590
3236995828,10cyclictest25-21ksoftirqd/107:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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