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2026-02-16 - 23:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Feb 16, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89732224162,50sleep00-21swapper/007:07:290
91562208173,23sleep20-21swapper/207:09:482
139491207173,23phc2sys0-21swapper/307:09:013
89492202168,23sleep10-21swapper/107:07:101
3175921540,5sleep3947099cyclictest12:20:383
2481221410,7sleep2946999cyclictest08:45:272
34862580,2sleep10-21swapper/109:10:171
139391560,1ptp4l391rcuc/311:10:163
308772500,1sleep30-21swapper/307:54:413
947099473,42cyclictest6885-21idleruntime-cro12:39:593
9470994532,10cyclictest41-21ksoftirqd/309:55:113
946899440,2cyclictest0-21swapper/112:11:231
263412440,27sleep233-21ksoftirqd/212:10:222
946899430,1cyclictest0-21swapper/112:01:031
9468994136,3cyclictest18024-21cron08:35:001
139391410,0ptp4l401ktimersoftd/311:35:223
139391400,1ptp4l401ktimersoftd/308:42:363
139391400,0ptp4l401ktimersoftd/312:15:183
139391400,0ptp4l401ktimersoftd/309:18:183
9470993933,3cyclictest3770-21grep09:10:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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