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2026-01-06 - 23:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jan 06, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66652204171,22sleep10-21swapper/107:05:101
139491203170,22phc2sys0-21swapper/307:08:103
84742202169,22sleep20-21swapper/207:05:552
84672195163,22sleep00-21swapper/007:05:490
1324621610,6sleep3922899cyclictest10:40:133
139391810,1ptp4l19355-21hddtemp_smartct07:30:153
9227996911,19cyclictest4304-21date09:15:002
922799581,53cyclictest19605-21cron08:40:002
139391570,1ptp4l401ktimersoftd/309:00:133
9227995610,22cyclictest17746-21/usr/sbin/munin10:50:232
922799555,21cyclictest1870-21taskset11:23:002
922799540,2cyclictest158922sleep207:20:512
922799510,4cyclictest10043-21chrt10:30:542
226392510,4sleep09-21ksoftirqd/012:05:230
922799457,24cyclictest4133-21seq11:25:522
139391450,1ptp4l401ktimersoftd/309:43:523
139391440,0ptp4l401ktimersoftd/308:40:183
9227994237,3cyclictest17524-21sh10:50:002
922799417,22cyclictest18835-21/usr/sbin/munin07:30:262
922799415,23cyclictest6205-21seq09:15:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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