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2026-03-21 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Mar 21, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181822250,17sleep10-21swapper/119:05:271
139491220170,40phc2sys0-21swapper/319:08:363
21482213169,19sleep20-21swapper/219:08:592
21762207143,21sleep00-21swapper/019:09:210
139391690,1ptp4l401ktimersoftd/323:35:293
119192680,3sleep011923-21latency_hist00:00:010
41722670,2sleep30-21swapper/323:40:253
41722670,2sleep30-21swapper/323:40:253
55682570,2sleep30-21swapper/319:15:163
31312570,5sleep3256099cyclictest21:25:143
273752570,3sleep10-21swapper/100:30:171
18362570,6sleep11837-21wc20:15:161
172672560,2sleep20-21swapper/223:00:242
124662540,2sleep30-21swapper/321:45:133
204522530,3sleep3391rcuc/323:10:003
205222510,4sleep2255999cyclictest00:15:182
2558994639,4cyclictest9481-21dump-pmu-power19:25:011
2558994540,3cyclictest7239-21basename21:34:591
139391440,1ptp4l3008-21ls20:15:263
139391440,0ptp4l401ktimersoftd/322:56:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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