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2025-12-08 - 05:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Dec 08, 2025 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1216723890,10sleep125-21ksoftirqd/119:07:021
1216723890,10sleep125-21ksoftirqd/119:07:021
137191205170,23phc2sys0-21swapper/319:09:073
137191205170,23phc2sys0-21swapper/319:09:073
123742204170,22sleep20-21swapper/219:09:382
123742204170,22sleep20-21swapper/219:09:382
121982202168,22sleep00-21swapper/019:07:190
121982202168,22sleep00-21swapper/019:07:190
2233921410,7sleep21269899cyclictest23:59:452
136991800,1ptp4l8193-21fschecks_count21:15:163
136991720,1ptp4l28464-21fschecks_count20:50:183
12698996320,6cyclictest33-21ksoftirqd/223:35:122
136991620,1ptp4l401ktimersoftd/321:10:573
223812610,6sleep11269799cyclictest00:00:001
136991540,39ptp4l0-21swapper/319:10:013
136991540,1ptp4l391rcuc/320:45:083
12698995422,8cyclictest33-21ksoftirqd/222:49:042
12698995418,5cyclictest33-21ksoftirqd/223:35:002
1269899539,41cyclictest25399-21kworker/2:122:20:272
12698995320,3cyclictest33-21ksoftirqd/221:28:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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