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2026-06-22 - 05:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jun 22, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491237169,23phc2sys0-21swapper/319:08:563
82532206141,21sleep10-21swapper/119:07:181
81362206172,22sleep00-21swapper/019:05:530
63292205172,22sleep20-21swapper/219:05:072
8751996511,19cyclictest13294-21latency_hist19:20:000
8754995810,46cyclictest17614-21kworker/3:023:09:133
8753995414,7cyclictest33-21ksoftirqd/221:20:002
8754995213,37cyclictest23135-21kworker/3:219:52:333
8754995213,37cyclictest23135-21kworker/3:219:52:333
8753995119,4cyclictest33-21ksoftirqd/220:00:012
173062500,3sleep117308-21timerandwakeup23:55:261
139391490,21ptp4l875499cyclictest22:25:133
875399488,10cyclictest33-21ksoftirqd/220:30:202
198212470,2sleep20-21swapper/222:55:132
198212470,2sleep20-21swapper/222:55:132
875399467,5cyclictest33-21ksoftirqd/221:40:282
8753994619,3cyclictest33-21ksoftirqd/219:40:222
8753994538,4cyclictest22834-21cron00:10:012
8753994515,6cyclictest33-21ksoftirqd/200:35:142
8753994515,4cyclictest33-21ksoftirqd/220:40:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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