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2026-08-26 - 20:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Aug 26, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491229165,52phc2sys0-21swapper/307:05:403
182162206173,22sleep20-21swapper/207:08:152
180432204171,22sleep10-21swapper/107:06:041
180522203171,22sleep00-21swapper/007:06:120
167221690,21sleep21864799cyclictest09:55:222
788821550,6sleep31864899cyclictest10:10:123
57898930,71rtkit-daemon0-21swapper/007:10:010
1864799661,63cyclictest28655-21kworker/2:211:15:332
1835326535,22sleep30-21swapper/307:10:013
1864599591,22cyclictest4240-21/usr/sbin/munin07:45:190
1864599590,20cyclictest2726-21latency08:50:200
1864599570,19cyclictest20514-21awk11:40:280
309572510,2sleep00-21swapper/010:55:260
1864799490,46cyclictest12993-21tr11:25:242
308712470,2sleep20-21swapper/208:40:262
139391470,1ptp4l0-21swapper/311:05:423
18646994617,27cyclictest0-21swapper/107:11:231
18646994540,3cyclictest25692-21sh11:55:001
18646994214,27cyclictest0-21swapper/110:40:131
1864699418,3cyclictest26487-21seq10:47:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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