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2026-06-08 - 20:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jun 08, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1315422730,50sleep30-21swapper/307:09:213
1315422730,50sleep30-21swapper/307:09:213
663822350,7sleep26633-21sort07:07:402
663822350,7sleep26633-21sort07:07:402
2801122090,6sleep128012-21rm07:09:351
2801122090,6sleep128012-21rm07:09:351
45182205172,22sleep00-21swapper/007:05:500
45182205172,22sleep00-21swapper/007:05:500
1914521520,5sleep01871399cyclictest08:50:030
1682021500,6sleep01871399cyclictest10:59:120
1682021500,6sleep01871399cyclictest10:59:120
926821440,8sleep01871399cyclictest09:35:160
231022780,2sleep20-21swapper/207:50:162
18714997132,7cyclictest25-21ksoftirqd/107:13:081
139672670,2sleep30-21swapper/307:30:203
77992620,6sleep07736-21sh07:10:560
260612620,3sleep126066-21sh09:05:001
273932610,2sleep30-21swapper/307:12:093
318422580,2sleep00-21swapper/009:15:140
18714995723,8cyclictest25-21ksoftirqd/109:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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