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2026-04-08 - 20:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Apr 08, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179412227163,21sleep10-21swapper/107:09:571
139491207173,22phc2sys0-21swapper/307:07:493
177662204171,22sleep20-21swapper/207:07:422
177692201168,22sleep00-21swapper/007:07:440
1040721730,7sleep11823799cyclictest11:20:291
576221180,5sleep31823999cyclictest10:05:173
18236996426,4cyclictest9-21ksoftirqd/011:20:000
95992620,5sleep21823899cyclictest08:00:002
160702620,3sleep316073-21proc_pri10:25:233
18236996028,4cyclictest9-21ksoftirqd/008:30:260
139391600,1ptp4l401ktimersoftd/308:10:023
18236995928,4cyclictest9-21ksoftirqd/007:55:150
18238995825,5cyclictest33-21ksoftirqd/210:15:012
18238995620,12cyclictest33-21ksoftirqd/207:29:592
18236995528,6cyclictest9-21ksoftirqd/010:02:360
18236995526,4cyclictest9-21ksoftirqd/009:40:240
18236995526,3cyclictest9-21ksoftirqd/010:15:130
18236995523,4cyclictest9-21ksoftirqd/010:25:150
18238995424,9cyclictest33-21ksoftirqd/211:05:182
18238995424,9cyclictest33-21ksoftirqd/211:05:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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