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2026-02-15 - 14:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Feb 15, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491226163,51phc2sys0-21swapper/319:07:563
255692202169,22sleep20-21swapper/219:07:202
254412201168,22sleep00-21swapper/019:05:450
255102195164,21sleep10-21swapper/119:06:391
2625621610,7sleep12606899cyclictest22:30:211
372421540,3sleep22606999cyclictest21:45:132
139391680,1ptp4l401ktimersoftd/322:57:233
139391630,1ptp4l401ktimersoftd/320:13:333
189792590,5sleep22606999cyclictest00:30:172
5852550,2sleep10-21swapper/119:25:001
157132540,3sleep22606999cyclictest22:10:122
253602530,1sleep20-21swapper/220:15:152
144662530,2sleep00-21swapper/023:15:000
1394915335,10phc2sys0-21swapper/319:10:013
57452490,2sleep10-21swapper/120:40:171
139391420,0ptp4l401ktimersoftd/320:00:413
26067994129,4cyclictest9-21ksoftirqd/021:27:380
26070994035,3cyclictest41-21ksoftirqd/322:30:003
139391400,1ptp4l401ktimersoftd/319:18:073
139391400,0ptp4l401ktimersoftd/320:25:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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