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2026-05-25 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon May 25, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,22phc2sys0-21swapper/319:08:413
156592204171,22sleep10-21swapper/119:05:591
156302204169,23sleep20-21swapper/219:05:362
158572203170,22sleep00-21swapper/019:08:270
2098521590,3sleep11626999cyclictest20:25:221
1230021380,5sleep11626999cyclictest23:30:181
139391730,1ptp4l391rcuc/323:55:183
16269996713,52cyclictest0-21swapper/100:35:531
63642650,7sleep21627099cyclictest19:55:222
263082610,5sleep10-21swapper/120:35:291
1627199618,6cyclictest3867-21awk20:59:593
134391610,6getstats1627199cyclictest20:22:213
168112580,3sleep2311rcuc/219:10:182
1627199578,7cyclictest6661-21tr21:05:143
1627199571,16cyclictest20973-21sort22:40:193
1627199569,9cyclictest11054-21sed20:05:203
1627199567,7cyclictest6554-21latency_hist23:20:013
1627199564,17cyclictest8789-21iwlist00:30:163
1627199561,16cyclictest19476-21irqrtprio19:15:193
1627199561,12cyclictest13845-21cat23:34:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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