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2025-12-27 - 18:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Dec 27, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130132205172,22sleep10-21swapper/107:08:451
130132205172,22sleep10-21swapper/107:08:451
130122203170,22sleep00-21swapper/007:08:440
130122203170,22sleep00-21swapper/007:08:440
130092198166,21sleep20-21swapper/207:08:422
130092198166,21sleep20-21swapper/207:08:422
128612197163,22sleep30-21swapper/307:06:463
128612197163,22sleep30-21swapper/307:06:463
1939321380,5sleep31341299cyclictest09:35:253
13412996129,3cyclictest41-21ksoftirqd/311:35:013
13412996126,4cyclictest41-21ksoftirqd/309:45:013
13412996029,4cyclictest41-21ksoftirqd/308:35:173
13412996028,7cyclictest41-21ksoftirqd/310:00:173
13412996028,4cyclictest41-21ksoftirqd/311:40:133
13412996028,4cyclictest41-21ksoftirqd/311:40:133
13412996028,4cyclictest41-21ksoftirqd/311:10:173
13412996027,6cyclictest41-21ksoftirqd/307:20:263
13412996024,4cyclictest41-21ksoftirqd/309:15:163
13412995929,8cyclictest41-21ksoftirqd/312:00:243
13412995929,7cyclictest41-21ksoftirqd/309:25:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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