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2026-07-23 - 10:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 23, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176582218157,51sleep00-21swapper/019:08:080
176982204170,23sleep30-21swapper/319:08:383
176972204171,22sleep20-21swapper/219:08:382
176642202168,22sleep10-21swapper/119:08:121
1780428362,11sleep00-21swapper/019:10:010
238662590,2sleep10-21swapper/100:00:011
156182570,2sleep00-21swapper/020:10:220
18274995331,2cyclictest9-21ksoftirqd/000:20:180
139391530,1ptp4l401ktimersoftd/321:26:183
1827699501,46cyclictest8305-21awk23:25:231
18274995015,6cyclictest9-21ksoftirqd/020:59:590
1827699470,45cyclictest0-21swapper/120:58:341
18274994718,7cyclictest9-21ksoftirqd/019:25:160
18274994718,6cyclictest9-21ksoftirqd/020:30:200
18278994628,15cyclictest33-21ksoftirqd/219:55:002
18274994616,6cyclictest9-21ksoftirqd/023:30:260
18278994531,12cyclictest33-21ksoftirqd/222:40:002
1827499459,6cyclictest9-21ksoftirqd/020:40:270
1827499459,5cyclictest9-21ksoftirqd/020:05:280
18274994515,4cyclictest9-21ksoftirqd/023:13:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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