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2026-07-29 - 16:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Jul 29, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208173,23phc2sys0-21swapper/307:09:223
101622205172,22sleep00-21swapper/007:05:520
103032204170,23sleep20-21swapper/207:07:422
102302203169,22sleep10-21swapper/107:06:461
2562521730,7sleep21087899cyclictest11:00:262
2206421400,6sleep21087899cyclictest07:30:242
10874997229,5cyclictest9-21ksoftirqd/007:30:010
41482710,5sleep11087699cyclictest10:15:251
217922580,4sleep0101ktimersoftd/012:00:250
139391570,1ptp4l401ktimersoftd/311:08:063
10874995719,7cyclictest9-21ksoftirqd/011:20:200
139391560,1ptp4l401ktimersoftd/308:48:053
10879995621,5cyclictest41-21ksoftirqd/311:40:253
10874995626,4cyclictest9-21ksoftirqd/010:45:220
10874995426,7cyclictest9-21ksoftirqd/007:15:230
10874995424,8cyclictest9-21ksoftirqd/010:00:240
10874995424,4cyclictest9-21ksoftirqd/008:25:240
10874995422,4cyclictest9-21ksoftirqd/007:55:280
10874995323,8cyclictest9-21ksoftirqd/010:55:210
10874995322,4cyclictest9-21ksoftirqd/008:05:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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