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2026-08-31 - 16:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 31, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491252197,45phc2sys0-21swapper/307:06:593
199832203170,22sleep10-21swapper/107:05:521
200662202169,22sleep20-21swapper/207:06:562
201162201168,22sleep00-21swapper/007:07:350
101952630,2sleep0111rcuc/007:55:160
139391620,1ptp4l401ktimersoftd/312:25:003
310432560,6sleep32060399cyclictest09:45:203
20603994710,5cyclictest41-21ksoftirqd/311:00:003
139391440,0ptp4l401ktimersoftd/307:56:343
139391430,1ptp4l401ktimersoftd/308:36:593
20603994237,3cyclictest41-21ksoftirqd/308:20:013
20603994237,3cyclictest41-21ksoftirqd/308:20:013
20602994228,12cyclictest33-21ksoftirqd/210:25:012
139391420,0ptp4l401ktimersoftd/311:24:573
139391420,0ptp4l401ktimersoftd/311:24:573
139391420,0ptp4l401ktimersoftd/309:03:133
139391420,0ptp4l401ktimersoftd/307:35:203
139391410,0ptp4l401ktimersoftd/309:34:253
2060399406,7cyclictest41-21ksoftirqd/309:00:013
2060399405,3cyclictest121rcu_preempt09:10:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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