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2025-11-15 - 12:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Nov 15, 2025 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
273342234167,22sleep20-21swapper/219:08:382
273282203170,22sleep10-21swapper/119:08:331
137191203169,22phc2sys0-21swapper/319:05:023
271942198166,22sleep00-21swapper/019:06:470
737921500,6sleep32773699cyclictest21:45:283
1673321210,5sleep02773399cyclictest22:05:230
27735996620,5cyclictest33-21ksoftirqd/221:05:002
27735996426,8cyclictest33-21ksoftirqd/220:39:592
72702610,4sleep07267-21basename22:55:010
136991570,1ptp4l401ktimersoftd/323:47:103
27733995647,3cyclictest9-21ksoftirqd/000:40:000
2773599549,43cyclictest5994-21kworker/2:121:35:272
27735995217,8cyclictest33-21ksoftirqd/222:40:012
136991490,1ptp4l401ktimersoftd/321:08:273
278322480,7sleep2321ktimersoftd/219:10:132
27736994843,2cyclictest18513-21wc21:05:013
2773399448,7cyclictest9-21ksoftirqd/019:35:000
136991440,0ptp4l401ktimersoftd/320:22:573
27733994314,4cyclictest9-21ksoftirqd/022:29:590
2773599429,7cyclictest33-21ksoftirqd/223:50:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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