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2026-08-04 - 01:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Aug 03, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278222233169,21sleep30-21swapper/307:09:483
257082208175,22sleep00-21swapper/007:05:070
277002204172,21sleep10-21swapper/107:08:171
275362202169,22sleep20-21swapper/207:06:092
139391700,1ptp4l391rcuc/307:55:143
120712680,7sleep22813599cyclictest08:50:192
134391600,2getstats0-21swapper/308:55:383
139391580,1ptp4l401ktimersoftd/310:10:393
139391580,1ptp4l401ktimersoftd/310:10:393
144022550,3sleep02813399cyclictest11:10:130
208672480,2sleep30-21swapper/310:15:173
28135994525,17cyclictest33-21ksoftirqd/211:10:002
28134994539,3cyclictest8264-21dump-pmu-power09:50:011
57898430,8rtkit-daemon0-21swapper/012:10:380
28133994136,3cyclictest9-21ksoftirqd/010:00:000
139391410,0ptp4l401ktimersoftd/308:30:003
139391400,0ptp4l401ktimersoftd/309:37:153
28136993933,4cyclictest41-21ksoftirqd/310:40:013
28134993934,3cyclictest7979-21wc12:05:001
139391390,0ptp4l401ktimersoftd/307:30:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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