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2026-02-16 - 02:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Feb 15, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147782204171,22sleep00-21swapper/007:05:080
168872203169,23sleep20-21swapper/207:09:362
168832201167,22sleep30-21swapper/307:09:323
166842201169,21sleep10-21swapper/107:07:051
1691928263,10sleep30-21swapper/307:10:003
32862660,4sleep13289-21sort11:10:141
139391630,1ptp4l401ktimersoftd/310:33:283
225602580,2sleep01721199cyclictest07:20:160
139391560,1ptp4l401ktimersoftd/308:20:263
39522550,1sleep30-21swapper/312:20:133
139391550,1ptp4l401ktimersoftd/307:54:153
17213995422,7cyclictest33-21ksoftirqd/208:05:002
17213995413,2cyclictest121rcu_preempt10:45:002
17213995330,10cyclictest33-21ksoftirqd/209:10:242
26282520,2sleep20-21swapper/207:45:212
17213995221,7cyclictest33-21ksoftirqd/211:35:002
17213995219,5cyclictest33-21ksoftirqd/207:25:002
17213995017,4cyclictest33-21ksoftirqd/207:10:152
1721399501,45cyclictest14517-21cat09:20:002
139391500,0ptp4l401ktimersoftd/312:35:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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