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2026-09-07 - 19:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Sep 07, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230164,22phc2sys0-21swapper/307:07:203
199912203170,22sleep00-21swapper/007:05:510
202672202170,21sleep10-21swapper/107:09:251
202882200167,22sleep20-21swapper/207:09:432
625621810,5sleep32061199cyclictest11:10:173
11992550,3sleep10-21swapper/108:45:121
291102490,2sleep30-21swapper/307:25:243
57898480,1rtkit-daemon0-21swapper/211:59:132
20611994627,16cyclictest41-21ksoftirqd/311:38:573
20609994337,4cyclictest1317-21runrttasks07:29:261
139391430,0ptp4l401ktimersoftd/310:55:203
139391420,0ptp4l401ktimersoftd/311:24:113
139391420,0ptp4l401ktimersoftd/309:40:223
20609994034,3cyclictest25-21ksoftirqd/107:19:591
139391400,0ptp4l401ktimersoftd/309:50:203
139391400,0ptp4l401ktimersoftd/309:16:413
57898380,21rtkit-daemon26840-21if_enp1s010:45:172
139391380,1ptp4l391rcuc/308:45:163
134391380,1getstats0-21swapper/312:30:273
20611993714,21cyclictest3507-21/usr/sbin/munin08:50:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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