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2026-03-14 - 16:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Mar 14, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122852204170,23sleep30-21swapper/307:08:573
120712204172,21sleep20-21swapper/207:06:112
122252201167,23sleep00-21swapper/007:08:100
120652201168,22sleep10-21swapper/107:06:061
2007621660,7sleep11266899cyclictest09:40:141
805921500,5sleep01266799cyclictest11:30:120
125962700,6sleep012590-21phc2sys10:30:220
139391650,1ptp4l401ktimersoftd/311:50:153
139391600,0ptp4l401ktimersoftd/308:59:253
64482550,4sleep30-21swapper/309:10:183
139391530,1ptp4l401ktimersoftd/312:06:183
139391520,0ptp4l401ktimersoftd/310:33:253
139391440,0ptp4l401ktimersoftd/307:24:503
12669994337,4cyclictest8775-21cron10:25:002
12669993934,3cyclictest33-21ksoftirqd/210:35:002
12670993833,3cyclictest41-21ksoftirqd/309:20:143
12669993831,4cyclictest33-21ksoftirqd/208:24:092
12668993731,4cyclictest25-21ksoftirqd/111:40:121
12668993731,4cyclictest25-21ksoftirqd/111:32:291
12667993733,2cyclictest9-21ksoftirqd/008:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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