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2026-04-22 - 16:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Apr 22, 2026 12:46:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491204170,22phc2sys0-21swapper/307:05:023
20502202168,23sleep20-21swapper/207:08:282
18262201168,22sleep10-21swapper/107:05:451
20982199166,22sleep00-21swapper/007:09:070
1018921500,8sleep0246599cyclictest11:55:160
217028163,10sleep20-21swapper/207:10:012
2466996411,51cyclictest0-21swapper/107:11:331
139391610,1ptp4l401ktimersoftd/308:20:583
139391610,1ptp4l401ktimersoftd/308:20:573
139391600,1ptp4l14958-21ls08:40:263
2466995923,7cyclictest25-21ksoftirqd/109:24:351
2466995923,7cyclictest25-21ksoftirqd/109:24:351
2466995922,4cyclictest25-21ksoftirqd/109:30:181
2466995921,4cyclictest25-21ksoftirqd/111:08:451
2466995725,7cyclictest25-21ksoftirqd/110:50:251
2466995725,7cyclictest25-21ksoftirqd/110:50:251
2466995723,8cyclictest25-21ksoftirqd/111:35:011
2466995625,7cyclictest25-21ksoftirqd/107:30:011
2466995624,11cyclictest25-21ksoftirqd/109:25:131
2466995622,6cyclictest25-21ksoftirqd/109:43:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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