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2025-12-16 - 21:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Dec 16, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305862212179,22sleep30-21swapper/307:08:513
305152212180,22sleep00-21swapper/007:07:570
305112210176,22sleep10-21swapper/107:07:531
306332209177,21sleep20-21swapper/207:09:242
2609521180,4sleep33097899cyclictest09:15:433
1567221180,2sleep20-21swapper/208:50:552
57898970,77rtkit-daemon0-21swapper/107:10:001
57898970,77rtkit-daemon0-21swapper/107:10:001
134491620,1getstats0-21swapper/307:14:223
134491620,1getstats0-21swapper/307:14:223
57898610,2rtkit-daemon0-21swapper/008:50:480
7362550,2sleep00-21swapper/010:35:510
278012520,3sleep1231rcuc/110:25:491
139391520,1ptp4l401ktimersoftd/308:40:283
312932510,2sleep2311rcuc/211:40:442
139391510,0ptp4l401ktimersoftd/308:05:533
139391500,0ptp4l401ktimersoftd/310:05:443
45402480,4sleep233-21ksoftirqd/207:20:502
30978994817,6cyclictest41-21ksoftirqd/309:00:563
139391440,0ptp4l401ktimersoftd/311:00:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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