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2026-07-30 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jul 30, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491235168,22phc2sys0-21swapper/307:08:213
9342205172,22sleep00-21swapper/007:08:390
9102203170,22sleep20-21swapper/207:08:212
8272202169,22sleep10-21swapper/107:07:151
1379521670,2sleep30-21swapper/309:45:193
134391650,8getstats156499cyclictest11:14:573
1563995525,4cyclictest33-21ksoftirqd/208:51:382
139391520,1ptp4l401ktimersoftd/310:56:433
1564994742,3cyclictest31965-21dump-pmu-power12:40:003
1563994438,3cyclictest21013-21fschecks_count10:00:132
1562994338,2cyclictest25-21ksoftirqd/108:51:511
1562994238,3cyclictest25-21ksoftirqd/112:00:011
156199421,38cyclictest2551-21cron08:20:000
1563994036,3cyclictest33-21ksoftirqd/211:20:002
1563994036,3cyclictest33-21ksoftirqd/211:20:002
1562994035,3cyclictest25-21ksoftirqd/111:30:001
1562994035,3cyclictest25-21ksoftirqd/110:40:001
1564993934,3cyclictest41-21ksoftirqd/309:23:493
1562993933,3cyclictest25-21ksoftirqd/108:05:001
139391390,1ptp4l401ktimersoftd/309:30:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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