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2026-08-07 - 00:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 06, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491206172,23phc2sys0-21swapper/307:08:153
61692202169,22sleep10-21swapper/107:07:351
60322202168,23sleep20-21swapper/207:05:462
60302202169,22sleep00-21swapper/007:05:440
63682138114,13sleep30-21swapper/307:10:023
6663996226,4cyclictest41-21ksoftirqd/308:40:003
6663996226,4cyclictest41-21ksoftirqd/308:40:003
318712620,4sleep0101ktimersoftd/010:15:230
139391610,0ptp4l391rcuc/308:43:523
6663995716,5cyclictest41-21ksoftirqd/308:50:243
139391540,1ptp4l401ktimersoftd/308:56:173
139391540,0ptp4l401ktimersoftd/307:55:503
139391530,1ptp4l401ktimersoftd/309:19:273
666099523,7cyclictest5502-21ps09:20:230
666099523,7cyclictest5502-21ps09:20:230
6663995023,7cyclictest41-21ksoftirqd/310:45:173
6663995019,7cyclictest41-21ksoftirqd/309:25:003
6663995019,7cyclictest41-21ksoftirqd/309:25:003
6663995019,4cyclictest41-21ksoftirqd/310:55:003
6663995017,4cyclictest41-21ksoftirqd/312:40:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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