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2026-08-04 - 18:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Aug 04, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
47632207174,22sleep00-21swapper/007:08:530
139491206173,22phc2sys0-21swapper/307:06:333
46022203169,23sleep20-21swapper/207:06:542
46952202169,22sleep10-21swapper/107:08:041
1384721430,3sleep2514699cyclictest07:25:272
514799661,21cyclictest449-21dbus-daemon07:35:253
514799661,19cyclictest449-21dbus-daemon10:45:243
514799660,26cyclictest19966-21awk08:45:233
5146996629,7cyclictest33-21ksoftirqd/207:45:212
5146996532,9cyclictest33-21ksoftirqd/210:00:182
5146996532,9cyclictest33-21ksoftirqd/210:00:182
5147996410,18cyclictest21348-21smartctl08:50:173
514799640,22cyclictest10495-21/usr/sbin/munin11:50:153
5146996433,7cyclictest33-21ksoftirqd/212:10:012
5146996433,6cyclictest33-21ksoftirqd/209:55:202
5146996432,6cyclictest33-21ksoftirqd/211:00:002
5146996431,5cyclictest33-21ksoftirqd/209:15:012
514799630,19cyclictest8233-21hddtemp_smartct11:45:153
5146996331,6cyclictest33-21ksoftirqd/210:35:272
5146996331,10cyclictest33-21ksoftirqd/210:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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