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2026-07-27 - 02:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun Jul 26, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
364122550,20sleep30-21swapper/307:05:153
52162208164,33sleep20-21swapper/207:06:022
53492206172,22sleep10-21swapper/107:07:471
55012205172,22sleep00-21swapper/007:09:380
1353421780,7sleep0596299cyclictest07:25:150
1903921680,1sleep00-21swapper/007:35:220
1734421410,3sleep1596399cyclictest07:30:241
552928263,10sleep20-21swapper/207:10:002
178652630,4sleep317869-21ptp4l08:40:233
139391570,1ptp4l401ktimersoftd/312:37:083
139391560,1ptp4l401ktimersoftd/312:22:413
48012530,2sleep30-21swapper/309:20:233
156912510,2sleep20-21swapper/212:00:002
61532500,2sleep20-21swapper/210:30:232
139391450,0ptp4l401ktimersoftd/310:30:203
139391440,1ptp4l401ktimersoftd/309:08:113
139391440,0ptp4l401ktimersoftd/312:18:243
139391440,0ptp4l401ktimersoftd/308:00:203
5964994338,3cyclictest28384-21cron09:05:002
139391430,0ptp4l401ktimersoftd/312:00:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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