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2026-06-12 - 01:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Jun 11, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44942227163,22sleep00-21swapper/007:08:430
43462216152,21sleep10-21swapper/107:06:461
139491204169,23phc2sys0-21swapper/307:09:263
44042202168,22sleep20-21swapper/207:07:332
1619121190,2sleep00-21swapper/009:45:230
1394918561,15phc2sys0-21swapper/307:10:013
4894996428,7cyclictest9-21ksoftirqd/011:20:000
4894996428,7cyclictest9-21ksoftirqd/011:20:000
139391640,1ptp4l391rcuc/308:25:253
4894996226,7cyclictest9-21ksoftirqd/009:55:010
4894996225,8cyclictest9-21ksoftirqd/010:45:010
101192620,2sleep10-21swapper/109:35:131
489799614,17cyclictest19670-21unixbench_singl08:45:263
4894996127,6cyclictest9-21ksoftirqd/011:40:200
4894995924,6cyclictest9-21ksoftirqd/011:15:000
4894995923,5cyclictest9-21ksoftirqd/007:50:010
4894995923,5cyclictest9-21ksoftirqd/007:50:000
4894995921,6cyclictest9-21ksoftirqd/009:25:000
139391590,1ptp4l391rcuc/307:35:103
489799582,11cyclictest139491phc2sys11:55:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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