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2026-04-14 - 19:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Apr 14, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
225342205172,22sleep30-21swapper/307:07:313
225082204172,21sleep20-21swapper/207:07:092
225072200167,22sleep10-21swapper/107:07:091
225062199167,22sleep00-21swapper/007:07:070
95932650,4sleep29588-21cron10:05:012
23028996329,6cyclictest33-21ksoftirqd/211:05:142
264322620,3sleep00-21swapper/011:45:190
83792600,4sleep38372-21turbostat11:10:003
139391600,7ptp4l401ktimersoftd/307:55:433
139391590,8ptp4l401ktimersoftd/311:57:413
23028995822,6cyclictest33-21ksoftirqd/209:55:202
23028995727,5cyclictest33-21ksoftirqd/207:30:192
23028995726,5cyclictest33-21ksoftirqd/212:05:002
23028995626,5cyclictest33-21ksoftirqd/212:30:042
23028995621,8cyclictest33-21ksoftirqd/211:33:412
23028995620,8cyclictest33-21ksoftirqd/210:54:022
23028995620,5cyclictest33-21ksoftirqd/211:45:222
23028995522,7cyclictest33-21ksoftirqd/211:15:252
23028995421,8cyclictest33-21ksoftirqd/208:09:552
23028995419,10cyclictest33-21ksoftirqd/207:45:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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