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2026-05-17 - 10:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sun May 17, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
104182215167,37sleep20-21swapper/219:07:592
139491206173,22phc2sys0-21swapper/319:05:493
104472202169,22sleep10-21swapper/119:08:231
105032201168,22sleep00-21swapper/019:09:060
2558421770,6sleep11086699cyclictest19:40:151
2896021630,7sleep01086599cyclictest00:15:250
57898910,70rtkit-daemon0-21swapper/219:10:012
1086599552,10cyclictest3942-21sed23:25:140
1086599540,15cyclictest1266-21mailstats19:55:230
225562520,2sleep00-21swapper/019:35:000
225562520,2sleep00-21swapper/019:35:000
253142510,1sleep30-21swapper/320:45:243
139391510,1ptp4l401ktimersoftd/321:10:183
10865995146,3cyclictest923-21sh23:20:010
1086599492,9cyclictest12516-21idleruntime22:35:170
1086599491,10cyclictest30024-21cat19:50:130
10867994742,3cyclictest26105-21sh20:50:012
139391420,0ptp4l401ktimersoftd/323:55:323
139391420,0ptp4l401ktimersoftd/319:40:213
139391420,0ptp4l401ktimersoftd/300:35:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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