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2026-03-31 - 23:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Mar 31, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300342204171,22sleep20-21swapper/207:07:322
139491204170,23phc2sys0-21swapper/307:07:023
299812203170,22sleep10-21swapper/107:06:511
300322201168,22sleep00-21swapper/007:07:300
3023328464,11sleep20-21swapper/207:10:002
30527996610,16cyclictest5436-21/usr/sbin/munin11:55:132
3052799656,23cyclictest4300-1kworker/2:0H09:25:012
139391650,0ptp4l401ktimersoftd/309:20:113
139391650,0ptp4l401ktimersoftd/309:20:103
3052799627,16cyclictest5395-21/usr/sbin/munin10:45:252
3052599625,17cyclictest0-21swapper/011:15:110
3052599615,19cyclictest0-21swapper/010:15:170
3052799608,11cyclictest18094-21chrt08:56:432
30525996011,17cyclictest13488-21sed09:55:220
139391600,1ptp4l401ktimersoftd/309:55:193
3052799598,11cyclictest30956-21unixbench_multi10:30:272
3052599597,17cyclictest0-21swapper/007:35:200
3052799588,11cyclictest28834-21chrt08:12:022
3052799587,12cyclictest13508-21cat09:55:212
3052599577,16cyclictest425-21grep10:35:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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