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2026-08-06 - 11:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Thu Aug 06, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179102206172,22sleep20-21swapper/219:08:032
139491206173,22phc2sys0-21swapper/319:09:223
179132204171,22sleep00-21swapper/019:08:050
159392204170,23sleep10-21swapper/119:05:091
1393911270,1ptp4l9099-21threads19:55:253
1394918464,11phc2sys0-21swapper/319:10:013
191092630,6sleep31835899cyclictest22:30:263
139391570,0ptp4l401ktimersoftd/321:11:503
139391540,1ptp4l391rcuc/321:50:443
261382530,3sleep09-21ksoftirqd/019:25:180
113812530,1sleep00-21swapper/020:00:230
139391500,9ptp4l0-21swapper/321:40:143
18357994540,3cyclictest1555-21turbostat.cron20:50:012
134491440,1getstats0-21swapper/300:00:243
57898430,8rtkit-daemon0-21swapper/119:40:321
139391430,0ptp4l401ktimersoftd/320:28:483
139391420,0ptp4l401ktimersoftd/322:59:363
57898410,1rtkit-daemon0-21swapper/100:25:441
139391400,0ptp4l401ktimersoftd/323:49:383
139391400,0ptp4l401ktimersoftd/321:15:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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