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2025-11-25 - 14:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Nov 25, 2025 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165072221161,50sleep00-21swapper/019:06:400
137191210146,52phc2sys0-21swapper/319:08:233
166602203169,22sleep10-21swapper/119:08:331
146342203170,22sleep20-21swapper/219:05:062
2884021380,6sleep01706499cyclictest22:55:160
153502600,1sleep10-21swapper/121:20:151
136991570,1ptp4l401ktimersoftd/320:40:443
136991570,1ptp4l401ktimersoftd/319:55:363
136991550,1ptp4l401ktimersoftd/300:19:233
84282530,2sleep28432-21sed22:10:262
202042530,2sleep20-21swapper/222:35:262
136991530,1ptp4l401ktimersoftd/322:55:223
245132500,2sleep30-21swapper/323:55:143
153892490,2sleep30-21swapper/320:11:373
136991430,0ptp4l401ktimersoftd/319:50:213
136991420,0ptp4l401ktimersoftd/322:20:133
136991420,0ptp4l401ktimersoftd/322:15:543
136991410,1ptp4l401ktimersoftd/322:33:543
136991390,0ptp4l401ktimersoftd/320:36:393
17065993832,4cyclictest25-21ksoftirqd/123:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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