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2025-12-31 - 07:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Wed Dec 31, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
83402204170,22sleep30-21swapper/319:08:423
81982202169,22sleep10-21swapper/119:06:511
81122202170,22sleep00-21swapper/019:05:510
81992201168,23sleep20-21swapper/219:06:532
239142770,2sleep10-21swapper/120:45:271
241922680,3sleep224196-21fschecks_count21:55:172
873499630,19cyclictest21972-21/usr/sbin/munin00:05:203
276992610,2sleep00-21swapper/023:10:120
100422550,2sleep110046-21irqrtprio21:25:191
139391520,1ptp4l391rcuc/321:45:223
139391450,0ptp4l401ktimersoftd/319:55:223
8733994430,12cyclictest33-21ksoftirqd/221:00:002
8731994416,3cyclictest9-21ksoftirqd/022:50:160
8732994336,4cyclictest25-21ksoftirqd/120:39:591
8731994311,8cyclictest9-21ksoftirqd/020:15:010
139391430,0ptp4l401ktimersoftd/319:30:493
8734994237,3cyclictest4475-21turbostat.cron23:30:003
8733994236,3cyclictest33-21ksoftirqd/219:40:002
139391420,0ptp4l401ktimersoftd/323:21:363
139391420,0ptp4l401ktimersoftd/322:09:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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