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2026-06-27 - 13:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jun 27, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188632206171,23sleep20-21swapper/219:06:172
139491205171,22phc2sys0-21swapper/319:05:073
188942204172,22sleep10-21swapper/119:06:411
188352201167,22sleep00-21swapper/019:05:550
2900521410,3sleep01944099cyclictest00:00:000
97952700,1sleep20-21swapper/219:55:202
97952700,1sleep20-21swapper/219:55:202
1914826037,15sleep30-21swapper/319:10:003
139391550,0ptp4l391rcuc/320:45:063
22932540,1sleep10-21swapper/120:45:251
19443995426,6cyclictest41-21ksoftirqd/300:35:253
1944399512,5cyclictest41-21ksoftirqd/323:45:173
139391510,0ptp4l391rcuc/320:44:513
39672490,2sleep00-21swapper/023:05:210
1944399475,6cyclictest41-21ksoftirqd/323:30:253
1944399472,7cyclictest41-21ksoftirqd/319:55:273
1944399472,7cyclictest41-21ksoftirqd/319:55:273
19443994712,7cyclictest41-21ksoftirqd/300:05:153
1944399465,7cyclictest41-21ksoftirqd/300:10:153
1944399465,6cyclictest41-21ksoftirqd/321:05:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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