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2026-09-14 - 19:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Sep 14, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142412207174,21sleep30-21swapper/307:07:223
143282204170,23sleep20-21swapper/207:08:292
142442203170,22sleep10-21swapper/107:07:241
141932202168,23sleep00-21swapper/007:06:420
14750997715,60cyclictest0-21swapper/110:05:531
14751997112,57cyclictest26857-21kworker/2:210:05:132
134391620,7getstats1475299cyclictest07:14:123
139391610,1ptp4l401ktimersoftd/311:40:283
14751996029,11cyclictest33-21ksoftirqd/207:15:002
14751996026,5cyclictest33-21ksoftirqd/208:55:142
14751996022,6cyclictest33-21ksoftirqd/207:15:132
14751995926,5cyclictest33-21ksoftirqd/211:25:222
14751995827,9cyclictest33-21ksoftirqd/212:35:142
14751995827,6cyclictest33-21ksoftirqd/212:25:142
14751995827,6cyclictest33-21ksoftirqd/208:25:172
14751995826,5cyclictest33-21ksoftirqd/209:45:002
14751995825,6cyclictest33-21ksoftirqd/211:05:202
14751995823,6cyclictest33-21ksoftirqd/212:00:002
14751995823,6cyclictest33-21ksoftirqd/209:00:272
14751995821,5cyclictest33-21ksoftirqd/210:50:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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