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2026-07-18 - 12:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Sat Jul 18, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290402204170,23sleep30-21swapper/319:08:163
290232204172,21sleep10-21swapper/119:08:021
288972204171,22sleep00-21swapper/019:06:230
288812204170,23sleep20-21swapper/219:06:172
57898890,68rtkit-daemon0-21swapper/019:10:000
307892560,2sleep30-21swapper/321:25:223
1394915336,9phc2sys0-21swapper/319:10:013
57898450,8rtkit-daemon0-21swapper/020:05:150
139391450,0ptp4l401ktimersoftd/319:27:133
139391430,0ptp4l401ktimersoftd/320:50:303
139391430,0ptp4l401ktimersoftd/319:32:113
57898410,2rtkit-daemon0-21swapper/019:40:460
139391410,0ptp4l401ktimersoftd/322:28:383
139391410,0ptp4l401ktimersoftd/320:25:203
139391400,0ptp4l401ktimersoftd/320:00:323
29468993832,4cyclictest41-21ksoftirqd/319:51:443
29468993832,3cyclictest41-21ksoftirqd/321:55:143
29468993730,4cyclictest17004-21irqrtprio22:05:163
29468993631,3cyclictest41-21ksoftirqd/323:07:043
29468993630,4cyclictest41-21ksoftirqd/323:15:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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