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2026-07-21 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Tue Jul 21, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38112236169,23sleep30-21swapper/307:06:353
38102207172,23sleep20-21swapper/207:06:332
40792204171,23sleep00-21swapper/007:09:570
40482203171,21sleep10-21swapper/107:09:341
2970221410,4sleep0437599cyclictest09:10:140
437599576,17cyclictest3089-21latency_hist08:15:000
437599573,18cyclictest0-21swapper/009:59:340
437599557,9cyclictest3202-21grep10:30:130
437599549,8cyclictest27459-21/usr/sbin/munin09:05:150
437599533,15cyclictest0-21swapper/009:30:140
437599533,14cyclictest0-21swapper/009:00:170
437599528,8cyclictest9464-21df_abs09:35:130
437799514,6cyclictest32534-21iwlist09:15:192
437599517,7cyclictest10410-21kernelversion11:50:200
437599517,17cyclictest6049-21hwlatdetect10:35:160
437599516,16cyclictest5831-21awk07:10:240
437599513,16cyclictest0-21swapper/008:20:230
4377995019,3cyclictest33-21ksoftirqd/209:03:372
437599504,15cyclictest0-21swapper/009:45:170
437599497,8cyclictest14626-21hddtemp_smartct07:30:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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