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2026-07-06 - 18:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Mon Jul 06, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491224196,19phc2sys0-21swapper/307:09:583
166652206173,22sleep20-21swapper/207:09:292
165732204170,23sleep00-21swapper/007:08:180
164032203170,21sleep10-21swapper/107:06:071
139391920,1ptp4l1951-21/usr/sbin/munin12:15:153
17005996426,5cyclictest9-21ksoftirqd/010:15:140
17005996226,10cyclictest9-21ksoftirqd/012:25:270
17008996127,5cyclictest41-21ksoftirqd/310:35:263
17005996121,8cyclictest9-21ksoftirqd/008:10:160
17008996032,7cyclictest41-21ksoftirqd/312:35:163
17008996031,4cyclictest41-21ksoftirqd/308:00:223
17008996028,9cyclictest41-21ksoftirqd/309:50:013
17008996023,8cyclictest41-21ksoftirqd/311:40:003
17005996026,5cyclictest9-21ksoftirqd/011:55:230
17008995929,4cyclictest41-21ksoftirqd/311:25:203
17008995830,7cyclictest41-21ksoftirqd/308:25:003
17008995830,4cyclictest41-21ksoftirqd/307:40:193
17008995829,7cyclictest41-21ksoftirqd/307:35:003
17008995829,3cyclictest41-21ksoftirqd/310:17:143
17008995824,9cyclictest41-21ksoftirqd/309:05:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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