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2026-03-02 - 10:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 02, 2026 00:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491207173,22phc2sys0-21swapper/319:06:513
79072204170,23sleep20-21swapper/219:09:192
77222203169,22sleep10-21swapper/119:06:531
77562201168,22sleep00-21swapper/019:07:200
1394919368,13phc2sys0-21swapper/319:10:013
8254998334,3cyclictest25-21ksoftirqd/123:19:591
153802730,1sleep00-21swapper/019:25:010
8256995928,7cyclictest41-21ksoftirqd/322:32:093
8256995828,9cyclictest41-21ksoftirqd/320:40:003
8256995827,10cyclictest41-21ksoftirqd/300:30:213
253702580,6sleep1825499cyclictest20:50:271
95752570,1sleep10-21swapper/122:35:011
825499569,7cyclictest25-21ksoftirqd/122:55:201
281342560,1sleep20-21swapper/223:10:282
825699554,6cyclictest29955-21cat00:24:593
825699544,7cyclictest5310-21tune2fs22:25:173
8254995413,9cyclictest121rcu_preempt22:45:121
825699530,7cyclictest401ktimersoftd/322:40:013
825699524,7cyclictest1985-21cut23:25:173
825699523,7cyclictest401ktimersoftd/322:45:013
825699523,7cyclictest14706-21hwlatdetect20:30:163
825699523,6cyclictest401ktimersoftd/321:30:243
825699522,7cyclictest8021-21vmstat21:20:263
8256995227,8cyclictest41-21ksoftirqd/320:25:253
8255995229,5cyclictest33-21ksoftirqd/220:11:442
8255995221,7cyclictest33-21ksoftirqd/200:10:232
8254995234,4cyclictest25-21ksoftirqd/100:00:011
160842520,2sleep10-21swapper/121:40:121
825699514,5cyclictest0-21swapper/319:30:203
8254995112,8cyclictest25-21ksoftirqd/122:00:251
163012510,1sleep20-21swapper/219:25:192
8256995022,9cyclictest41-21ksoftirqd/320:00:253
825699501,7cyclictest9006-21cat20:20:003
8255995023,17cyclictest33-21ksoftirqd/222:10:252
825499508,9cyclictest25-21ksoftirqd/123:10:281
825499508,8cyclictest25-21ksoftirqd/122:50:131
8254995031,3cyclictest25-21ksoftirqd/100:10:261
825699493,6cyclictest401ktimersoftd/319:20:143
8256994919,9cyclictest41-21ksoftirqd/320:25:013
825699491,6cyclictest401ktimersoftd/321:05:143
825699490,6cyclictest401ktimersoftd/300:10:143
8255994923,19cyclictest33-21ksoftirqd/223:05:272
8254994911,2cyclictest121rcu_preempt19:55:191
8253994918,7cyclictest9-21ksoftirqd/023:40:130
8253994915,4cyclictest9-21ksoftirqd/021:30:230
825699483,7cyclictest401ktimersoftd/321:25:133
825699483,6cyclictest401ktimersoftd/322:20:123
825699482,6cyclictest27564-21cat22:05:013
825699481,6cyclictest401ktimersoftd/323:30:213
8254994812,4cyclictest25-21ksoftirqd/122:15:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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