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2026-03-09 - 07:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 09, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491211177,23phc2sys0-21swapper/319:09:463
71642202168,22sleep10-21swapper/119:05:431
74612201169,21sleep20-21swapper/219:09:342
73202200168,22sleep00-21swapper/019:07:430
1394918161,11phc2sys0-21swapper/319:10:013
7789995918,5cyclictest25-21ksoftirqd/120:05:001
7789995612,4cyclictest25-21ksoftirqd/122:25:011
262272550,4sleep10-21swapper/119:45:261
7789995412,8cyclictest25-21ksoftirqd/121:25:201
284352530,2sleep10-21swapper/122:05:221
778999519,7cyclictest25-21ksoftirqd/100:35:181
7789995118,6cyclictest25-21ksoftirqd/121:00:131
7789995112,8cyclictest25-21ksoftirqd/120:10:201
778999509,9cyclictest25-21ksoftirqd/123:30:161
7789994938,3cyclictest25-21ksoftirqd/121:00:001
7789994919,4cyclictest25-21ksoftirqd/119:25:261
778999489,7cyclictest25-21ksoftirqd/121:50:221
778999481,45cyclictest0-21swapper/123:15:231
7789994814,3cyclictest121rcu_preempt00:30:221
779099478,37cyclictest32568-21kworker/2:219:34:332
778999473,7cyclictest25-21ksoftirqd/123:55:001
7789994710,10cyclictest25-21ksoftirqd/121:15:171
7790994617,27cyclictest6218-21kworker/2:022:56:242
779099460,43cyclictest30512-21cron21:05:012
7789994635,3cyclictest25-21ksoftirqd/100:25:001
7789994620,11cyclictest25-21ksoftirqd/100:15:261
7789994612,2cyclictest121rcu_preempt20:50:181
779099450,3cyclictest555-21kworker/2:121:15:332
778999458,4cyclictest25-21ksoftirqd/119:55:231
778999457,9cyclictest25-21ksoftirqd/100:10:161
778999456,8cyclictest25-21ksoftirqd/119:10:241
778999452,3cyclictest25-21ksoftirqd/123:45:271
7789994513,4cyclictest25-21ksoftirqd/119:35:171
7789994510,9cyclictest25-21ksoftirqd/122:00:001
7788994514,3cyclictest9-21ksoftirqd/020:50:160
7788994514,3cyclictest9-21ksoftirqd/000:25:280
7788994513,3cyclictest9-21ksoftirqd/021:50:010
778999449,4cyclictest25-21ksoftirqd/121:40:261
778999447,4cyclictest25-21ksoftirqd/121:45:251
778999446,4cyclictest25-21ksoftirqd/123:35:221
7789994438,3cyclictest25-21ksoftirqd/123:25:001
778999441,2cyclictest121rcu_preempt19:30:171
7789994411,4cyclictest25-21ksoftirqd/122:45:171
7788994417,4cyclictest9-21ksoftirqd/020:40:130
7788994415,3cyclictest9-21ksoftirqd/021:25:200
7788994412,4cyclictest9-21ksoftirqd/020:20:250
778999437,4cyclictest25-21ksoftirqd/122:40:201
778999436,4cyclictest25-21ksoftirqd/122:55:171
7789994312,3cyclictest121rcu_preempt21:05:141
7789994311,9cyclictest25-21ksoftirqd/122:00:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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