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2026-03-30 - 21:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Mon Mar 30, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491227163,52phc2sys0-21swapper/307:08:223
1725822200,7sleep09706-21kworker/0:007:05:180
181522202169,22sleep10-21swapper/107:05:531
183072201169,21sleep20-21swapper/207:07:542
1580921740,5sleep31877699cyclictest11:30:233
91232560,2sleep10-21swapper/110:10:221
139391510,1ptp4l401ktimersoftd/311:46:433
157502500,2sleep00-21swapper/010:25:170
139391500,0ptp4l401ktimersoftd/307:42:053
139391480,13ptp4l0-21swapper/309:35:133
139391460,10ptp4l0-21swapper/309:10:193
18773994438,3cyclictest19675-21sh10:35:000
139391430,0ptp4l401ktimersoftd/312:25:553
139391430,0ptp4l401ktimersoftd/312:15:193
139391430,0ptp4l401ktimersoftd/308:15:143
139391420,0ptp4l401ktimersoftd/309:32:393
18775994124,5cyclictest33-21ksoftirqd/212:10:282
1877499411,11cyclictest25-21ksoftirqd/111:00:011
139391410,1ptp4l391rcuc/307:15:193
18775994028,9cyclictest33-21ksoftirqd/210:00:172
1877499404,3cyclictest121rcu_preempt07:55:201
1877499403,6cyclictest121rcu_preempt11:30:161
18774994035,3cyclictest14997-21sh08:10:001
18773994036,2cyclictest9-21ksoftirqd/010:00:000
18774993936,2cyclictest25-21ksoftirqd/110:25:001
139391390,0ptp4l401ktimersoftd/309:00:003
18775993833,3cyclictest560-21latency_hist07:39:592
18775993832,3cyclictest33-21ksoftirqd/208:19:592
1877499385,3cyclictest25-21ksoftirqd/109:45:171
18774993834,2cyclictest25-21ksoftirqd/107:20:001
1877499383,3cyclictest121rcu_preempt10:30:261
18774993833,3cyclictest25-21ksoftirqd/107:50:181
18774993832,4cyclictest25-21ksoftirqd/109:57:101
18774993832,3cyclictest25-21ksoftirqd/109:00:001
18773993833,3cyclictest9-21ksoftirqd/010:20:130
18773993833,3cyclictest9-21ksoftirqd/010:10:000
18775993732,3cyclictest33-21ksoftirqd/207:55:002
18774993733,2cyclictest25-21ksoftirqd/107:45:001
18774993732,3cyclictest25-21ksoftirqd/111:35:001
18774993732,3cyclictest25-21ksoftirqd/108:30:191
18774993732,3cyclictest25-21ksoftirqd/108:25:101
18774993731,4cyclictest25-21ksoftirqd/110:30:011
18774993731,3cyclictest25-21ksoftirqd/110:45:241
18774993730,4cyclictest25-21ksoftirqd/112:20:111
18773993733,2cyclictest9-21ksoftirqd/008:15:000
18773993724,3cyclictest9-21ksoftirqd/008:00:250
18773993720,8cyclictest9-21ksoftirqd/007:45:260
1877399371,5cyclictest121rcu_preempt07:50:220
18776993630,4cyclictest41-21ksoftirqd/309:21:013
18776993630,4cyclictest41-21ksoftirqd/308:44:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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