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2026-02-25 - 23:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Wed Feb 25, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491220192,19phc2sys0-21swapper/307:09:593
172752208175,22sleep10-21swapper/107:08:201
171062200168,21sleep20-21swapper/207:06:082
171242195161,22sleep00-21swapper/007:06:220
2932721470,6sleep01770599cyclictest10:55:240
2932721470,6sleep01770599cyclictest10:55:230
17705997527,4cyclictest9-21ksoftirqd/011:05:000
17708996330,3cyclictest41-21ksoftirqd/308:50:003
17708996322,7cyclictest41-21ksoftirqd/312:15:193
17705996316,3cyclictest9-21ksoftirqd/009:05:170
17705996316,3cyclictest9-21ksoftirqd/009:05:170
17708995920,8cyclictest41-21ksoftirqd/311:30:183
17708995827,9cyclictest41-21ksoftirqd/310:45:183
226542570,1sleep00-21swapper/007:20:130
17708995622,10cyclictest41-21ksoftirqd/308:54:593
17708995522,9cyclictest41-21ksoftirqd/309:00:263
17708995519,4cyclictest41-21ksoftirqd/312:10:193
17708995517,8cyclictest41-21ksoftirqd/307:25:003
113942550,1sleep20-21swapper/208:05:002
113942550,1sleep20-21swapper/208:05:002
17708995430,7cyclictest41-21ksoftirqd/309:30:003
17708995423,6cyclictest41-21ksoftirqd/309:30:153
17708995423,4cyclictest41-21ksoftirqd/309:55:243
17708995420,4cyclictest41-21ksoftirqd/311:10:273
17708995419,8cyclictest41-21ksoftirqd/307:10:133
17708995417,8cyclictest41-21ksoftirqd/311:54:593
17708995417,7cyclictest41-21ksoftirqd/308:10:233
17708995323,7cyclictest41-21ksoftirqd/309:24:593
17708995321,9cyclictest41-21ksoftirqd/311:25:133
17708995319,8cyclictest41-21ksoftirqd/310:10:003
17708995319,4cyclictest41-21ksoftirqd/308:55:223
17708995318,7cyclictest41-21ksoftirqd/307:25:153
17708995318,4cyclictest41-21ksoftirqd/309:10:223
17708995317,9cyclictest41-21ksoftirqd/307:55:263
17708995317,8cyclictest41-21ksoftirqd/312:00:143
17708995317,8cyclictest41-21ksoftirqd/308:00:143
17708995317,8cyclictest41-21ksoftirqd/308:00:143
17708995222,7cyclictest41-21ksoftirqd/310:55:243
17708995222,7cyclictest41-21ksoftirqd/310:55:243
17708995220,6cyclictest41-21ksoftirqd/310:00:143
17708995219,7cyclictest41-21ksoftirqd/308:30:133
17708995219,3cyclictest41-21ksoftirqd/310:40:163
17708995215,9cyclictest41-21ksoftirqd/310:15:213
17708995214,11cyclictest41-21ksoftirqd/311:55:153
17708995127,5cyclictest41-21ksoftirqd/309:45:003
17708995120,8cyclictest41-21ksoftirqd/309:45:143
17708995119,8cyclictest41-21ksoftirqd/311:15:213
17708995118,7cyclictest41-21ksoftirqd/311:20:163
17708995116,4cyclictest41-21ksoftirqd/310:30:243
17708995111,8cyclictest41-21ksoftirqd/310:20:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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