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2026-06-09 - 06:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Tue Jun 09, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269902224197,18sleep10-21swapper/119:07:591
139491205172,22phc2sys0-21swapper/319:06:243
269072203169,23sleep00-21swapper/019:07:010
270782201169,21sleep20-21swapper/219:09:082
276221340,3sleep32744099cyclictest19:25:173
2743899616,11cyclictest20229-21sort23:20:251
2743899616,11cyclictest20229-21sort23:20:251
113472600,5sleep02743799cyclictest21:55:250
2743899595,12cyclictest29064-21cat22:35:011
27439995815,9cyclictest33-21ksoftirqd/223:55:002
34592570,1sleep10-21swapper/119:25:241
2743899565,12cyclictest2088-21cut22:45:151
139391560,1ptp4l401ktimersoftd/320:55:153
2743899555,16cyclictest11694-21ptp4l00:10:231
2743899545,12cyclictest29878-21cpu19:15:131
2743899545,11cyclictest25411-21sed22:25:181
2743899535,12cyclictest15660-21sed19:50:201
2743899534,11cyclictest28306-21cpu23:40:131
2743899525,17cyclictest31652-21cpu22:40:121
139391520,1ptp4l401ktimersoftd/300:36:293
2743999515,3cyclictest121rcu_preempt23:40:232
2743899513,17cyclictest0-21swapper/121:35:011
2743899486,13cyclictest3601-21if_enp4s023:55:171
2743899485,16cyclictest12757-21/usr/sbin/munin00:15:201
2743899476,12cyclictest11268-21awk21:55:251
2743899476,11cyclictest13925-21head22:00:261
2743899463,9cyclictest0-21swapper/120:00:161
27439994533,3cyclictest33-21ksoftirqd/222:30:152
27439994515,7cyclictest33-21ksoftirqd/200:20:002
27439994513,4cyclictest33-21ksoftirqd/221:35:192
27439994414,3cyclictest33-21ksoftirqd/220:55:182
2743899444,8cyclictest31655-21meminfo23:45:201
27440994338,3cyclictest23056-21fschecks_count21:15:143
27440994337,3cyclictest41-21ksoftirqd/321:59:593
27439994334,8cyclictest33-21ksoftirqd/221:55:252
27439994332,9cyclictest33-21ksoftirqd/219:15:242
27439994332,9cyclictest33-21ksoftirqd/200:30:262
27439994316,3cyclictest33-21ksoftirqd/223:25:262
2743899435,10cyclictest319-21date20:25:251
139391430,0ptp4l401ktimersoftd/322:16:083
139391430,0ptp4l401ktimersoftd/319:20:013
2743999429,5cyclictest33-21ksoftirqd/223:05:192
27439994236,3cyclictest33-21ksoftirqd/220:44:592
27439994230,9cyclictest33-21ksoftirqd/223:45:242
2743999421,3cyclictest121rcu_preempt22:00:272
27439994212,7cyclictest33-21ksoftirqd/222:19:592
139391420,0ptp4l401ktimersoftd/323:18:583
139391420,0ptp4l401ktimersoftd/323:18:583
2743999416,4cyclictest33-21ksoftirqd/222:20:272
2743999415,5cyclictest33-21ksoftirqd/219:10:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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