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2026-03-06 - 05:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Fri Mar 06, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304162230162,22sleep20-21swapper/219:05:572
305982204171,21sleep00-21swapper/019:08:120
303952204171,22sleep10-21swapper/119:05:401
139491203169,23phc2sys0-21swapper/319:09:163
96472720,2sleep00-21swapper/000:00:280
96472720,2sleep00-21swapper/000:00:280
139391680,1ptp4l4027-21irqstats23:50:203
134391620,1getstats0-21swapper/323:40:283
3102899570,17cyclictest4331-21/usr/sbin/munin21:35:232
3102899570,17cyclictest21610-21/usr/sbin/munin19:55:242
3102899570,17cyclictest0-21swapper/220:20:002
228072560,3sleep03102699cyclictest00:30:120
31027995523,4cyclictest25-21ksoftirqd/120:25:001
73102540,1sleep10-21swapper/122:50:121
116062530,1sleep20-21swapper/223:00:002
211282520,2sleep20-21swapper/222:10:222
3102899510,11cyclictest1647-21cat23:45:202
3102899500,17cyclictest1300-21snmpd20:11:512
3102899500,10cyclictest10174-21latency_hist00:05:002
3102899500,10cyclictest10174-21latency_hist00:05:002
31027995013,4cyclictest25-21ksoftirqd/119:10:131
31028994916,30cyclictest16317-21ls00:15:232
3102899490,10cyclictest921-21date19:15:002
31027994922,7cyclictest25-21ksoftirqd/119:39:591
31027994919,4cyclictest25-21ksoftirqd/121:45:261
3102899480,11cyclictest3094-21/usr/sbin/munin23:50:182
3102899480,11cyclictest12649-21irqstats23:00:212
31027994816,4cyclictest25-21ksoftirqd/123:00:001
31027994816,4cyclictest25-21ksoftirqd/121:55:251
31027994815,4cyclictest25-21ksoftirqd/122:05:271
31027994719,3cyclictest25-21ksoftirqd/121:35:281
31027994716,4cyclictest25-21ksoftirqd/123:55:131
31027994714,8cyclictest25-21ksoftirqd/119:30:241
3102799460,2cyclictest121rcu_preempt19:25:001
3102899450,11cyclictest20333-21timerandwakeup23:15:252
31027994532,3cyclictest25-21ksoftirqd/100:30:001
31027994513,7cyclictest25-21ksoftirqd/122:25:001
31027994513,4cyclictest25-21ksoftirqd/119:15:191
31027994513,4cyclictest25-21ksoftirqd/119:15:181
31027994511,4cyclictest25-21ksoftirqd/123:20:271
31027994511,3cyclictest25-21ksoftirqd/121:05:191
31027994511,3cyclictest25-21ksoftirqd/120:05:271
31027994510,4cyclictest25-21ksoftirqd/119:45:251
31029994414,28cyclictest17997-21kworker/3:023:36:033
31027994416,3cyclictest25-21ksoftirqd/121:14:121
31027994410,7cyclictest25-21ksoftirqd/121:25:291
31027994410,4cyclictest25-21ksoftirqd/123:35:211
139391440,1ptp4l401ktimersoftd/323:58:133
139391440,1ptp4l401ktimersoftd/323:33:413
139391440,1ptp4l401ktimersoftd/322:18:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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