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2026-02-21 - 20:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 21, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491230164,23phc2sys0-21swapper/307:06:243
178562208175,22sleep00-21swapper/007:07:480
180192206173,22sleep10-21swapper/107:09:491
177702203170,22sleep20-21swapper/207:06:412
1190421740,4sleep01832699cyclictest11:25:020
123102610,2sleep10-21swapper/112:30:241
57898520,37rtkit-daemon0-21swapper/207:10:012
139391500,1ptp4l401ktimersoftd/309:02:463
18326994438,3cyclictest21316-21latency_hist11:45:000
18327994336,4cyclictest25-21ksoftirqd/108:24:591
139391420,0ptp4l401ktimersoftd/308:50:013
18328994130,9cyclictest33-21ksoftirqd/208:35:272
18327994136,3cyclictest25-21ksoftirqd/108:59:591
139391410,0ptp4l401ktimersoftd/309:45:273
18329994034,4cyclictest41-21ksoftirqd/310:02:303
18326994035,3cyclictest29997-21cron07:35:000
139391400,0ptp4l401ktimersoftd/310:44:103
18327993933,3cyclictest25-21ksoftirqd/110:49:591
273722380,1sleep20-21swapper/211:55:192
18327993833,3cyclictest25-21ksoftirqd/111:25:001
18327993833,3cyclictest25-21ksoftirqd/109:04:591
18327993832,4cyclictest35892irq/126-enp1s0-10:53:041
18327993832,3cyclictest25-21ksoftirqd/108:20:011
18327993832,3cyclictest25-21ksoftirqd/107:55:011
18328993730,4cyclictest33-21ksoftirqd/209:14:492
18327993732,3cyclictest25-21ksoftirqd/108:34:591
18327993732,3cyclictest25-21ksoftirqd/107:15:001
18327993731,4cyclictest25-21ksoftirqd/110:15:541
18327993731,3cyclictest25-21ksoftirqd/108:30:001
18329993631,3cyclictest41-21ksoftirqd/307:10:303
18329993630,4cyclictest41-21ksoftirqd/311:23:473
18329993630,4cyclictest41-21ksoftirqd/311:04:583
18328993631,3cyclictest33-21ksoftirqd/209:00:002
18328993630,4cyclictest33-21ksoftirqd/210:27:062
18327993632,3cyclictest25-21ksoftirqd/112:10:001
18327993632,3cyclictest25-21ksoftirqd/107:45:011
18327993632,3cyclictest25-21ksoftirqd/107:45:011
18327993631,3cyclictest25-21ksoftirqd/111:55:121
18327993631,3cyclictest25-21ksoftirqd/109:55:171
18327993631,3cyclictest25-21ksoftirqd/109:35:191
18327993630,4cyclictest25-21ksoftirqd/110:13:091
18326993631,3cyclictest9-21ksoftirqd/008:40:010
18326993629,5cyclictest9-21ksoftirqd/010:43:570
139391360,0ptp4l401ktimersoftd/307:55:173
18329993530,3cyclictest41-21ksoftirqd/311:50:103
18329993530,3cyclictest41-21ksoftirqd/308:30:113
18329993529,4cyclictest41-21ksoftirqd/312:04:313
18329993529,4cyclictest41-21ksoftirqd/311:30:333
18329993529,4cyclictest41-21ksoftirqd/310:36:093
18329993529,4cyclictest41-21ksoftirqd/309:56:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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