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2026-03-05 - 04:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Thu Mar 05, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244152207167,22sleep20-21swapper/219:07:092
224582204170,23sleep30-21swapper/319:05:093
246272202169,22sleep10-21swapper/119:09:531
244702202168,23sleep00-21swapper/019:07:510
2464528161,10sleep00-21swapper/019:10:000
279912550,1sleep10-21swapper/119:15:181
2493999481,44cyclictest14898-21kworker/3:000:33:043
139391460,7ptp4l401ktimersoftd/319:15:543
79602450,2sleep00-21swapper/020:50:000
139391430,0ptp4l401ktimersoftd/323:50:193
139391430,0ptp4l401ktimersoftd/321:58:523
139391430,0ptp4l401ktimersoftd/321:58:523
12532430,1sleep20-21swapper/220:35:142
139391420,0ptp4l401ktimersoftd/323:30:153
139391420,0ptp4l401ktimersoftd/322:21:273
24936994132,6cyclictest9-21ksoftirqd/000:34:590
24939994026,12cyclictest41-21ksoftirqd/323:55:093
139391400,1ptp4l401ktimersoftd/323:46:553
57898390,2rtkit-daemon0-21swapper/121:18:491
24938993933,4cyclictest33-21ksoftirqd/222:45:002
139391390,1ptp4l401ktimersoftd/322:49:323
24939993822,3cyclictest41-21ksoftirqd/323:15:103
24939993732,3cyclictest41-21ksoftirqd/320:25:003
24939993721,4cyclictest41-21ksoftirqd/321:13:103
24938993732,3cyclictest33-21ksoftirqd/219:55:102
24938993732,3cyclictest33-21ksoftirqd/219:55:102
24938993731,4cyclictest33-21ksoftirqd/223:22:422
24937993731,3cyclictest29755-21cron23:50:001
313252360,5sleep32493999cyclictest19:20:213
24938993631,3cyclictest33-21ksoftirqd/220:23:272
24938993630,4cyclictest33-21ksoftirqd/220:50:002
24937993630,4cyclictest25-21ksoftirqd/123:16:221
24937993630,4cyclictest25-21ksoftirqd/123:11:211
24937993630,4cyclictest25-21ksoftirqd/123:02:141
24937993630,4cyclictest25-21ksoftirqd/120:29:271
24937993630,4cyclictest25-21ksoftirqd/100:34:341
24937993630,3cyclictest25-21ksoftirqd/120:04:131
24937993629,5cyclictest25-21ksoftirqd/120:59:321
24939993529,4cyclictest41-21ksoftirqd/322:29:243
24938993529,4cyclictest33-21ksoftirqd/223:02:402
24937993529,4cyclictest25-21ksoftirqd/123:10:001
24937993529,4cyclictest25-21ksoftirqd/100:11:231
24937993529,3cyclictest25-21ksoftirqd/121:54:591
24937993528,4cyclictest25-21ksoftirqd/119:34:231
24936993529,4cyclictest9-21ksoftirqd/020:55:100
24936993529,4cyclictest9-21ksoftirqd/020:01:380
24939993429,3cyclictest41-21ksoftirqd/323:26:263
24939993429,3cyclictest41-21ksoftirqd/323:22:303
24939993428,4cyclictest41-21ksoftirqd/323:44:093
24939993428,4cyclictest41-21ksoftirqd/322:30:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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