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2026-01-31 - 20:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 31, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291372215171,32sleep10-21swapper/107:08:081
292232206173,23sleep30-21swapper/307:09:153
291652202168,23sleep20-21swapper/207:08:282
271482201168,22sleep00-21swapper/007:05:050
1394918965,15phc2sys0-21swapper/307:10:013
237492810,2sleep20-21swapper/212:35:142
139391780,1ptp4l391rcuc/308:35:253
139391720,1ptp4l391rcuc/310:05:363
106142690,6sleep32958499cyclictest09:50:253
2958499547,45cyclictest15955-21kworker/3:212:33:333
139391540,1ptp4l391rcuc/309:00:513
34972530,2sleep30-21swapper/308:30:123
2958499484,42cyclictest4957-21kworker/3:007:33:133
29583994531,12cyclictest33-21ksoftirqd/210:15:012
29582994537,5cyclictest20860-21dump-pmu-power10:15:001
134391440,8getstats2958499cyclictest08:27:143
139391430,0ptp4l401ktimersoftd/312:00:273
139391430,0ptp4l401ktimersoftd/309:47:363
139391420,0ptp4l401ktimersoftd/310:40:063
139391420,0ptp4l401ktimersoftd/308:46:113
139391420,0ptp4l401ktimersoftd/308:20:363
134491410,1getstats0-21swapper/307:35:263
57898390,3rtkit-daemon577-21rtkit-daemon11:52:031
139391390,2ptp4l391rcuc/311:50:193
57898380,3rtkit-daemon577-21rtkit-daemon10:02:031
57898380,3rtkit-daemon577-21rtkit-daemon08:13:541
29584993833,3cyclictest12988-21wc08:50:133
29584993827,9cyclictest41-21ksoftirqd/310:30:113
29583993831,5cyclictest33-21ksoftirqd/208:19:592
2958399381,35cyclictest3864-21kworker/2:210:43:442
57898370,6rtkit-daemon0-21swapper/207:52:182
57898370,6rtkit-daemon0-21swapper/207:52:182
57898370,3rtkit-daemon577-21rtkit-daemon09:43:151
29583993731,4cyclictest33-21ksoftirqd/210:58:552
29583993731,3cyclictest33-21ksoftirqd/211:30:252
29582993731,4cyclictest25-21ksoftirqd/107:25:091
139391370,0ptp4l401ktimersoftd/311:10:243
29584993631,3cyclictest41-21ksoftirqd/311:25:013
29584993631,3cyclictest41-21ksoftirqd/311:25:003
29584993630,4cyclictest41-21ksoftirqd/309:58:593
29583993617,17cyclictest33-21ksoftirqd/210:10:012
29582993630,4cyclictest25-21ksoftirqd/111:34:401
29582993630,4cyclictest25-21ksoftirqd/109:57:411
29581993631,3cyclictest9-21ksoftirqd/012:05:000
134391360,1getstats0-21swapper/307:27:143
29584993530,3cyclictest41-21ksoftirqd/307:20:083
29584993529,4cyclictest41-21ksoftirqd/312:24:003
29584993529,4cyclictest41-21ksoftirqd/312:13:383
29584993524,9cyclictest41-21ksoftirqd/309:26:053
29584993523,10cyclictest41-21ksoftirqd/310:23:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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