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2026-02-24 - 21:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Tue Feb 24, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2762722230,5sleep30-21swapper/307:08:003
2686322200,7sleep126848-21sh07:09:351
2380422100,5sleep20-21swapper/207:08:262
285832200167,22sleep00-21swapper/007:06:130
736621640,6sleep22236499cyclictest09:50:222
2236499748,11cyclictest3571-21od07:10:222
2236499698,15cyclictest7906-21awk07:40:002
11852680,9sleep31215-21grep07:11:503
2236499659,11cyclictest13354-21latency_hist12:20:012
2236499647,16cyclictest4097-21systemctl10:50:242
2236499638,15cyclictest9563-21irqrtprio12:10:182
2236499638,11cyclictest616-21gdbus10:40:002
22364996310,18cyclictest32214-21sed09:35:172
22364996310,18cyclictest32214-21sed09:35:172
2236499628,16cyclictest16977-21/usr/sbin/munin11:20:242
2236499627,11cyclictest11495-21sort10:00:162
2236499626,16cyclictest0-21swapper/211:45:142
2236499618,11cyclictest19673-21grep09:10:122
2236499616,26cyclictest0-21swapper/211:00:002
2236499616,12cyclictest0-21swapper/208:45:142
2236499616,11cyclictest32148-21irqrtprio11:50:192
22364996113,10cyclictest17829-21sed09:05:192
2236499607,11cyclictest760-21cut10:45:182
2236499606,16cyclictest0-21swapper/207:45:002
2236499605,17cyclictest0-21swapper/210:40:202
2236499605,17cyclictest0-21swapper/210:40:202
22364996011,9cyclictest13436-21/usr/sbin/munin12:20:202
2236499599,10cyclictest14773-21mailstats10:05:242
2236499597,17cyclictest3420-21irqrtprio08:35:182
2236499597,10cyclictest22610-21irqrtprio11:30:172
22364995912,9cyclictest9158-21awk11:00:292
22364995911,9cyclictest5865-21cut08:40:182
227522580,3sleep122764-21sort07:11:351
2236499588,10cyclictest31077-21sed08:25:192
2236499587,18cyclictest10640-21cut11:05:202
2236499587,11cyclictest23902-21latency10:25:232
2236499586,16cyclictest0-21swapper/212:05:122
2236499586,10cyclictest15877-21sort12:25:142
22364995812,10cyclictest20835-21df_abs10:20:162
95062570,5sleep29510-21irqrtprio09:55:202
2236499575,10cyclictest0-21swapper/208:20:242
2236499569,15cyclictest25623-21gzip09:20:242
2236499568,11cyclictest22894-21wc12:40:002
2236499567,16cyclictest20761-21tr11:25:242
2236499567,16cyclictest11255-21cut07:45:182
2236499567,11cyclictest27477-21cat10:35:002
2236499566,9cyclictest0-21swapper/211:55:152
2236499566,16cyclictest0-21swapper/209:30:182
2236499566,11cyclictest26062-21irqrtprio08:15:192
2236499566,11cyclictest0-21swapper/208:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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