You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-24 - 19:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Sat Jan 24, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139491208173,23phc2sys0-21swapper/307:08:083
127822203170,22sleep00-21swapper/007:08:310
126282203170,22sleep10-21swapper/107:06:321
126242203170,22sleep20-21swapper/207:06:282
2741621160,2sleep00-21swapper/008:45:190
13193997311,19cyclictest12511-21awk11:35:270
13195996428,4cyclictest33-21ksoftirqd/211:35:272
13193996410,13cyclictest6275-21cut09:10:130
13195996321,6cyclictest33-21ksoftirqd/207:20:162
13195996224,8cyclictest33-21ksoftirqd/212:15:262
1319399629,11cyclictest22470-21chrt10:50:180
13195996129,4cyclictest33-21ksoftirqd/209:55:132
13195996125,4cyclictest33-21ksoftirqd/210:45:132
13195996125,4cyclictest33-21ksoftirqd/210:45:122
1319399619,10cyclictest1-21systemd08:15:240
13195996027,9cyclictest33-21ksoftirqd/212:05:272
13195996027,10cyclictest33-21ksoftirqd/210:00:192
13195996025,7cyclictest33-21ksoftirqd/210:25:012
1319399609,12cyclictest15036-21awk09:25:260
1319399608,10cyclictest14832-21df_abs08:20:140
13195995929,3cyclictest33-21ksoftirqd/207:35:162
13195995927,4cyclictest33-21ksoftirqd/210:25:182
13195995927,3cyclictest33-21ksoftirqd/208:50:242
1319399597,17cyclictest10024-21df_abs08:10:150
1319399596,11cyclictest0-21swapper/012:15:160
13195995828,4cyclictest33-21ksoftirqd/207:50:182
13195995827,6cyclictest33-21ksoftirqd/210:50:212
13195995824,6cyclictest33-21ksoftirqd/209:05:152
13195995821,6cyclictest33-21ksoftirqd/212:00:122
13195995819,5cyclictest33-21ksoftirqd/207:10:202
1319399588,9cyclictest31338-21cstates08:55:130
57898570,18rtkit-daemon28197-21cat09:55:163
13195995724,4cyclictest33-21ksoftirqd/208:10:182
13195995723,3cyclictest33-21ksoftirqd/211:50:012
1319399579,9cyclictest9087-21awk09:15:160
1319399579,9cyclictest9087-21awk09:15:160
1319399579,9cyclictest25499-21cstates09:50:140
1319399579,9cyclictest10719-21sort10:25:190
1319399575,9cyclictest0-21swapper/011:20:160
1319399575,9cyclictest0-21swapper/008:00:010
13195995630,7cyclictest33-21ksoftirqd/210:15:182
13195995628,3cyclictest33-21ksoftirqd/210:40:222
13195995624,10cyclictest33-21ksoftirqd/209:00:232
13195995617,10cyclictest33-21ksoftirqd/208:20:182
1319399568,10cyclictest7875-21fschecks_time10:20:160
1319399568,10cyclictest28441-21if_enp1s012:10:160
1319399567,10cyclictest7339-21date12:35:000
1319399566,11cyclictest32252-21latency_hist10:05:010
13195995520,4cyclictest33-21ksoftirqd/210:11:362
13195995517,6cyclictest33-21ksoftirqd/211:40:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional