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2026-03-01 - 01:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot3.osadl.org (updated Sat Feb 28, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181692230162,23sleep20-21swapper/207:09:062
139491206172,23phc2sys0-21swapper/307:06:193
182342204170,23sleep00-21swapper/007:09:520
182432203171,21sleep10-21swapper/107:09:571
97921450,5sleep11853999cyclictest11:00:261
1853999566,8cyclictest24957-21unixbench_singl11:50:271
1853999557,7cyclictest21475-21grep07:15:151
1853999546,6cyclictest14925-21sh12:40:001
230342530,4sleep123032-21perf11:50:011
1853999535,6cyclictest0-21swapper/112:15:001
1853999531,10cyclictest17551-21df_abs08:15:151
1853999530,10cyclictest12277-21latency_hist10:20:011
1853999526,6cyclictest31260-21irqrtprio12:05:161
1853999523,11cyclictest26692-21sed07:25:191
1853999522,10cyclictest10569-21cstates12:30:131
1853999521,11cyclictest31332-21cut07:35:211
1853999516,5cyclictest17866-21if_err_enp1s010:30:151
1853999513,9cyclictest3446-21awk11:05:251
38502500,1sleep30-21swapper/312:15:173
255552500,2sleep30-21swapper/311:55:013
1853999506,5cyclictest8610-21latency07:55:181
1853999503,6cyclictest0-21swapper/110:35:181
1853999500,11cyclictest10747-21sed08:00:191
1853999500,10cyclictest13119-21irqrtprio10:20:181
1853999497,6cyclictest4711-21grep12:15:251
1853999496,7cyclictest21480-21grep08:20:271
1853999490,9cyclictest7176-21fschecks_time09:00:141
1853999490,9cyclictest29206-21phc2sys12:00:211
1853999490,9cyclictest29206-21phc2sys12:00:211
1853999490,9cyclictest14766-21missed_timers11:30:211
1853999487,7cyclictest24455-21grep09:35:211
1853999481,9cyclictest29531-21ls08:40:121
1853999481,17cyclictest27237-21sed08:35:141
1853999480,9cyclictest16207-21ptp4l-jitter10:25:251
1853999480,9cyclictest12976-21if_enp4s008:05:161
1853999480,8cyclictest10737-21sed09:05:261
1853999480,16cyclictest13036-21sed11:25:261
1853999480,15cyclictest5682-21cut08:55:241
1853999480,11cyclictest17282-21expr09:20:201
162862480,1sleep20-21swapper/210:25:262
1853999473,5cyclictest0-21swapper/109:45:141
1853999471,10cyclictest7550-21date07:55:011
1853999470,10cyclictest16362-21cat08:10:231
139391470,0ptp4l401ktimersoftd/310:25:213
1853999464,6cyclictest11648-21cstates09:10:131
1853999461,9cyclictest3147-21cstates10:00:131
1853999461,11cyclictest32051-21df_abs08:45:151
1853999460,10cyclictest22843-21irqrtprio08:25:191
18538994614,7cyclictest9-21ksoftirqd/008:00:190
1854099450,44cyclictest0-21swapper/211:10:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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