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2026-01-27 - 06:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Tue Jan 27, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41076072300,1sleep10-21swapper/123:34:181
3701628992518,6cyclictest1290-21dbus-daemon22:40:010
3701629992421,2cyclictest4152867-21ssh00:00:011
3701630992118,1cyclictest0-21swapper/222:17:402
3701628992118,2cyclictest4108123-21cat23:35:000
3701628992115,5cyclictest0-21swapper/019:15:010
3701628992017,2cyclictest3974093-21sendmail22:20:010
3701628992017,2cyclictest1290-21dbus-daemon20:00:020
3701628992016,3cyclictest0-21swapper/020:10:030
3701628992012,4cyclictest4087801-21kthreadcore23:22:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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