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2025-10-28 - 10:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Tue Oct 28, 2025 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19121332930,1sleep00-21swapper/019:16:100
1900028993116,7cyclictest1661-21polkitd22:50:000
23763632280,1sleep12047382-21diskmemload00:16:081
1900028992415,8cyclictest2158235-21kthreadcore22:11:110
1900028992219,2cyclictest2011418-21grep20:40:010
1900030992118,1cyclictest0-21swapper/200:10:022
1900030992117,2cyclictest0-21swapper/200:31:012
2564091201,2phc2sys0-21swapper/323:48:423
1900030992018,1cyclictest0-21swapper/221:45:022
1900030992017,1cyclictest0-21swapper/200:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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