You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-10-29 - 08:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Thu Oct 29, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
365287321110,2sleep30-21swapper/321:26:263
373232421090,2sleep30-21swapper/322:11:243
36486482640,1sleep13648652-21tr21:21:311
345654599238,3cyclictest0-21swapper/123:21:061
38003732210,2sleep03800368-21sh22:47:410
3456545992114,3cyclictest3811079-21/usr/sbin/munin22:56:331
3456544992115,5cyclictest3749695-21cstates22:21:220
3456544992114,1cyclictest3972599-21ssh00:26:060
3456546992017,2cyclictest0-21swapper/219:36:392
3456545992015,2cyclictest3456542-21cyclictest00:20:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional