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2025-12-13 - 02:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Fri Dec 12, 2025 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
333904522240,3sleep30-21swapper/321:30:013
316921621590,2sleep33169219-21turbostat19:20:003
33693932970,1sleep13369397-21kthreadcore21:45:101
34057222430,1sleep00-21swapper/022:05:490
3160040993129,1cyclictest0-21swapper/200:30:022
3160039993128,2cyclictest3435186-21cstates22:25:011
34509282300,1sleep13450927-21ssh22:33:311
3160039993023,2cyclictest170550irq/121-eno120:05:011
3160038992724,2cyclictest0-21swapper/021:00:010
3160040992623,1cyclictest0-21swapper/200:00:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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