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2025-05-09 - 05:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Fri May 09, 2025 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
339863121030,2sleep30-21swapper/319:35:243
36508042350,1sleep10-21swapper/122:26:101
35482622330,2sleep30-21swapper/321:30:093
25010912917,4phc2sys0-21swapper/323:05:193
3363809992824,2cyclictest0-21swapper/123:20:011
3363808992616,6cyclictest3813332-21irqcore00:00:260
3363808992611,1cyclictest3811766-21ssh00:00:010
25010912518,3phc2sys0-21swapper/321:25:343
25010912517,2phc2sys0-21swapper/323:54:153
25010912514,2phc2sys0-21swapper/321:48:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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