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2026-03-13 - 12:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Fri Mar 13, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212464921080,2sleep10-21swapper/100:11:431
191060621050,1sleep11910607-21aten_repower_cu22:11:351
18310662940,2sleep1341rcuc/121:26:381
16880992790,2sleep30-21swapper/319:36:363
20868112390,2sleep20-21swapper/223:51:002
1654802992414,5cyclictest2902298rtkit-daemon21:12:080
2649091220,2phc2sys0-21swapper/322:11:353
20040472220,2sleep20-21swapper/223:01:462
1654803992218,3cyclictest1286-21avahi-daemon23:05:021
1654804992119,1cyclictest0-21swapper/219:15:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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