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2025-09-13 - 09:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Sat Sep 13, 2025 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
354429621080,1sleep10-21swapper/120:09:391
35108222950,1sleep10-21swapper/119:39:411
37824612750,2sleep30-21swapper/322:44:343
35315632310,2sleep30-21swapper/319:59:393
347289899311,18cyclictest3831581-21ssh23:10:010
3472898992715,8cyclictest3646524-21sendmail_mailqu21:24:460
3472899992620,2cyclictest176650irq/121-eno122:35:011
3472898992617,8cyclictest3752755-21/usr/sbin/munin22:25:010
347289899256,12cyclictest0-21swapper/023:49:400
3472898992512,9cyclictest3934913-21kthreadcore00:09:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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