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2026-06-12 - 02:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Thu Jun 11, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
104695221040,2sleep30-21swapper/310:55:283
8914842320,1sleep00-21swapper/009:10:280
10207392300,2sleep20-21swapper/210:40:242
737527992922,2cyclictest67250irq/126-eno109:45:011
737527992922,2cyclictest67250irq/126-eno109:45:011
737527992722,1cyclictest9314031systemd-run09:40:011
737527992615,6cyclictest0-21swapper/109:35:031
737527992522,2cyclictest916364-21dump-pmu-power09:30:011
737526992522,2cyclictest886926-21grep09:10:000
737526992514,6cyclictest918164-21irqrtprio09:30:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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