You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-12 - 03:34
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Fri Jun 12, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20371092990,3sleep02037107-21sed23:30:330
19659722670,1sleep11965971-21ssh22:45:251
20318932310,2sleep30-21swapper/323:30:203
1675852992517,7cyclictest2113102-21acpi00:25:180
1675852992413,6cyclictest0-21swapper/021:50:030
1675852992315,7cyclictest1748128-21kthreadcore20:05:280
1675852992314,5cyclictest2020657-21kthreadcore23:20:300
1675852992314,5cyclictest2020657-21kthreadcore23:20:300
1675853992219,2cyclictest1-21systemd19:20:011
1675853992216,2cyclictest1675850-21cyclictest23:55:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional