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2026-07-03 - 10:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jul 03, 2026 00:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
331834621680,2sleep30-21swapper/322:05:023
329114421150,2sleep30-21swapper/321:49:513
329114421150,2sleep30-21swapper/321:49:513
348096821080,2sleep03480971-21grep23:55:010
35184852580,1sleep03518483-21ssh00:20:180
35184852580,1sleep03518483-21ssh00:20:180
308766299288,4cyclictest0-21swapper/220:10:002
308766099274,4cyclictest0-21swapper/023:24:540
308766099272,19cyclictest3120358-21users19:35:010
308766099272,17cyclictest1242-21mta-sts-daemon23:32:410
3087660992620,5cyclictest660-21dbus-daemon21:40:010
3087660992618,4cyclictest191rcu_preempt22:14:550
308766099255,8cyclictest3221745-21cut20:59:550
308766099253,7cyclictest3294081-21kthreadcore21:49:550
308766099253,7cyclictest3294081-21kthreadcore21:49:550
3087660992513,11cyclictest3425302-21kthreadcore23:19:550
3087660992511,9cyclictest0-21swapper/021:54:520
3087661992421,2cyclictest3428732-21systemctl23:20:011
308766099246,13cyclictest3245949-21/usr/sbin/munin21:19:540
308766099245,8cyclictest3147462-21cut19:59:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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