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2026-06-18 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jun 18, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14244232990,2sleep30-21swapper/309:30:163
15786902960,2sleep30-21swapper/311:15:133
15696082950,1sleep10-21swapper/111:07:581
12683812380,1sleep10-21swapper/107:25:191
15042392340,2sleep30-21swapper/310:25:033
1244455992421,2cyclictest1688441-21grep12:30:020
1244457992320,1cyclictest0-21swapper/210:10:022
1244457992219,1cyclictest0-21swapper/211:10:012
1244455992219,2cyclictest0-21swapper/011:55:120
1244455992112,5cyclictest0-21swapper/011:05:010
1244457992017,1cyclictest0-21swapper/208:25:002
1244456992017,2cyclictest1542299-21cut10:50:161
1244456992017,2cyclictest1457608-21mailstats09:50:221
1244456992017,2cyclictest1250503-21latency_hist07:15:011
124445599209,6cyclictest0-21swapper/009:55:130
1244455992016,2cyclictest0-21swapper/010:45:020
1244455992012,4cyclictest1579325-21kthreadcore11:15:170
1244457991917,1cyclictest0-21swapper/211:20:012
1244457991916,1cyclictest0-21swapper/211:55:022
1244457991916,1cyclictest0-21swapper/210:35:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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