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2026-08-19 - 19:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Aug 19, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138019821190,2sleep30-21swapper/310:55:023
138019821190,2sleep30-21swapper/310:55:023
123674621000,2sleep30-21swapper/309:15:303
12915912970,2sleep30-21swapper/309:55:063
14762502700,1sleep11476249-21ssh11:58:571
1080197992922,2cyclictest69250irq/121-eno110:45:131
1080196992815,8cyclictest1224780-21irqrtprio09:10:090
1080196992716,6cyclictest0-21swapper/008:35:010
1080197992614,6cyclictest0-21swapper/109:30:101
1080196992616,6cyclictest1233036-21kthreadcore09:15:110
1080197992514,6cyclictest0-21swapper/111:50:021
1080197992514,6cyclictest0-21swapper/111:05:101
1080197992514,3cyclictest1306-21mta-sts-daemon10:15:021
1080197992513,3cyclictest0-21swapper/110:04:481
1080197992421,2cyclictest664-21dbus-daemon11:25:011
1080197992421,2cyclictest1-21systemd12:40:011
1080196992413,6cyclictest0-21swapper/009:55:010
1080196992413,6cyclictest0-21swapper/009:55:010
3240591230,7phc2sys0-21swapper/311:34:483
1080197992314,5cyclictest1034-21runrttasks09:21:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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