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2026-05-11 - 07:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon May 11, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
320691321590,2sleep30-21swapper/300:30:203
321953921170,2sleep30-21swapper/300:40:023
31755742950,2sleep30-21swapper/300:10:203
29062322880,2sleep30-21swapper/321:11:353
31125362690,1sleep13112535-21ssh23:29:581
31125362690,1sleep13112535-21ssh23:29:581
31888372380,1sleep20-21swapper/200:20:012
30531622360,2sleep20-21swapper/222:50:182
28206642300,1sleep10-21swapper/120:05:211
2747080992817,7cyclictest3200731-21kthreadcore00:25:220
30429342260,0sleep13042933-21ssh22:40:471
2747080992514,6cyclictest2918910-21kthreadcore21:20:210
2747081992421,2cyclictest2907487-21grep21:15:011
2747082992219,1cyclictest0-21swapper/222:15:002
2747082992219,1cyclictest0-21swapper/200:30:012
2747080992219,2cyclictest3028935-21apt-key22:35:010
2747080992219,2cyclictest2968163-21awk21:55:000
2747080992219,2cyclictest2899885-21sh21:10:010
2747082992118,1cyclictest0-21swapper/221:00:002
2747082992118,1cyclictest0-21swapper/221:00:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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