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2026-07-25 - 05:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jul 25, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
45803421020,2sleep0241rcuc/020:56:010
4166512960,2sleep20-21swapper/220:25:012
7365532270,1sleep20-21swapper/200:06:052
323382992713,10cyclictest0-21swapper/023:15:020
5642592250,2sleep30-21swapper/322:10:583
323382992514,6cyclictest0-21swapper/022:25:020
323382992410,10cyclictest0-21swapper/022:40:010
323384992319,2cyclictest0-21swapper/219:20:002
323383992320,2cyclictest0-21swapper/120:50:031
323383992317,2cyclictest69250irq/121-eno122:25:581
323383992312,2cyclictest723548-21munin-run00:00:011
323382992315,7cyclictest699687-21sensors_temp23:41:030
323384992219,1cyclictest0-21swapper/200:15:012
323383992214,3cyclictest535744-21kthreadcore21:51:001
323384992117,2cyclictest0-21swapper/223:32:072
323384992116,3cyclictest0-21swapper/200:00:022
323383992116,3cyclictest268-21systemd-journal22:55:001
32338299219,6cyclictest0-21swapper/022:10:510
323382992112,5cyclictest0-21swapper/023:25:010
1157598210,3rtkit-daemon1307-21mta-sts-daemon00:19:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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