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2026-07-18 - 18:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jul 18, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95873321340,2sleep0676-21mta-sts-daemon10:16:160
81179321030,2sleep30-21swapper/308:31:143
710806992617,7cyclictest16-21ksoftirqd/011:15:030
710806992320,2cyclictest1073623-21latency_hist11:35:000
710806992315,3cyclictest16-21ksoftirqd/012:35:020
710806992314,5cyclictest951349-21kthreadcore10:11:160
71080699230,3cyclictest0-21swapper/009:01:090
710807992218,3cyclictest718661-21sort07:15:031
710806992218,2cyclictest191rcu_preempt07:30:010
710806992214,3cyclictest16-21ksoftirqd/009:10:010
710807992118,2cyclictest918248-21ssh09:50:011
71080699217,5cyclictest1126777-21ssh12:11:100
710806992118,2cyclictest1-21systemd07:20:010
710806992115,3cyclictest16-21ksoftirqd/008:00:010
710806992113,3cyclictest896668-21/usr/sbin/munin09:36:200
710806992111,1cyclictest191rcu_preempt10:46:150
710806992110,1cyclictest17750irq/127-ahci[0000:00:17.0]12:00:010
71080699210,11cyclictest1097431-21sed11:51:130
710808992018,1cyclictest0-21swapper/210:50:022
710808992017,1cyclictest0-21swapper/209:10:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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