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2026-08-29 - 18:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 29, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13785121610,2sleep30-21swapper/312:19:483
410323921140,2sleep00-21swapper/010:09:520
14537221000,2sleep30-21swapper/312:22:163
275562910,2sleep30-21swapper/311:14:573
40773732600,2sleep20-21swapper/209:54:552
3839199992715,7cyclictest86037-21kthreadcore11:49:530
383920199266,5cyclictest0-21swapper/111:44:311
3839199992410,5cyclictest0-21swapper/012:40:010
997762230,2sleep20-21swapper/211:55:012
3839201992317,2cyclictest82050irq/121-eno110:49:491
383919999235,6cyclictest0-21swapper/009:29:310
3839199992313,6cyclictest1011-21gdbus10:50:020
383919999229,5cyclictest134352-21missed_timers12:14:570
383919999227,6cyclictest0-21swapper/012:09:300
383919999227,2cyclictest0-21swapper/009:59:310
383919999226,6cyclictest0-21swapper/011:19:310
3839203992117,2cyclictest0-21swapper/209:15:012
383920199219,7cyclictest141647-21kthreadcore12:19:541
383920199212,12cyclictest42799-21cut11:24:531
3839201992110,7cyclictest4089628-21munin-run10:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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