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2026-06-25 - 18:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jun 25, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
191001221090,2sleep20-21swapper/209:20:012
19476922990,2sleep30-21swapper/309:45:033
18939612820,2sleep30-21swapper/309:05:113
21981582800,2sleep30-21swapper/312:30:123
21278582330,2sleep10-21swapper/111:45:051
19112342330,3sleep30-21swapper/309:20:063
1750036993324,2cyclictest1864866-21fschecks_count08:45:021
1750036992923,2cyclictest67250irq/126-eno111:25:011
1750038992516,6cyclictest0-21swapper/208:00:012
1750035992418,2cyclictest17750irq/132-ahci[0000:00:17.0]09:45:010
492398230,6rtkit-daemon1242-21mta-sts-daemon09:06:211
1750038992320,1cyclictest0-21swapper/212:35:022
1750038992320,1cyclictest0-21swapper/211:35:012
1750036992317,2cyclictest67250irq/126-eno110:15:061
1750035992320,2cyclictest1932630-21cut09:35:020
1750035992315,7cyclictest2023977-21kthreadcore10:35:060
1750035992313,5cyclictest0-21swapper/009:15:020
1750036992219,2cyclictest2014078-21cstates10:30:021
1750036992219,2cyclictest2014078-21cstates10:30:021
1750035992219,2cyclictest1999237-21cstates10:20:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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