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2026-07-24 - 14:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jul 24, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289915021560,1sleep02899153-21cut22:21:000
283246821490,1sleep02832471-21irqrtprio21:35:590
267693921080,2sleep30-21swapper/319:31:073
29198432870,1sleep3551rcuc/322:35:023
29048812710,0sleep12904884-21cut22:25:021
28966952710,1sleep12896694-21ssh22:18:131
29568032280,2sleep11176268-1atop23:00:011
3240591271,6phc2sys0-21swapper/323:25:533
2644792992522,2cyclictest664-21dbus-daemon00:40:020
2644792992421,2cyclictest2644787-21cyclictest00:35:020
2644793992320,2cyclictest2874991-21grep22:05:021
2644792992312,6cyclictest0-21swapper/023:40:030
2644793992219,2cyclictest1-21systemd00:30:011
2644793992216,2cyclictest69250irq/121-eno123:14:071
2644793992216,2cyclictest69250irq/121-eno122:00:011
2644793992214,3cyclictest759-1atopacctd21:16:031
2644792992215,6cyclictest3004371-21kthreadcore23:31:010
2644792992212,6cyclictest0-21swapper/023:50:010
3240591212,2phc2sys0-21swapper/319:50:563
28116272210,2sleep30-21swapper/321:21:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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