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2026-08-30 - 21:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Aug 30, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209562521090,2sleep30-21swapper/310:23:153
1801795993010,6cyclictest0-21swapper/009:34:420
1801795992911,2cyclictest0-21swapper/010:49:500
20130752260,2sleep30-21swapper/309:34:533
180179599267,7cyclictest0-21swapper/010:45:010
1801801992517,2cyclictest82050irq/121-eno111:49:531
180179599259,5cyclictest2078966-21cstates10:14:460
180179599259,5cyclictest2021012-21kthreadcore09:39:540
180179599259,15cyclictest778-21dbus-daemon12:10:020
180179599236,6cyclictest0-21swapper/011:59:290
180179599233,2cyclictest0-21swapper/009:14:290
1801795992313,2cyclictest778-21dbus-daemon09:20:030
1801795992313,2cyclictest778-21dbus-daemon09:20:030
1801795992312,3cyclictest1857822-21kthreadcore07:49:510
1801795992312,3cyclictest1826858-21irqrtprio07:29:510
1801795992311,3cyclictest2155439-21pmu-power10:54:560
1801795992311,3cyclictest2155439-21pmu-power10:54:560
1801795992311,3cyclictest1870144-21kthreadcore07:59:530
180179599229,7cyclictest0-21swapper/011:19:280
180179599221,5cyclictest2314853-21tr12:24:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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