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2026-07-29 - 23:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 29, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46173021120,1sleep10-21swapper/109:06:031
317764992924,1cyclictest69250irq/121-eno110:16:031
3458402280,1sleep1345844-21cat07:31:011
317763992313,6cyclictest0-21swapper/012:00:020
317764992215,3cyclictest558538-21kthreadcore10:11:031
317765992118,1cyclictest0-21swapper/209:40:002
317763992119,1cyclictest0-21swapper/007:15:020
317763992118,2cyclictest518093-21/usr/sbin/munin09:45:010
317763992113,4cyclictest0-21swapper/010:40:020
317763992110,6cyclictest0-21swapper/010:20:390
317765992012,3cyclictest0-21swapper/211:15:402
317765992010,4cyclictest0-21swapper/209:34:322
317764992017,2cyclictest621867-21grep10:55:011
317764992017,2cyclictest0-21swapper/108:16:011
31776399208,4cyclictest1309-21mta-sts-daemon11:04:380
317763992014,5cyclictest750031-21kthreadcore12:21:020
317763992011,5cyclictest0-21swapper/010:30:010
317763992010,5cyclictest0-21swapper/012:06:350
317763992010,5cyclictest0-21swapper/009:26:020
31776399200,4cyclictest0-21swapper/010:40:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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