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2026-05-14 - 00:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed May 13, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
350241621010,1sleep13502417-21latency_hist08:55:011
34689932980,2sleep30-21swapper/308:25:183
3367963992522,2cyclictest3580020-21wc09:45:211
3367963992320,2cyclictest0-21swapper/112:10:011
3367962992320,2cyclictest3528640-21idleruntime-cro09:15:000
3367962992320,2cyclictest1-21systemd07:15:010
3367962992219,2cyclictest3755764-21mailstats11:40:220
3367962992212,6cyclictest0-21swapper/011:20:180
383433398210,4rtkit-daemon3851702-21mta-sts-daemon09:40:480
3367964992119,1cyclictest0-21swapper/209:00:012
3367963992118,2cyclictest1326-21systemd-logind10:35:011
3367963992113,4cyclictest191rcu_preempt08:30:001
336796399210,2cyclictest3750080-21latency_hist11:40:001
336796299218,5cyclictest0-21swapper/011:25:090
3367962992118,2cyclictest3559076-21grep09:35:000
3367962992110,6cyclictest0-21swapper/010:55:220
34782502200,3sleep30-21swapper/308:35:123
3367964992017,1cyclictest0-21swapper/211:35:142
3367964992017,1cyclictest0-21swapper/210:55:212
3367963992017,2cyclictest3773071-21/usr/sbin/munin11:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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