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2026-07-28 - 15:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jul 28, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291313521430,3sleep30-21swapper/310:27:563
26549642930,1sleep00-21swapper/007:15:040
30158872460,1sleep13015891-21tr11:36:071
28998472370,3sleep12899851-21cpuspeed_turbos10:20:441
2646387992826,1cyclictest0-21swapper/110:00:011
264638699233,5cyclictest3078622-21/usr/sbin/munin12:21:060
2646386992311,7cyclictest2928460-21ssh10:38:340
264638699229,8cyclictest2759694-21irqcore08:40:500
264638699224,7cyclictest3087287-21grep12:26:040
264638699223,6cyclictest2789131-21munin-run09:05:010
264638699223,13cyclictest2777264-21/usr/sbin/munin08:55:420
264638699223,12cyclictest2984520-21cat11:16:110
2646386992214,4cyclictest0-21swapper/010:30:010
2646386992211,3cyclictest1300-21mta-sts-daemon09:40:310
264638899212,8cyclictest0-21swapper/212:10:012
2646387992115,2cyclictest491rcuog/211:01:351
264638699214,7cyclictest3055607-21sh12:04:110
264638699214,7cyclictest3003346-21runrttasks11:29:340
264638699214,7cyclictest2827622-21tr09:30:490
264638699214,7cyclictest0-21swapper/010:30:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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