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2026-05-15 - 09:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri May 15, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251648121940,2sleep30-21swapper/300:25:163
20621252990,1sleep10-21swapper/119:10:031
21165092970,1sleep10-21swapper/119:50:141
22707462860,2sleep20-21swapper/221:45:142
23166762250,2sleep30-21swapper/322:15:133
2061850992513,8cyclictest2491495-21cstates00:10:100
2061850992513,8cyclictest0-21swapper/000:00:010
2061851992421,2cyclictest3824500-21cron23:10:001
2061850992418,5cyclictest2269536-21systemd-run21:45:010
2061850992415,8cyclictest2373946-21/usr/sbin/munin22:50:170
2061850992411,8cyclictest0-21swapper/022:15:140
2061850992410,9cyclictest0-21swapper/022:00:070
2061850992410,13cyclictest2410580-21kthreadcore23:15:150
2061850992314,8cyclictest2248707-21kthreadcore21:30:150
206185099231,16cyclictest0-21swapper/000:30:070
2061850992310,8cyclictest0-21swapper/022:25:010
2061850992310,8cyclictest0-21swapper/021:25:150
206185099230,3cyclictest2237962-21ssh21:23:340
206185099230,17cyclictest2215198-21diskmemload22:25:050
206185199220,21cyclictest2299936-21ssh22:05:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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