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2026-08-30 - 07:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Aug 30, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
99774021030,1sleep1997744-21cut22:14:531
7458622260,2sleep0745865-21kthreadcore19:29:540
7458622260,2sleep0745865-21kthreadcore19:29:540
7427882260,2sleep20-21swapper/219:24:592
71957599222,2cyclictest82050irq/121-eno122:46:391
71957499229,7cyclictest0-21swapper/023:44:310
71957499225,2cyclictest0-21swapper/023:59:300
719576992017,1cyclictest0-21swapper/222:18:372
719575992010,4cyclictest501rcuop/200:19:291
71957499209,7cyclictest0-21swapper/023:55:010
7651482190,1sleep1765147-21hddtemp_smartct19:44:501
719576991916,1cyclictest0-21swapper/200:07:372
719575991915,3cyclictest1177059-21kthreadcore23:54:551
719575991914,4cyclictest24617-21JS14:54:061
719575991911,3cyclictest1107275-21kthreadcore23:14:561
719574991913,2cyclictest17850irq/132-ahci[0000:00:17.0]19:55:010
71957499190,17cyclictest1001220-21kthreadcore22:14:550
2213291190,3phc2sys0-21swapper/323:14:403
2213291190,2phc2sys0-21swapper/321:41:413
71957699181,8cyclictest0-21swapper/222:39:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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