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2025-12-07 - 00:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Dec 06, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
104380121740,2sleep30-21swapper/312:05:013
76264521010,1sleep10-21swapper/109:22:111
5969372880,2sleep30-21swapper/307:15:023
7683982720,1sleep00-21swapper/009:25:150
7683982720,1sleep00-21swapper/009:25:150
6917422270,2sleep20-21swapper/208:30:152
589219992616,5cyclictest1700-21systemd-logind08:55:001
589218992617,8cyclictest1803-21gdbus10:50:020
589218992517,4cyclictest959828-21kthreadcore11:15:150
589218992411,7cyclictest0-21swapper/012:20:050
589218992411,7cyclictest0-21swapper/012:20:050
589219992317,2cyclictest170550irq/121-eno110:10:211
589219992317,2cyclictest170550irq/121-eno110:10:211
589219992315,3cyclictest927015-21wc10:55:191
589218992312,6cyclictest926581-21kthreadcore10:55:180
589218992312,6cyclictest0-21swapper/009:50:080
589218992312,5cyclictest1069902-21wc12:20:010
58921999229,3cyclictest0-21swapper/112:35:011
58921999227,11cyclictest491rcuog/208:40:071
589219992211,3cyclictest983697-21fschecks_time11:30:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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