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2026-01-28 - 07:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jan 28, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181428021100,1sleep10-21swapper/122:27:421
16967112910,2sleep30-21swapper/321:22:353
1529275992923,2cyclictest134050irq/121-eno121:57:421
2649091250,2phc2sys0-21swapper/300:09:463
1529275992515,3cyclictest1770122-21kthreadcore22:02:451
1529275992418,2cyclictest134050irq/121-eno122:55:021
1529275992313,3cyclictest1426-21gdbus22:45:011
1529274992320,2cyclictest1748079-21gpgv21:50:010
1529274992320,2cyclictest1586099-21wc19:55:000
1529274992320,2cyclictest1-21systemd19:20:000
1529276992219,1cyclictest0-21swapper/221:20:002
1529276992219,1cyclictest0-21swapper/219:45:002
1529276992219,1cyclictest0-21swapper/219:45:002
152927599226,5cyclictest1984155-21cat00:02:421
1529275992219,2cyclictest1529272-21cyclictest21:27:481
1529275992214,3cyclictest0-21swapper/100:30:011
1529275992212,2cyclictest1975736-21kthreadcore23:57:431
1529275992212,2cyclictest1975736-21kthreadcore23:57:431
1529274992216,5cyclictest1882012-21latency_hist23:05:020
1529274992210,7cyclictest0-21swapper/022:12:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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