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2026-08-11 - 18:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Aug 11, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299401921760,2sleep30-21swapper/307:10:303
299401921760,2sleep30-21swapper/307:10:303
321357121130,2sleep23213559-21turbostat10:00:012
34057452720,1sleep03405743-21ssh12:07:440
2990409993024,5cyclictest3265778-21grep10:35:010
2990409992823,4cyclictest3221397-21ssh10:05:020
299040999279,11cyclictest0-21swapper/011:15:080
2990413992513,7cyclictest0-21swapper/112:20:351
299040999259,10cyclictest0-21swapper/011:40:080
299040999257,8cyclictest3338666-21diskmemload11:21:420
299040999252,4cyclictest3317620-21grep11:10:010
2990409992520,4cyclictest2996766-21missed_timers07:15:020
2990409992520,4cyclictest2996766-21missed_timers07:15:020
2990409992515,9cyclictest3173307-21kthreadcore09:30:310
2990409992511,9cyclictest0-21swapper/011:00:020
2990409992511,10cyclictest0-21swapper/010:35:310
2990409992510,10cyclictest0-21swapper/010:45:020
2990413992421,2cyclictest0-21swapper/109:10:081
2990413992413,4cyclictest1309-21mta-sts-daemon09:47:281
299040999248,9cyclictest0-21swapper/009:45:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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