You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-18 - 06:35
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jun 18, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6817072290,2sleep0241rcuc/023:40:180
6170602240,0sleep0617059-21unixbench_singl22:55:250
307106992421,2cyclictest1-21systemd21:10:010
307106992415,5cyclictest509687-21kthreadcore21:45:160
307107992320,2cyclictest699808-21cron23:55:011
307106992313,6cyclictest0-21swapper/022:00:020
307107992215,2cyclictest492398rtkit-daemon21:35:491
307106992219,2cyclictest537640-21systemd22:05:020
3153791210,2phc2sys0-21swapper/323:24:363
307106992112,8cyclictest557837-21unixbench-2d22:15:240
3153791201,5phc2sys0-21swapper/319:05:103
307107992017,2cyclictest765-1atopacctd23:40:021
307107992017,2cyclictest707196-21cron00:00:011
30710699208,5cyclictest746937-21kthreadcore00:25:180
307106992017,2cyclictest744020-21cron00:25:010
307106992017,2cyclictest633698-21sh23:10:020
307106992017,2cyclictest313515-21cpuspeed19:15:020
307108991917,1cyclictest0-21swapper/223:10:022
307108991915,2cyclictest0-21swapper/200:38:392
307108991915,2cyclictest0-21swapper/200:38:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional