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2025-12-03 - 22:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Dec 03, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32031782980,1sleep10-21swapper/108:10:151
33154612360,2sleep30-21swapper/309:30:203
3126553992623,2cyclictest3126550-21cyclictest11:10:001
3126552992614,5cyclictest3608261-21cut12:20:020
3126552992514,4cyclictest3460008-21cpuspeed_turbos10:55:110
3126552992511,5cyclictest0-21swapper/010:30:010
3126553992421,2cyclictest1652-1atopacctd10:10:271
3126553992416,3cyclictest0-21swapper/112:25:201
312655299249,6cyclictest0-21swapper/011:05:180
3126552992422,1cyclictest3269545-21gpgconf09:05:010
3126552992415,1cyclictest0-21swapper/008:55:260
3126552992414,5cyclictest3444662-21kthreadcore10:45:200
3126553992320,2cyclictest3126550-21cyclictest11:00:001
3126553992317,2cyclictest170550irq/121-eno109:10:011
3126553992314,4cyclictest170550irq/121-eno109:20:011
3126552992313,1cyclictest0-21swapper/007:45:180
3126552992310,5cyclictest3355894-21if_enp1s009:55:200
3126553992214,2cyclictest170550irq/121-eno109:30:181
3126553992212,4cyclictest3339799-21cut09:45:171
312655299228,4cyclictest0-21swapper/010:20:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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