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2026-09-13 - 07:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Sep 13, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
152400221070,2sleep30-21swapper/321:34:353
18249912850,2sleep30-21swapper/300:24:323
15737942830,2sleep30-21swapper/322:04:293
1313838992418,2cyclictest82050irq/121-eno122:14:311
131383899240,18cyclictest1718957-21cut23:24:321
1313837992320,2cyclictest24617-21JS14:54:060
1313837992312,5cyclictest1672587-21kthreadcore22:59:320
1313837992311,5cyclictest1586477-21kthreadcore22:09:350
2447398220,3rtkit-daemon24472-21rtkit-daemon23:08:481
1313838992215,2cyclictest82050irq/121-eno100:34:321
1313837992210,7cyclictest1836414-21grep00:29:390
1313838992118,2cyclictest1544285-21ssh21:45:021
1313838992115,2cyclictest82050irq/121-eno123:39:281
131383799217,7cyclictest0-21swapper/022:34:400
131383799217,6cyclictest0-21swapper/023:15:020
1313837992116,1cyclictest0-21swapper/019:49:090
131383899209,3cyclictest0-21swapper/123:15:031
1313838992010,4cyclictest1830746-21aten2.4-expect00:29:201
1313838992010,4cyclictest1314649-21seq19:14:271
131383799206,2cyclictest0-21swapper/023:39:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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