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2026-09-04 - 18:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Sep 04, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
761521170,2sleep30-21swapper/307:29:213
7560821140,2sleep30-21swapper/308:14:463
48484921110,2sleep20-21swapper/212:19:462
12467521100,1sleep00-21swapper/008:50:020
4177684992213,5cyclictest245355-21kthreadcore10:04:420
417768499208,7cyclictest0-21swapper/010:35:030
417768499207,7cyclictest0-21swapper/010:39:390
417768499205,2cyclictest0-21swapper/008:44:220
4177684992013,6cyclictest214051-21systemd-run09:45:010
4177684992011,5cyclictest237225-21kthreadcore09:59:460
417768699197,4cyclictest0-21swapper/111:09:261
417768699190,1cyclictest124496-21appstreamcli08:50:011
417768699190,19cyclictest0-21swapper/111:57:071
417768499197,7cyclictest0-21swapper/010:50:020
4177684991915,3cyclictest203726-21kthreadcore09:39:450
417768499191,3cyclictest523119-21ssh12:39:560
417768799180,14cyclictest0-21swapper/208:44:222
4177686991815,2cyclictest24648-21gmain10:58:151
417768499189,8cyclictest502262-21kthreadcore12:29:430
417768499189,4cyclictest0-21swapper/009:19:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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