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2026-08-25 - 23:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Aug 25, 2026 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
396618321110,2sleep13622453-21cyclictest10:50:031
396618321110,2sleep13622453-21cyclictest10:50:031
382038221070,2sleep30-21swapper/309:29:553
36394252960,1sleep10-21swapper/107:20:031
36575972950,2sleep30-21swapper/307:35:003
38659232800,1sleep10-21swapper/109:54:591
40854502400,2sleep14085440-21ssh11:59:501
39003452330,1sleep20-21swapper/210:14:562
37024442320,1sleep20-21swapper/208:09:542
41242212290,2sleep04124029-21ssh12:20:020
3622470992511,3cyclictest3823938-21kthreadcore09:30:031
37539072240,1sleep1341rcuc/108:45:001
3622462992418,2cyclictest82050irq/121-eno109:35:020
3622462992415,5cyclictest3839072-21kthreadcore09:40:010
3622470992313,3cyclictest3890591-21/usr/sbin/munin10:10:001
3622462992313,6cyclictest4037990-21phc2sys11:30:020
3622462992312,7cyclictest4070537-21cut11:50:010
41118842220,2sleep20-21swapper/212:14:502
3622470992212,3cyclictest4146704-21runrttasks12:34:011
3622470992212,3cyclictest3826389-21/usr/sbin/munin09:30:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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