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2026-07-23 - 11:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 23, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79936221580,1sleep0799366-21kthreadcore19:16:050
119746621080,3sleep30-21swapper/300:16:023
107273721040,2sleep1690-21rs:main1
107273721040,2sleep1690-21rs:main1
104525821020,1sleep00-21swapper/022:22:280
117638921010,2sleep20-21swapper/200:00:012
786632992814,3cyclictest0-21swapper/123:15:581
786632992720,6cyclictest1222962-21/usr/sbin/munin00:35:001
78663099270,5cyclictest491rcuog/222:41:480
786632992615,3cyclictest1034-21runrttasks22:14:571
78663099260,3cyclictest1080492-21ssh22:55:550
786632992522,2cyclictest801012-21munin-plugin-st19:20:011
786632992413,6cyclictest0-21swapper/121:35:021
78663099249,8cyclictest831827-21head19:45:580
78663099249,11cyclictest0-21swapper/023:47:530
78663099244,3cyclictest1118805-21kthreadcore23:21:030
786630992419,4cyclictest892327-21munin-run20:35:010
786630992412,8cyclictest1149788-21kthreadcore23:41:050
786632992320,2cyclictest1300-21mta-sts-daemon20:40:021
786632992312,6cyclictest0-21swapper/121:14:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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