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2026-05-21 - 08:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu May 21, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148464821620,3sleep30-21swapper/300:20:063
10849162970,1sleep01084919-21cut19:44:590
13978272700,1sleep01397825-21ssh23:24:070
1044679992926,2cyclictest0-21swapper/119:40:011
1044678992617,8cyclictest0-21swapper/023:00:010
1044678992614,4cyclictest1451847-21ssh00:00:010
1044679992522,2cyclictest1444165-21aten_repower_vo23:55:011
1044679992420,2cyclictest0-21swapper/122:30:011
1044678992416,6cyclictest1497172-21/usr/sbin/munin00:30:030
1044679992320,2cyclictest1398515-21cpuspeed23:25:001
1044678992320,2cyclictest1375593-21cpu23:10:010
1044678992320,2cyclictest1199798-21latency_hist21:15:000
13907612220,2sleep10-21swapper/123:19:591
1044680992219,1cyclictest0-21swapper/221:50:012
1044679992220,1cyclictest1223252-21apt21:30:011
1044679992219,2cyclictest0-21swapper/100:30:021
1044678992219,2cyclictest1091764-21fschecks_count19:50:010
1044678992215,5cyclictest1494349-21kthreadcore00:25:070
2649091210,2phc2sys0-21swapper/322:45:033
1044680992118,1cyclictest0-21swapper/223:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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