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2026-05-10 - 13:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun May 10, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126905221090,2sleep30-21swapper/300:25:013
115594521060,2sleep30-21swapper/323:10:183
9798212330,2sleep1979820-21ssh21:15:201
818124992623,1cyclictest0-21swapper/222:25:022
818122992516,5cyclictest1241333-21kthreadcore00:05:220
818123992413,4cyclictest1290-21dbus-daemon00:05:001
818124992212,1cyclictest0-21swapper/223:55:012
818124992212,1cyclictest0-21swapper/219:55:012
81812299229,7cyclictest0-21swapper/023:20:160
818122992214,7cyclictest1196473-21kthreadcore23:35:220
818122992115,5cyclictest1226849-21kthreadcore23:55:210
818122992110,7cyclictest1285891-21irqrtprio00:35:200
383433398210,5rtkit-daemon3851705-21mta-sts-daemon00:14:200
8351842200,1sleep016-21ksoftirqd/019:20:210
818124992017,1cyclictest0-21swapper/220:30:012
818124992012,1cyclictest0-21swapper/200:10:002
818123992017,2cyclictest1268937-21systemd-run00:25:011
818123992017,2cyclictest0-21swapper/123:35:011
818123992017,2cyclictest0-21swapper/120:10:011
81812299209,6cyclictest0-21swapper/021:15:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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