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2026-06-26 - 07:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jun 26, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300974121090,1sleep10-21swapper/123:15:091
288052021000,2sleep30-21swapper/321:50:063
29891612990,1sleep10-21swapper/123:02:471
2675116992825,2cyclictest2975133-21grep22:55:010
2675116992817,6cyclictest3075776-21kthreadcore00:00:110
2675116992712,6cyclictest0-21swapper/000:39:590
2675118992622,2cyclictest0-21swapper/200:39:592
2675117992623,2cyclictest0-21swapper/120:50:021
2675116992623,2cyclictest2795649-21irqcore20:50:020
2675116992615,4cyclictest2930663-21munin-plugin-st22:25:000
2675117992522,2cyclictest3102645-21latency_hist00:20:021
2675117992522,2cyclictest2997635-21latency_hist23:10:011
267511699259,6cyclictest0-21swapper/022:05:000
2675116992522,2cyclictest2740314-21df20:05:010
2675118992421,1cyclictest0-21swapper/223:20:012
2675116992421,2cyclictest2990396-21ls23:05:010
2675118992320,1cyclictest0-21swapper/221:05:002
2675118992320,1cyclictest0-21swapper/221:00:002
2675117992320,2cyclictest2703759-21systemd19:35:021
2675117992313,4cyclictest0-21swapper/122:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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