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2026-06-04 - 03:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jun 04, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2488776992815,9cyclictest2659479-21mailstats22:09:510
2488776992614,8cyclictest2762880-21kthreadcore23:19:460
2488776992614,8cyclictest2762880-21kthreadcore23:19:460
2488776992519,5cyclictest2840498-21systemd-journal21:00:000
2488776992414,9cyclictest2681158-21kthreadcore22:24:450
248877699240,3cyclictest2607992-21ssh21:36:250
2649191230,2ptp4l0-21swapper/323:10:003
2488786992316,3cyclictest0-21swapper/219:29:352
248877699238,9cyclictest2745866-21sort23:09:430
2488776992317,5cyclictest3827634-1atopacctd20:10:020
2488776992317,5cyclictest1326-21systemd-logind22:55:030
248877699231,4cyclictest2519566-21munin-run19:50:010
2488776992314,8cyclictest2884257-21kthreadcore00:39:450
2488776992314,8cyclictest2675138-21latency_hist22:20:010
2488776992311,8cyclictest2830191-21kthreadcore00:04:450
2488776992311,8cyclictest1290-21dbus-daemon23:55:000
248878699228,9cyclictest0-21swapper/222:00:012
2488786992214,6cyclictest0-21swapper/222:09:402
2488786992213,3cyclictest0-21swapper/221:54:382
2488776992211,8cyclictest2648337-21kthreadcore22:04:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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