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2026-07-31 - 23:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jul 31, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25262621620,2sleep30-21swapper/312:08:043
411128521200,1sleep10-21swapper/108:10:591
3852721010,2sleep30-21swapper/309:45:033
1592822770,2sleep1159283-21cut11:05:571
683902700,1sleep068388-21ssh10:05:240
4032008993128,2cyclictest90409-21latency_hist10:20:010
2205662300,2sleep1220426-21ssh11:45:571
4032009992315,3cyclictest0-21swapper/109:35:021
4032008992311,4cyclictest684-21systemd-logind10:00:020
4032010992219,1cyclictest0-21swapper/212:00:002
4032008992215,6cyclictest4091627-21cut07:55:580
4032009992118,2cyclictest684-21systemd-logind07:10:011
4032008992112,3cyclictest9147-21/usr/sbin/munin09:25:540
4032010992010,5cyclictest0-21swapper/208:20:022
4032009992013,3cyclictest249345-21kthreadcore12:05:581
403200899207,5cyclictest0-21swapper/011:18:350
4032008992018,1cyclictest0-21swapper/009:25:020
4032008992017,2cyclictest1-21systemd09:00:020
4032008992014,5cyclictest123540-21kthreadcore10:40:570
3240591201,9phc2sys0-21swapper/307:05:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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