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2026-06-23 - 05:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jun 23, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145652221630,2sleep20-21swapper/221:40:102
143767321460,1sleep11437675-21pmu-power21:25:141
166577921310,2sleep30-21swapper/300:00:113
15410162680,2sleep20-21swapper/222:35:132
16088472410,0sleep11608848-21sh23:20:131
16871112280,2sleep30-21swapper/300:15:103
1261437992718,8cyclictest0-21swapper/023:10:030
1261439992523,1cyclictest0-21swapper/221:35:032
1261437992415,8cyclictest0-21swapper/022:40:030
1261438992321,1cyclictest1469735-21ls21:50:001
1261437992318,4cyclictest0-21swapper/023:55:030
1261437992317,2cyclictest67250irq/126-eno121:25:030
1261439992219,1cyclictest0-21swapper/223:20:012
1261438992217,3cyclictest274-21systemd-journal20:20:001
1261438992211,2cyclictest67250irq/126-eno123:50:021
126143799223,11cyclictest738-21gdbus19:15:010
1261437992214,7cyclictest0-21swapper/021:20:010
3153791210,2phc2sys0-21swapper/322:05:133
1261438992115,2cyclictest67250irq/126-eno100:25:141
1261437992116,2cyclictest1663966-21aten2.4-expect00:00:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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