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2025-11-29 - 20:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Nov 29, 2025 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
355186999264,2cyclictest3894902-21cat11:00:230
3551869992621,4cyclictest4040426-21idleruntime-cro12:25:000
3551869992621,4cyclictest4040426-21idleruntime-cro12:25:000
38319552250,1sleep10-21swapper/110:25:011
355186999259,6cyclictest0-21swapper/012:00:170
3551869992515,2cyclictest170550irq/121-eno109:15:230
3551869992513,8cyclictest0-21swapper/011:10:190
3551869992511,9cyclictest0-21swapper/011:35:010
3551869992511,6cyclictest0-21swapper/009:55:020
3551870992413,3cyclictest3953492-21munin-plugin-st11:35:001
355186999245,10cyclictest0-21swapper/012:26:460
3551869992418,5cyclictest3823119-21latency_hist10:20:000
3551869992415,8cyclictest3846270-21sort10:30:290
3551869992411,5cyclictest0-21swapper/010:05:010
3551870992313,3cyclictest4045184-21kthreadcore12:25:261
3551870992313,3cyclictest3900441-21runrttasks11:04:051
355186999239,6cyclictest260-21systemd-journal11:49:550
355186999231,9cyclictest3799363-21cut10:05:250
3551869992317,5cyclictest3982831-21kthreadcore11:50:240
3551869992317,5cyclictest3965566-21kthreadcore11:40:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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