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2026-05-05 - 20:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue May 05, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94946121050,2sleep30-21swapper/311:55:003
7548962720,2sleep20-21swapper/209:30:292
7969582590,1sleep0796956-21ssh10:13:400
8806692510,1sleep10-21swapper/111:09:001
6599142430,2sleep30-21swapper/308:20:283
56769999314,18cyclictest934314-21turbostat11:45:000
567699993116,7cyclictest945470-21kthreadcore11:50:300
567699992821,2cyclictest3851703-21mta-sts-daemon08:20:210
10143482280,2sleep30-21swapper/312:35:283
567700992522,2cyclictest787983-21latency_hist10:05:011
567699992320,2cyclictest953081-21kthreadcore11:55:300
567699992320,2cyclictest1010442-21latency_hist12:35:000
567701992119,1cyclictest0-21swapper/208:30:022
567701992118,1cyclictest0-21swapper/208:40:002
567700992118,2cyclictest714543-21idleruntime-cro09:05:001
567700992118,2cyclictest1-21systemd08:10:011
567699992113,7cyclictest0-21swapper/009:20:000
383433398210,3rtkit-daemon3851703-21mta-sts-daemon10:48:370
567700992017,2cyclictest812801-21grep10:25:001
56769999209,6cyclictest0-21swapper/010:09:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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