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2026-08-06 - 10:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Aug 06, 2026 00:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14125182710,1sleep11412501-21ssh21:40:481
14441842610,4sleep1341rcuc/122:04:291
15258082350,2sleep30-21swapper/323:00:023
1213902993517,13cyclictest0-21swapper/100:40:001
1213902993423,7cyclictest191rcu_preempt19:15:041
1213902993330,2cyclictest1362683-21grep21:10:011
1213902993330,2cyclictest1362683-21grep21:10:011
1213902993220,7cyclictest69250irq/121-eno123:03:451
1213902993216,11cyclictest0-21swapper/122:00:011
16539142290,2sleep11653522-21ssh00:25:411
1213902992915,10cyclictest1612635-21head23:55:461
121390299284,13cyclictest1-21systemd20:35:011
1213902992814,10cyclictest1392641-21sh21:30:141
1213903992720,3cyclictest0-21swapper/221:20:272
1213902992516,8cyclictest1592207-21base6423:45:011
1213902992511,10cyclictest1567097-21kthreadcore23:25:441
1213902992416,7cyclictest1-21systemd22:40:031
1213902992416,7cyclictest1-21systemd22:40:031
1213902992410,9cyclictest0-21swapper/123:30:471
121390299239,9cyclictest0-21swapper/100:20:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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