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2026-06-13 - 05:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jun 13, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
398832321580,3sleep30-21swapper/300:20:013
39373602470,2sleep30-21swapper/323:45:183
37615022380,1sleep13761508-21kthreadcore21:45:241
3559319993227,3cyclictest0-21swapper/122:05:011
38785142280,1sleep1191rcu_preempt23:05:201
355931899286,18cyclictest0-21swapper/021:40:030
3559318992621,4cyclictest0-21swapper/023:45:020
3559318992615,8cyclictest3796672-21/usr/sbin/munin22:10:020
3559318992419,4cyclictest3966545-21systemd00:05:030
3559319992320,2cyclictest274-21systemd-journal00:00:011
3559319992320,2cyclictest274-21systemd-journal00:00:011
355931899239,9cyclictest0-21swapper/022:40:300
3559318992317,5cyclictest1-21systemd20:34:310
3559318992312,7cyclictest3784890-21kthreadcore22:00:250
3559318992311,8cyclictest0-21swapper/021:55:020
37167542220,1sleep30-21swapper/321:15:243
3559319992218,2cyclictest0-21swapper/121:10:191
3559319992215,2cyclictest492398rtkit-daemon22:40:021
355931899229,8cyclictest0-21swapper/023:50:270
355931899229,8cyclictest0-21swapper/019:25:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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