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2026-06-08 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 08, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
380891221060,1sleep00-21swapper/010:45:310
392258721050,2sleep13922560-21ssh12:00:351
351780799251,19cyclictest3661916-21irqstats09:05:310
3517807992412,7cyclictest0-21swapper/012:15:330
351780799229,8cyclictest0-21swapper/012:25:020
3517807992213,8cyclictest3689702-21tail09:25:280
3517807992213,8cyclictest0-21swapper/011:15:010
3517807992213,5cyclictest3666369-21diskmemload10:15:400
3517807992211,7cyclictest0-21swapper/009:50:020
3517808992118,2cyclictest3593064-21/usr/sbin/munin08:10:011
3517808992113,2cyclictest67250irq/126-eno109:15:261
351780799216,10cyclictest0-21swapper/009:50:280
3517807992116,4cyclictest3858146-21sh11:20:000
3517807992111,9cyclictest0-21swapper/011:05:010
3517807992111,9cyclictest0-21swapper/010:45:020
351780799209,10cyclictest0-21swapper/011:50:240
351780799206,10cyclictest0-21swapper/011:40:330
3517807992015,4cyclictest3755013-21sh10:10:020
3517807992014,4cyclictest3517930-21systemd07:10:020
3517808991917,1cyclictest0-21swapper/111:10:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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