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2026-07-02 - 09:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 02, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165132321620,2sleep30-21swapper/323:45:033
139141321030,1sleep10-21swapper/120:45:021
16067242980,2sleep30-21swapper/323:15:013
1273994993822,5cyclictest67250irq/126-eno122:29:481
1273993992521,3cyclictest1-21systemd20:00:010
1273993992514,4cyclictest1700151-21kthreadcore00:19:570
1273993992421,2cyclictest1635850-21sensors_temp23:35:020
1273993992421,2cyclictest1273991-21cyclictest00:30:010
1273993992410,9cyclictest0-21swapper/000:34:560
1273996992320,1cyclictest0-21swapper/219:34:552
1273994992320,2cyclictest1403305-21grep20:55:011
1273994992317,2cyclictest67250irq/126-eno100:20:011
1273994992311,7cyclictest0-21swapper/100:30:011
1273993992320,2cyclictest1628425-21grep23:30:010
1273996992219,1cyclictest0-21swapper/223:15:012
1273996992219,1cyclictest0-21swapper/223:05:022
1273996992219,1cyclictest0-21swapper/220:25:012
1273994992219,2cyclictest274-21systemd-journal23:50:031
1273994992219,2cyclictest1679049-21sh00:05:021
1273993992219,2cyclictest1650679-21timerandwakeup23:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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