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2026-07-30 - 12:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 30, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156603721010,2sleep30-21swapper/323:01:103
144205321010,2sleep30-21swapper/321:40:303
16628312710,1sleep11662830-21ssh00:08:261
1248408992715,7cyclictest1547312-21kthreadcore22:51:000
13966382260,2sleep30-21swapper/321:06:073
124840899267,13cyclictest0-21swapper/023:01:000
1248408992619,5cyclictest1412125-21idleruntime-cro21:20:010
1248408992517,4cyclictest191rcu_preempt00:30:490
1248408992515,9cyclictest1490310-21kthreadcore22:11:010
1248408992415,4cyclictest1157598rtkit-daemon22:47:570
1248408992414,6cyclictest1248406-21cyclictest22:00:550
1248408992411,8cyclictest0-21swapper/023:35:020
1248408992410,10cyclictest1497499-21kthreadcore22:16:010
1248409992320,2cyclictest1589578-21sendmail23:20:011
1248409992320,2cyclictest1500695-21grep22:20:011
1248409992312,6cyclictest0-21swapper/122:47:401
1248409992312,6cyclictest0-21swapper/100:26:391
124840899239,8cyclictest1663929-21ssh00:10:390
124840899239,8cyclictest1663929-21ssh00:10:390
124840899238,11cyclictest1508847-21cpu22:25:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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