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2026-07-11 - 19:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jul 11, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263675422020,2sleep30-21swapper/312:10:003
259426722000,2sleep30-21swapper/311:44:353
248811621800,2sleep30-21swapper/310:29:483
228060221540,2sleep30-21swapper/307:59:403
246007421500,2sleep30-21swapper/310:12:293
258456621040,1sleep10-21swapper/111:34:471
26198192920,1sleep00-21swapper/011:59:430
24766732320,2sleep12476520-21ssh10:24:411
2221449992514,7cyclictest2393878-21/usr/sbin/munin09:29:430
2221450992317,2cyclictest67250irq/126-eno109:39:281
2221449992313,6cyclictest0-21swapper/012:29:430
2221449992212,6cyclictest0-21swapper/012:35:010
222144999220,18cyclictest2242589-21/usr/sbin/munin07:29:470
2221451992118,1cyclictest0-21swapper/208:25:012
2221450992118,2cyclictest2503778-21/usr/sbin/munin10:40:011
2221449992118,2cyclictest2436380-21/usr/sbin/munin09:55:010
2221450992017,2cyclictest660-21dbus-daemon10:00:021
2221450992017,2cyclictest2377309-21idleruntime-cro09:15:001
2221450992012,3cyclictest2678004-21kthreadcore12:39:421
222144999209,6cyclictest0-21swapper/009:14:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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