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2026-08-05 - 20:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Aug 05, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71757121000,2sleep30-21swapper/312:25:453
4871552960,2sleep30-21swapper/309:50:413
7289312310,2sleep20-21swapper/212:33:572
44748499264,20cyclictest191rcu_preempt12:05:461
447483992520,4cyclictest456541-21wc07:55:010
447483992513,5cyclictest682476-21kthreadcore12:00:490
447483992510,6cyclictest0-21swapper/012:25:220
447484992414,3cyclictest695972-21kthreadcore12:10:451
44748499233,9cyclictest0-21swapper/111:10:021
44748499232,12cyclictest711762-21tr12:20:451
44748499231,8cyclictest640710-21ssh11:35:231
447484992316,2cyclictest191rcu_preempt11:45:461
447484992315,3cyclictest36-21ksoftirqd/109:25:011
447484992314,1cyclictest191rcu_preempt07:15:021
44748399239,6cyclictest0-21swapper/008:20:010
447483992317,2cyclictest664-21dbus-daemon07:20:020
447483992316,2cyclictest0-21swapper/011:24:520
44748399231,18cyclictest602608-21ssh11:10:220
447483992215,2cyclictest0-21swapper/010:10:010
447483992213,5cyclictest574542-21kthreadcore10:50:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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