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2026-04-02 - 13:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Apr 02, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
404089922120,2sleep30-21swapper/323:16:163
396417421120,2sleep30-21swapper/322:26:143
374338121090,3sleep30-21swapper/319:46:103
38876512960,2sleep20-21swapper/221:35:022
39182012310,2sleep03918203-21aten_repower_fr21:56:090
40085102290,1sleep10-21swapper/122:56:101
3696701992516,8cyclictest3968119-21latency22:26:170
3696701992515,9cyclictest3970930-21sh22:31:090
369670199248,7cyclictest3955084-21systemd-run22:20:000
369670199248,4cyclictest0-21swapper/023:50:010
3696701992415,8cyclictest3703050-21aten_repower_en19:15:010
3696701992413,9cyclictest4022787-21sh23:05:010
3696703992320,1cyclictest0-21swapper/220:55:002
369670199238,6cyclictest0-21swapper/023:10:020
369670199238,13cyclictest0-21swapper/022:01:140
369670199237,7cyclictest0-21swapper/022:41:090
3696701992314,8cyclictest3886109-21unixbench_multi21:31:230
3696701992313,9cyclictest3896730-21grep21:41:140
3696701992313,8cyclictest0-21swapper/022:50:020
3696701992313,2cyclictest4075538-21cron23:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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