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2026-05-18 - 04:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon May 18, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37940262960,2sleep30-21swapper/321:10:143
38021022370,2sleep13802059-21ssh21:15:211
3634754992619,3cyclictest3827634-1atopacctd21:10:121
3634755992519,1cyclictest0-21swapper/223:25:012
3634754992520,2cyclictest134050irq/121-eno122:40:111
3634754992519,2cyclictest134050irq/121-eno121:35:011
363475399255,12cyclictest3681779-21apt19:45:050
3634755992219,1cyclictest0-21swapper/200:30:012
3634754992214,3cyclictest0-21swapper/100:25:011
3634755992118,1cyclictest0-21swapper/222:45:002
3634755992118,1cyclictest0-21swapper/222:20:002
3634753992111,6cyclictest0-21swapper/021:45:000
3634753992111,5cyclictest0-21swapper/023:15:050
3634754992017,2cyclictest3949333-21munin-run22:55:011
3634754992017,2cyclictest3896431-21systemd-run22:20:021
3634754992017,2cyclictest3865329-21latency_hist22:00:001
3634754992017,2cyclictest1290-21dbus-daemon00:30:021
3634754992016,3cyclictest3964493-21dump-pmu-power23:05:001
3634754992013,3cyclictest3951968-21kthreadcore22:55:101
3634754992013,3cyclictest3951968-21kthreadcore22:55:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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