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2026-08-06 - 23:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Aug 06, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244769621160,2sleep30-21swapper/311:00:013
228984421010,1sleep10-21swapper/109:10:491
219221421010,2sleep30-21swapper/307:50:483
23206362920,2sleep30-21swapper/309:32:233
213583999231,7cyclictest0-21swapper/211:20:202
213583699235,12cyclictest664-21dbus-daemon10:00:011
24795482220,2sleep02479550-21tr11:20:420
2135836992218,3cyclictest2492504-21systemd-run11:30:021
2135836992216,2cyclictest191rcu_preempt09:40:241
2135835992217,4cyclictest690-21rs:main0
1157598220,2rtkit-daemon1309-21mta-sts-daemon11:39:150
2135836992115,2cyclictest69250irq/121-eno111:15:011
2135835992111,5cyclictest0-21swapper/010:25:430
23530132200,1sleep20-21swapper/209:55:432
2135839992017,1cyclictest0-21swapper/209:05:002
2135839992017,1cyclictest0-21swapper/209:05:002
2135836992018,1cyclictest2135833-21cyclictest11:20:011
2135836992017,2cyclictest2462509-21dump-pmu-power11:10:011
2135835992017,2cyclictest2508564-21sed11:40:380
2135835992013,6cyclictest2331166-21kthreadcore09:40:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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