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2026-04-30 - 18:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Apr 30, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
378652921030,2sleep30-21swapper/309:55:373
36622872280,2sleep0171ktimers/008:25:000
3565457992516,4cyclictest0-21swapper/109:45:381
3565456992522,2cyclictest3803985-21unin-run10:10:010
3565457992421,2cyclictest1326-21systemd-logind12:30:001
39520012230,2sleep30-21swapper/311:45:363
383433398230,5rtkit-daemon3851704-21mta-sts-daemon12:21:381
37587952230,2sleep13758726-21ssh09:40:001
3565458992320,2cyclictest0-21swapper/208:10:022
3565457992316,6cyclictest1-21systemd09:20:011
3565456992320,2cyclictest3571795-21missed_timers07:15:010
3565456992320,2cyclictest3571795-21missed_timers07:15:010
3565456992320,2cyclictest1290-21dbus-daemon09:15:000
356545899221,4cyclictest0-21swapper/208:50:012
3565457992219,2cyclictest3781472-21systemd09:55:011
3565457992219,2cyclictest1290-21dbus-daemon12:05:001
3565456992219,2cyclictest3952751-21ntpd10:14:130
3565456992219,2cyclictest3729023-21grep09:20:020
3565456992212,5cyclictest0-21swapper/011:55:020
38730952210,2sleep30-21swapper/310:55:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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