You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-09 - 05:10
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jan 09, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
109206521110,1sleep00-21swapper/022:38:090
84835221040,2sleep1848351-21wc20:00:001
8494472680,2sleep20-21swapper/220:03:012
8670392410,2sleep0867041-21aten_repower_cu20:18:020
785530992814,9cyclictest0-21swapper/021:48:140
785531992613,4cyclictest36-21ksoftirqd/121:23:101
785530992512,12cyclictest1251513-21kthreadcore00:08:070
2902298250,7rtkit-daemon1288-1atopacctd23:12:120
785530992418,5cyclictest927656-21perf21:05:000
78553099239,2cyclictest257-21systemd-journal20:20:320
78553099235,5cyclictest0-21swapper/021:58:130
785531992216,2cyclictest134050irq/121-eno100:05:011
785531992210,2cyclictest134050irq/121-eno121:43:061
78553099221,6cyclictest1-21systemd22:50:010
78553099220,9cyclictest860449-21latency_hist20:10:000
785532992118,1cyclictest0-21swapper/220:25:012
785531992117,3cyclictest0-21swapper/100:00:011
78553099218,2cyclictest0-21swapper/000:38:000
78553099216,9cyclictest0-21swapper/019:26:570
785530992116,4cyclictest1149174-21sh23:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional