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2026-03-04 - 19:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Mar 04, 2026 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134316399289,13cyclictest0-21swapper/009:51:540
134316399272,14cyclictest0-21swapper/012:11:580
1343163992614,8cyclictest1501658-21tr09:16:490
14678532250,2sleep30-21swapper/308:51:513
1343164992522,2cyclictest1290-21dbus-daemon11:30:011
134316399249,6cyclictest0-21swapper/012:16:460
1343163992317,5cyclictest1343161-21cyclictest10:05:020
1343163992316,6cyclictest1490826-21diskmemload09:41:590
1343163992316,6cyclictest1490826-21diskmemload09:41:590
1343163992313,9cyclictest1288-1atopacctd10:21:590
1343163992312,10cyclictest0-21swapper/010:20:000
134316399223,4cyclictest1525997-21sshd09:29:480
1343163992215,6cyclictest1363579-21latency_hist07:25:010
1343164992115,2cyclictest134050irq/121-eno110:00:021
1343164992114,2cyclictest1500141-21munin-run09:15:011
134316399219,5cyclictest1511721-21kthreadcore09:21:550
134316399219,4cyclictest0-21swapper/012:10:010
134316399219,2cyclictest191rcu_preempt10:11:480
134316399219,2cyclictest191rcu_preempt10:11:480
134316399211,6cyclictest1-21systemd07:15:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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