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2026-07-05 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jul 05, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39670052750,3sleep30-21swapper/311:59:523
38860972340,2sleep30-21swapper/311:04:533
38051032310,2sleep20-21swapper/210:09:572
3568078992617,3cyclictest36-21ksoftirqd/112:40:011
356807899240,5cyclictest3606822-21latency_hist07:40:011
3568077992417,6cyclictest274-21systemd-journal12:25:020
3153791241,3phc2sys0-21swapper/310:39:533
3568078992315,3cyclictest36-21ksoftirqd/112:30:011
3568077992320,2cyclictest660-21dbus-daemon07:40:010
3568077992320,2cyclictest3704379-21idleruntime-cro09:00:000
492398220,3rtkit-daemon1174-21ntpd09:22:361
3568079992219,1cyclictest0-21swapper/212:40:012
3568078992214,3cyclictest3994883-21kthreadcore12:19:501
3568078992214,3cyclictest36-21ksoftirqd/111:00:031
356807799228,5cyclictest671-21polkitd11:45:010
3568077992214,7cyclictest3568075-21cyclictest10:24:500
3568079992118,1cyclictest0-21swapper/211:45:002
356807899218,7cyclictest0-21swapper/107:14:431
3568077992111,6cyclictest0-21swapper/011:39:510
3568079992018,1cyclictest0-21swapper/210:20:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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