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2026-06-17 - 03:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jun 17, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286595921650,2sleep30-21swapper/322:05:223
272093721120,2sleep30-21swapper/320:15:253
296851421040,1sleep10-21swapper/123:15:141
28349672990,2sleep20-21swapper/221:45:132
30790802310,2sleep30-21swapper/300:30:153
3153791261,9phc2sys0-21swapper/322:35:143
29828492260,2sleep30-21swapper/323:25:023
2634179992414,6cyclictest0-21swapper/023:00:010
2634180992315,3cyclictest0-21swapper/122:10:001
2634181992219,1cyclictest0-21swapper/223:45:012
2634179992212,5cyclictest0-21swapper/000:05:150
2634181992118,1cyclictest0-21swapper/200:40:012
2634180992118,2cyclictest2842055-21/usr/sbin/munin21:50:011
2634180992114,2cyclictest67250irq/126-eno123:40:001
2634179992118,2cyclictest2640343-21hddtemp_smartct19:15:010
492398200,4rtkit-daemon1237-21mta-sts-daemon21:06:260
2634181992017,1cyclictest0-21swapper/223:30:002
2634181992017,1cyclictest0-21swapper/223:10:012
2634181992017,1cyclictest0-21swapper/219:30:582
2634181992017,1cyclictest0-21swapper/200:20:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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