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2026-09-23 - 07:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Sep 23, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190333021060,2sleep20-21swapper/220:54:152
18112252960,1sleep0191rcu_preempt19:44:190
22952902690,3sleep02295294-21latency_hist00:35:020
22044012320,2sleep20-21swapper/223:45:212
2213291250,8phc2sys0-21swapper/320:38:553
176121599242,9cyclictest0-21swapper/123:18:541
1761214992215,6cyclictest798-21mta-sts-daemon23:10:010
1761215992114,6cyclictest24615-21JS14:54:061
176121599207,2cyclictest191rcu_preempt21:20:011
176121599203,9cyclictest36-21ksoftirqd/121:49:161
1761215992015,1cyclictest191rcu_preempt00:38:551
176121599200,3cyclictest2285017-21ssh00:32:051
1761214992014,5cyclictest2152898-21/usr/sbin/munin23:19:200
1761214992014,5cyclictest1761212-21cyclictest00:04:040
1761214992011,6cyclictest2200967-21kthreadcore23:44:190
2213291191,6phc2sys0-21swapper/322:38:533
1761216991916,1cyclictest0-21swapper/200:01:592
176121599195,4cyclictest191rcu_preempt21:33:551
1761215991916,2cyclictest341rcuc/119:10:011
1761215991914,1cyclictest191rcu_preempt19:20:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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