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2026-06-15 - 15:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 15, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341872421580,2sleep30-21swapper/322:55:023
356426921540,2sleep30-21swapper/300:31:053
348463721120,2sleep13484642-21idleruntime-cro23:40:011
343936621050,2sleep30-21swapper/323:06:323
35628182940,1sleep1191rcu_preempt00:30:231
35656102760,2sleep20-21swapper/200:35:012
311479199317,19cyclictest0-21swapper/022:45:160
3114791993119,8cyclictest693-21systemd-logind23:55:030
311479199301,24cyclictest3301851-21perl21:35:200
311479199289,11cyclictest0-21swapper/022:05:170
311479199276,14cyclictest0-21swapper/000:35:150
3114791992716,7cyclictest3471895-21kthreadcore23:30:210
311479199268,9cyclictest0-21swapper/022:55:180
3114791992620,5cyclictest3374645-21grep22:25:030
3114791992610,8cyclictest3276820-21timerandwakeup21:15:300
3114792992514,3cyclictest3367275-21aten_repower_fr22:20:161
3114791992520,4cyclictest3159838-21idleruntime-cro19:45:000
3114791992513,8cyclictest660-21dbus-daemon00:05:020
3114791992512,12cyclictest1246-21mta-sts-daemon00:13:370
3114791992510,11cyclictest3178719-21tail20:00:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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