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2026-05-12 - 10:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue May 12, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81199021590,1sleep0191rcu_preempt23:00:250
88265321000,2sleep1882654-21apt23:50:001
6422452470,1sleep1642246-21grep21:10:231
8844332390,2sleep30-21swapper/323:50:183
5646382380,5sleep1564643-21kthreadcore20:10:201
5646382380,5sleep1564643-21kthreadcore20:10:201
484397992825,2cyclictest936609-21dump-pmu-power00:25:000
484398992619,3cyclictest707636-21cstates21:55:141
484398992512,3cyclictest0-21swapper/100:30:131
484397992520,1cyclictest7374071systemd-run22:15:010
484397992514,6cyclictest0-21swapper/022:55:010
484398992421,2cyclictest506632-21grep19:25:181
484398992413,6cyclictest0-21swapper/121:25:021
484397992415,3cyclictest3827634-1atopacctd21:33:510
484398992320,2cyclictest852043-21sh23:30:001
484398992318,1cyclictest191rcu_preempt23:03:371
484397992312,2cyclictest511841-21systemd-run19:30:010
484398992219,2cyclictest775929-21munin-run22:40:011
484398992219,2cyclictest0-21swapper/122:35:011
484398992215,2cyclictest1996-21runrttasks23:13:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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