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2026-07-06 - 10:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jul 06, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62419721110,3sleep1554544-21kworker/1:0+events23:04:481
36518421070,1sleep00-21swapper/019:54:510
30901499307,12cyclictest36-21ksoftirqd/120:30:011
309013992724,2cyclictest0-21swapper/021:39:560
309013992724,2cyclictest0-21swapper/021:39:560
30901499240,12cyclictest695259-21munin-run23:50:011
309014992320,2cyclictest754763-21grep00:30:021
309014992316,2cyclictest191rcu_preempt23:27:471
309014992316,2cyclictest191rcu_preempt00:34:431
492398220,2rtkit-daemon1247-21mta-sts-daemon20:55:240
31537912211,3phc2sys0-21swapper/321:54:563
309014992216,2cyclictest67250irq/126-eno121:59:471
309014992215,3cyclictest191rcu_preempt22:29:491
309014992214,3cyclictest36-21ksoftirqd/122:35:021
309014992213,4cyclictest36-21ksoftirqd/123:40:031
309013992211,6cyclictest0-21swapper/023:44:470
30901499217,9cyclictest36-21ksoftirqd/121:10:011
309014992118,2cyclictest660-21dbus-daemon23:10:021
309014992118,2cyclictest660-21dbus-daemon21:35:011
309014992115,1cyclictest191rcu_preempt23:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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