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2026-07-14 - 15:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jul 14, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190078721110,2sleep30-21swapper/311:16:193
166053421110,2sleep20-21swapper/208:26:252
187212921030,2sleep30-21swapper/310:56:273
19049942990,1sleep20-21swapper/211:16:262
18540302730,1sleep11854029-21ssh10:41:381
1565251993122,8cyclictest1795527-21apt-config10:05:011
1565251993116,10cyclictest1719194-21kthreadcore09:11:251
1565250993126,4cyclictest664-21dbus-daemon11:45:010
15982252300,1sleep10-21swapper/107:36:191
1565251992617,2cyclictest1571543-21cut07:15:021
1565251992510,3cyclictest0-21swapper/111:40:021
1565251992421,2cyclictest1023401-1atop09:10:011
1565250992314,5cyclictest1799333-21kthreadcore10:06:240
1157598230,4rtkit-daemon1306-21mta-sts-daemon07:14:580
1565251992215,3cyclictest1886709-21irqcore11:06:231
1565251992215,3cyclictest1886709-21irqcore11:06:231
1565251992212,4cyclictest1306-21mta-sts-daemon10:16:261
1565251992210,2cyclictest0-21swapper/111:50:011
1565250992111,5cyclictest0-21swapper/010:45:020
1565250992110,6cyclictest0-21swapper/012:16:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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