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2026-06-20 - 09:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jun 20, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4390921020,2sleep043608-21ssh21:35:150
707582970,2sleep20-21swapper/221:55:092
1148972740,1sleep0114895-21ssh22:24:570
2633212460,1sleep20-21swapper/200:05:112
4048531992618,7cyclictest70516-21unin-run21:55:020
4048531992618,7cyclictest70516-21unin-run21:55:020
4048532992520,1cyclictest67250irq/126-eno121:45:041
4048532992313,2cyclictest67250irq/126-eno123:25:231
4048532992313,2cyclictest67250irq/126-eno122:54:391
4048531992312,6cyclictest0-21swapper/021:35:010
404853199227,2cyclictest808-21hwrng22:03:400
404853199225,10cyclictest294948-21cat00:25:150
4048531992214,7cyclictest303118-21kthreadcore00:30:150
3153791222,8phc2sys0-21swapper/319:05:073
4048533992118,1cyclictest0-21swapper/220:00:012
4048532992116,3cyclictest109260-21kthreadcore22:20:141
4048531992118,2cyclictest314230-21munin-plugin-st00:40:010
4048531992118,2cyclictest0-21swapper/019:15:010
4048531992114,6cyclictest660-21dbus-daemon23:45:010
3153791210,2phc2sys0-21swapper/320:20:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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