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2025-12-23 - 05:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Dec 23, 2025 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6689802860,2sleep30-21swapper/320:58:323
536220992620,5cyclictest889007-1atop00:00:010
536220992516,4cyclictest561125-21kthreadcore19:28:310
536225992320,2cyclictest829025-21systemd23:10:021
536225992320,2cyclictest0-21swapper/120:55:011
53622099220,2cyclictest542629-21munin-run19:15:010
53622099218,2cyclictest689481-21latency_hist21:15:010
536220992114,5cyclictest1286-21avahi-daemon23:30:020
536225992016,3cyclictest731079-21sendmail_mailqu21:48:361
536220992015,4cyclictest556607-21systemd-run19:25:010
536220992015,4cyclictest1-21systemd00:20:010
536220992014,4cyclictest797969-21systemd-run22:45:010
53622799198,6cyclictest0-21swapper/200:20:012
536227991917,1cyclictest0-21swapper/219:50:022
536227991916,1cyclictest0-21swapper/220:20:012
536225991916,2cyclictest1326-21systemd-logind21:45:011
53622099195,6cyclictest937714-21awk00:40:000
53622099192,7cyclictest641066-21turbostat20:35:000
536220991914,4cyclictest677606-21cut21:05:020
536220991914,4cyclictest586678-21perf19:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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