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2026-08-08 - 16:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 08, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200937121010,2sleep30-21swapper/312:01:153
19211692740,1sleep01921167-21ssh11:04:200
15997332530,3sleep20-21swapper/207:05:332
18590972480,2sleep30-21swapper/310:20:383
1602994992822,2cyclictest69250irq/121-eno107:20:011
1602993992817,6cyclictest1825739-21latency_hist10:00:030
1602993992514,6cyclictest759-1atopacctd12:30:370
19064092230,2sleep20-21swapper/210:55:002
1602993992320,2cyclictest1641669-21latency_hist07:40:000
1602994992213,3cyclictest1820638-21kthreadcore09:55:371
16952692210,2sleep20-21swapper/208:20:382
1602994992116,3cyclictest688-21in:imuxsock09:50:021
1602993992118,2cyclictest1958919-21grep11:30:020
1602993992118,1cyclictest0-21swapper/011:20:020
1602993992113,4cyclictest1034-21runrttasks10:31:080
1602993992113,4cyclictest1034-21runrttasks10:31:080
3240591201,4phc2sys0-21swapper/310:15:193
1602995992017,1cyclictest0-21swapper/212:14:432
1602995992017,1cyclictest0-21swapper/209:25:012
1602994992017,2cyclictest1899119-21sh10:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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