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2026-09-01 - 14:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Sep 01, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118400021040,2sleep30-21swapper/322:45:013
8667762390,2sleep30-21swapper/319:24:513
847488992413,7cyclictest1158410-21runrttasks22:31:260
84748899240,15cyclictest0-21swapper/000:19:270
84749099232,17cyclictest0-21swapper/220:09:282
847488992314,8cyclictest977-21rs:main0
847488992312,7cyclictest1116653-21irqcore22:09:490
84748899230,18cyclictest919479-21/usr/sbin/munin20:04:550
84748899225,4cyclictest0-21swapper/021:54:510
84748899215,9cyclictest0-21swapper/022:14:280
847488992114,6cyclictest24619-21llvmpipe-120:44:590
847488992112,7cyclictest24615-21JS14:54:060
847488992112,5cyclictest1180159-21kthreadcore22:44:500
84748899211,13cyclictest0-21swapper/021:19:270
84748899210,10cyclictest1206459-21tr22:59:490
847489992013,3cyclictest1260219-21kthreadcore23:29:501
847488992017,2cyclictest1281545-21ssh23:40:010
847488992014,5cyclictest24648-21gmain23:23:310
847488992014,5cyclictest1188-21runrttasks23:40:570
847488992011,5cyclictest1262280-21kthreadcore23:29:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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