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2026-06-08 - 06:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 08, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283767821020,2sleep02837622-21ssh22:15:380
283767821020,2sleep02837622-21ssh22:15:380
29214962340,4sleep02921497-21/usr/sbin/munin23:15:290
28479452310,2sleep30-21swapper/322:25:303
29937952290,2sleep20-21swapper/200:05:012
2588018992817,3cyclictest2958611-21kthreadcore23:40:331
2588018992519,2cyclictest67250irq/126-eno123:50:031
2588018992515,3cyclictest765-1atopacctd21:45:021
2588018992415,2cyclictest0-21swapper/100:10:021
2588017992415,5cyclictest2943343-21gltestperf23:30:290
29755052230,1sleep12975508-21cut23:50:331
2588017992315,4cyclictest2752909-21kthreadcore21:20:320
2588018992219,2cyclictest660-21dbus-daemon21:40:021
2588017992219,2cyclictest3045169-21dump-pmu-power00:40:000
2588017992219,2cyclictest2749210-21proc_pri21:15:380
2588017992214,7cyclictest2983224-21kthreadcore23:55:350
2588017992211,6cyclictest0-21swapper/022:55:020
2588018992118,2cyclictest2614634-21latency_hist19:30:011
2588017992112,4cyclictest0-21swapper/020:55:000
2588018992017,2cyclictest2802835-21latency_hist21:55:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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