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2026-08-12 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Aug 12, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100534521230,2sleep30-21swapper/311:27:253
111005021080,2sleep1684-21systemd-logind12:40:011
92407421030,5sleep00-21swapper/010:32:180
650099994017,12cyclictest814808-21cstates09:20:230
650099994014,14cyclictest1034-21runrttasks11:10:080
65009999318,18cyclictest0-21swapper/009:40:270
650103993014,10cyclictest0-21swapper/109:25:021
65009999297,16cyclictest0-21swapper/009:50:180
65009999296,16cyclictest0-21swapper/012:00:020
650099992920,8cyclictest954519-21latency_hist10:55:020
650103992818,9cyclictest873023-21idleruntime-cro10:00:001
650103992812,8cyclictest857315-21sh09:47:181
650103992812,8cyclictest857315-21sh09:47:181
65009999289,12cyclictest1034-21runrttasks10:04:370
650103992719,7cyclictest863737-21mailstats09:50:311
65009999279,13cyclictest0-21swapper/009:05:320
65009999276,2cyclictest0-21swapper/012:10:230
65009999275,6cyclictest0-21swapper/012:15:050
650103992613,7cyclictest1043375-21sh11:54:411
650103992612,7cyclictest1034759-21sh11:46:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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