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2026-05-17 - 00:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat May 16, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11709662940,3sleep00-21swapper/012:08:430
11565242670,1sleep01156519-21ssh12:00:010
11565242670,1sleep01156519-21ssh12:00:010
743322992717,6cyclictest1018650-21ls10:30:010
743329992519,2cyclictest134050irq/121-eno111:35:011
743329992413,3cyclictest1126335-21ssh11:40:081
743322992414,6cyclictest1144291-21kthreadcore11:50:150
743329992318,3cyclictest0-21swapper/107:50:001
743322992320,2cyclictest1057017-21idleruntime-cro10:55:000
383433398230,3rtkit-daemon3851704-21mta-sts-daemon10:01:210
743329992219,2cyclictest1290-21dbus-daemon11:30:001
743329992218,3cyclictest3851704-21mta-sts-daemon11:54:431
743329992214,3cyclictest0-21swapper/112:10:001
743322992219,2cyclictest808739-21sendmail08:00:000
743334992118,1cyclictest0-21swapper/207:35:002
74332999212,2cyclictest134050irq/121-eno110:20:011
743329992117,3cyclictest1290-21dbus-daemon12:20:001
74332299218,6cyclictest0-21swapper/011:00:060
743322992118,2cyclictest1209782-21/usr/sbin/munin12:35:030
743334992017,1cyclictest0-21swapper/211:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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