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2026-05-24 - 00:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat May 23, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204260521010,2sleep30-21swapper/311:45:043
17614012840,3sleep30-21swapper/308:35:053
21058582420,2sleep10-21swapper/112:27:031
21058582420,2sleep10-21swapper/112:27:031
1653660992421,2cyclictest1848983-21cut09:40:031
1653663992320,1cyclictest0-21swapper/212:40:002
1653660992320,2cyclictest1855812-21grep09:45:021
1653660992320,2cyclictest1290-21dbus-daemon08:50:021
1653660992219,2cyclictest1758290-21systemd08:35:021
1653660992219,2cyclictest0-21swapper/111:30:031
165365799224,1cyclictest2076504-21grep12:09:570
1653657992219,2cyclictest2085333-21latency_hist12:15:030
1653657992219,2cyclictest2023508-21apt-key11:35:010
1653660992118,2cyclictest3851698-21mta-sts-daemon08:15:021
1653657992118,2cyclictest1695671-21if_eno107:45:010
165365799210,15cyclictest0-21swapper/010:40:500
1653663992018,1cyclictest0-21swapper/211:50:012
1653663992018,1cyclictest0-21swapper/211:30:012
1653663992017,1cyclictest0-21swapper/210:10:002
1653663992017,1cyclictest0-21swapper/208:25:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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