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2026-05-06 - 20:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed May 06, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2462828993229,1cyclictest0-21swapper/207:15:022
27178422300,1sleep20-21swapper/210:15:242
2462826992522,2cyclictest2632303-21idleruntime-cro09:20:000
2462826992413,6cyclictest0-21swapper/010:40:000
2462826992413,6cyclictest0-21swapper/010:25:000
2649091230,2phc2sys0-21swapper/311:10:333
2462827992320,2cyclictest2462824-21cyclictest10:35:011
2462827992219,2cyclictest1290-21dbus-daemon12:35:021
2462828992118,1cyclictest0-21swapper/211:20:002
2462827992118,2cyclictest3827634-1atopacctd11:55:021
2462827992118,2cyclictest1-21systemd10:15:021
2462827992115,2cyclictest134050irq/121-eno109:30:281
246282699215,10cyclictest0-21swapper/012:00:200
2462826992118,2cyclictest2708865-21/usr/sbin/munin10:10:000
2462826992118,2cyclictest2566808-21latency_hist08:30:010
2462828992018,1cyclictest0-21swapper/209:25:022
2462828992017,1cyclictest0-21swapper/210:10:012
2462827992017,2cyclictest2709273-21/usr/sbin/munin10:10:021
2462827992017,2cyclictest2573102-21latency_hist08:35:001
2462827992017,2cyclictest2529421-21sh08:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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