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2026-06-09 - 12:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jun 09, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27204621020,1sleep10-21swapper/119:20:301
4847022930,2sleep20-21swapper/222:04:422
4239742280,2sleep20-21swapper/221:20:332
255156992717,3cyclictest706567-21latency_hist00:35:021
255156992522,2cyclictest522121-21grep22:30:031
255156992421,2cyclictest551808-21latency_hist22:50:011
255156992320,2cyclictest514554-21latency_hist22:25:011
255156992320,2cyclictest484828-21latency_hist22:05:001
3622032220,2sleep1362207-21fschecks_count20:35:281
255156992213,2cyclictest0-21swapper/121:10:021
255155992215,1cyclictest67250irq/126-eno121:00:250
255157992119,1cyclictest0-21swapper/223:25:022
25515699219,2cyclictest492398rtkit-daemon22:06:341
25515699214,7cyclictest448107-21awk21:40:011
255155992118,2cyclictest660-21dbus-daemon00:35:020
255155992118,2cyclictest658-21avahi-daemon23:05:010
255155992115,5cyclictest0-21swapper/000:20:010
255155992114,6cyclictest656636-21kthreadcore00:00:310
255155992113,7cyclictest413068-21kthreadcore21:15:300
255155992113,7cyclictest413068-21kthreadcore21:15:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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