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2026-07-02 - 02:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 01, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34862821070,2sleep20-21swapper/207:19:542
53835921050,2sleep1538363-21unixbench_multi09:45:041
69269721020,2sleep1692633-21ssh11:30:011
339131993115,11cyclictest0-21swapper/108:55:021
7222402270,1sleep10-21swapper/111:50:011
33913399271,16cyclictest0-21swapper/212:20:022
339127992615,7cyclictest780798-21latency_hist12:30:010
33913199250,14cyclictest768318-21taskset12:23:561
339133992421,1cyclictest0-21swapper/212:10:022
33913199243,13cyclictest1-21systemd07:35:021
339131992417,6cyclictest0-21swapper/108:10:011
339131992416,7cyclictest648832-21latency_hist11:00:031
339131992416,7cyclictest0-21swapper/109:35:021
339131992415,8cyclictest677850-21timedrift11:20:011
33913199241,18cyclictest510242-21taskset09:29:261
339127992420,3cyclictest389384-21tr07:50:020
339127992415,5cyclictest765872-21kthreadcore12:19:590
339133992320,1cyclictest0-21swapper/207:45:002
33913199238,10cyclictest698046-21kthreadcore11:34:561
33913199238,10cyclictest698046-21kthreadcore11:34:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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