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2026-05-15 - 23:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri May 15, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3017273992819,5cyclictest0-21swapper/208:35:072
301727199269,11cyclictest601rcuop/309:45:070
3017271992612,9cyclictest0-21swapper/010:15:010
3017272992516,8cyclictest3354090-21dump-pmu-power11:10:001
3017271992514,7cyclictest0-21swapper/010:00:000
301727299249,3cyclictest0-21swapper/109:20:011
301727199242,21cyclictest3468839-21awk12:25:000
3017271992418,5cyclictest3224267-21sh09:45:000
3017271992410,9cyclictest0-21swapper/010:02:490
3017271992410,1cyclictest191rcu_preempt09:21:480
301727199240,4cyclictest3452634-21ssh12:12:040
3017272992310,3cyclictest3247547-21aten_repower_en10:00:081
301727199236,3cyclictest501rcuop/211:36:420
301727199232,3cyclictest191rcu_preempt11:50:000
301727199231,21cyclictest3058636-21sed07:40:100
3017271992310,12cyclictest3361762-21true11:15:010
301727299228,1cyclictest0-21swapper/112:05:071
301727299225,9cyclictest1290-21dbus-daemon09:10:011
3017272992219,2cyclictest3422709-21apt-key11:55:001
3017272992214,7cyclictest3827634-1atopacctd12:20:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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