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2025-12-11 - 02:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Dec 10, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51128721570,2sleep30-21swapper/310:58:523
2529972790,2sleep30-21swapper/308:15:003
3210132770,1sleep10-21swapper/109:10:041
17111499271,18cyclictest191760-21munin-run07:25:010
171115992616,4cyclictest36-21ksoftirqd/110:30:011
17111499267,2cyclictest0-21swapper/010:40:120
171114992623,2cyclictest564412-21aten_repower_fr11:30:020
171115992522,2cyclictest283559-21tr08:40:001
171114992513,7cyclictest0-21swapper/010:35:020
171116992320,1cyclictest0-21swapper/207:55:012
171114992314,5cyclictest1803-21gdbus11:00:000
171115992219,2cyclictest320186-21sh09:10:001
171115992214,3cyclictest36-21ksoftirqd/110:40:001
171114992218,3cyclictest538036-21latency_hist11:15:010
171116992118,1cyclictest0-21swapper/212:05:012
171115992118,2cyclictest555603-21systemd11:25:011
171115992113,3cyclictest413101-21timerandwakeup10:00:151
171114992118,2cyclictest503271-21acpi10:55:010
171114992118,2cyclictest1635-21dbus-daemon12:40:010
171114992110,6cyclictest0-21swapper/011:45:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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