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2026-05-03 - 18:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun May 03, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11032172970,2sleep20-21swapper/209:25:362
13088932880,2sleep30-21swapper/311:40:413
12810082780,3sleep30-21swapper/311:25:263
12117412680,1sleep01211739-21ssh10:39:420
10104912480,1sleep01010495-21tr08:15:330
9498512310,2sleep30-21swapper/307:30:273
11146672280,2sleep30-21swapper/309:35:313
921925992724,2cyclictest1272440-21tr11:20:001
921924992615,7cyclictest1192298-21kthreadcore10:25:340
921925992519,2cyclictest134050irq/121-eno109:15:021
921924992522,2cyclictest1-21systemd11:10:010
2649091250,6phc2sys0-21swapper/307:15:253
921924992413,6cyclictest0-21swapper/009:40:010
921924992317,5cyclictest3851703-21mta-sts-daemon11:45:370
921925992217,2cyclictest134050irq/121-eno109:40:331
921925992217,2cyclictest134050irq/121-eno109:40:331
921925992216,2cyclictest134050irq/121-eno110:45:011
921925992215,3cyclictest1174162-21/usr/sbin/munin10:15:361
921924992219,2cyclictest1290-21dbus-daemon09:15:010
92192499221,12cyclictest1242106-21perf11:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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