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2026-08-20 - 17:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Aug 20, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
320428821110,1sleep00-21swapper/010:30:080
32923972990,2sleep30-21swapper/311:30:033
33601822780,2sleep20-21swapper/212:15:032
30572502730,2sleep30-21swapper/308:45:063
2940265992715,7cyclictest0-21swapper/012:00:010
29565642240,2sleep20-21swapper/207:25:062
2940266992421,2cyclictest3106400-21df09:25:021
2940266992421,2cyclictest3106400-21df09:25:021
2940266992413,5cyclictest3358785-21sh12:14:461
2940266992320,2cyclictest3099065-21systemd09:20:031
2940266992320,2cyclictest3028549-21munin-run08:25:001
2940266992320,2cyclictest2986702-21cut07:50:031
2940265992313,6cyclictest3177106-21kthreadcore10:10:080
32338592220,2sleep30-21swapper/310:50:073
2940266992219,2cyclictest3381313-21wc12:30:011
2940266992219,2cyclictest2961655-21/usr/sbin/munin07:30:021
2940266992118,2cyclictest664-21dbus-daemon11:35:011
2940266992118,2cyclictest664-21dbus-daemon08:45:021
2940266992118,2cyclictest3262465-21cstates11:10:021
2940266992118,2cyclictest1-21systemd07:45:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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