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2026-09-22 - 21:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Sep 22, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10381962880,1sleep00-21swapper/010:49:510
8449332410,1sleep10-21swapper/108:59:201
7717092230,3sleep30-21swapper/308:05:033
693000992210,7cyclictest0-21swapper/012:15:030
693000992114,4cyclictest24617-21JS14:54:060
693000992113,5cyclictest913871-21switchtime09:39:220
693000992111,6cyclictest1-21systemd12:30:020
2213291210,4phc2sys0-21swapper/311:23:553
69300199206,4cyclictest82050irq/121-eno112:28:551
69300199204,10cyclictest1056248-21cat11:00:021
693001992016,3cyclictest24648-21gmain11:24:151
69300099208,7cyclictest0-21swapper/010:38:570
693000992014,1cyclictest0-21swapper/009:28:580
693002991917,1cyclictest0-21swapper/211:04:332
693002991916,1cyclictest0-21swapper/211:24:132
69300199196,4cyclictest798376-21grep08:24:201
693001991916,2cyclictest24815-21gsd-power09:46:461
693001991915,3cyclictest24615-21JS14:54:061
693001991915,3cyclictest24614-21JS14:54:061
693001991910,4cyclictest1086504-21kthreadcore11:19:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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