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2025-11-23 - 08:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Nov 23, 2025 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
380703522000,2sleep30-21swapper/300:35:273
3301120992314,5cyclictest3741691-21kthreadcore23:55:350
3301122992218,2cyclictest0-21swapper/221:00:012
3301121992214,3cyclictest3450304-21/usr/sbin/munin21:10:311
3301120992118,2cyclictest1635-21dbus-daemon19:15:010
3301120992115,5cyclictest2009-21runrttasks23:34:480
3301120992111,5cyclictest0-21swapper/022:15:010
835298200,7rtkit-daemon1652-1atopacctd21:38:290
3301122992017,1cyclictest0-21swapper/200:35:422
3301121992017,2cyclictest1635-21dbus-daemon23:25:011
3301121992013,3cyclictest2009-21runrttasks00:24:421
3301120992016,2cyclictest0-21swapper/000:20:020
3301120992011,5cyclictest3736796-21latency_hist23:55:010
3301120992010,2cyclictest0-21swapper/023:10:380
835298190,2rtkit-daemon8351-21rtkit-daemon21:36:411
3301122991916,1cyclictest0-21swapper/220:35:012
3301122991915,1cyclictest0-21swapper/221:05:002
3301121991916,2cyclictest3301118-21cyclictest20:45:001
3301121991915,3cyclictest3765648-21kthreadcore00:10:321
3301121991912,3cyclictest3628696-21kthreadcore22:50:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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