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2026-07-09 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 09, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
169636021020,1sleep11696361-21latency_hist19:10:011
19228762370,2sleep00-21swapper/022:04:450
1696312993020,9cyclictest0-21swapper/122:30:001
1696312992818,2cyclictest67250irq/126-eno123:10:421
1696313992314,4cyclictest0-21swapper/223:00:012
3153791221,3phc2sys0-21swapper/322:29:393
169631199229,5cyclictest660-21dbus-daemon23:30:020
169631199229,5cyclictest660-21dbus-daemon23:30:020
1696311992219,2cyclictest698-21in:imuxsock21:30:010
492398210,2rtkit-daemon4922-21rtkit-daemon23:07:400
1696313992118,1cyclictest0-21swapper/222:05:022
1696312992118,2cyclictest0-21swapper/121:40:011
1696313992017,1cyclictest0-21swapper/200:10:012
169631399201,12cyclictest0-21swapper/219:20:012
1696312992017,2cyclictest0-21swapper/100:20:011
169631199201,7cyclictest1-21systemd20:10:020
1696311992017,2cyclictest1-21systemd20:00:010
1696311992011,5cyclictest1247-21mta-sts-daemon21:57:110
169631199200,7cyclictest1980709-21ssh22:44:370
3153791190,2phc2sys0-21swapper/322:34:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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