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2026-08-02 - 01:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 01, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190766421170,1sleep00-21swapper/009:55:550
20380432690,1sleep02038041-21ssh11:21:050
18546772610,1sleep01854675-21ssh09:20:120
17427272420,1sleep00-21swapper/007:50:480
20554082300,1sleep02055410-21gltestperf11:35:520
1691064992417,2cyclictest69250irq/121-eno111:20:021
1691065992320,1cyclictest0-21swapper/209:20:022
169106599231,14cyclictest0-21swapper/211:05:342
1691063992320,2cyclictest1979804-21cron10:45:010
1691065992220,1cyclictest0-21swapper/211:20:022
1691064992214,7cyclictest1942991-21idleruntime-cro10:20:001
1691063992213,5cyclictest2147006-21kthreadcore12:35:560
169106599211,9cyclictest0-21swapper/210:55:352
1691064992113,3cyclictest1895594-21kthreadcore09:45:551
1691063992118,2cyclictest1869063-21sh09:30:010
1691063992114,6cyclictest1852719-21timerandwakeup09:16:010
1157598210,4rtkit-daemon1307-21mta-sts-daemon09:43:450
1691065992018,1cyclictest0-21swapper/210:45:032
1691064992017,2cyclictest0-21swapper/109:40:011
1691064992014,1cyclictest1697093-21idleruntime-cro07:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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