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2026-09-07 - 21:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Sep 07, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
258135221050,2sleep30-21swapper/311:29:413
23667082850,0sleep02366711-21cut09:29:400
24765792430,2sleep0241rcuc/010:30:010
23894322390,2sleep20-21swapper/209:42:292
26745392340,1sleep02674541-21cat12:24:390
216673899330,23cyclictest2414555-21munin-run09:55:010
2166738992912,12cyclictest2497721-21irqcore10:44:380
25854892270,2sleep20-21swapper/211:34:332
216673899272,14cyclictest0-21swapper/011:29:170
216673899256,2cyclictest0-21swapper/012:34:410
216673899249,5cyclictest2396343-21cut09:44:450
216673899249,14cyclictest2444438-21irqcore10:14:380
216673899246,10cyclictest2334825-21diskmemload09:47:000
216673899241,5cyclictest0-21swapper/012:06:100
2166738992415,8cyclictest2533487-21kthreadcore11:04:400
2166738992414,6cyclictest2568125-21gltestperf11:24:360
216673899235,2cyclictest0-21swapper/012:01:180
216673899235,13cyclictest0-21swapper/010:59:210
216673899231,5cyclictest0-21swapper/010:21:370
2166738992313,9cyclictest2338620-21kthreadcore09:14:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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