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2026-06-21 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jun 21, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
268622421720,2sleep30-21swapper/307:35:123
304750321560,2sleep30-21swapper/311:55:183
26849172990,2sleep20-21swapper/207:35:032
29831932760,1sleep02983191-21ssh11:14:270
2651813993329,3cyclictest2844097-21grep09:40:010
26706872310,1sleep00-21swapper/007:20:140
2651814992418,2cyclictest67250irq/126-eno110:05:161
2651815992321,1cyclictest0-21swapper/208:10:032
492398220,3rtkit-daemon1237-21mta-sts-daemon09:01:311
2651815992220,1cyclictest0-21swapper/211:10:022
2651815992220,1cyclictest0-21swapper/211:10:022
2651815992220,1cyclictest0-21swapper/210:45:022
265181399228,9cyclictest0-21swapper/012:40:020
2651814992118,2cyclictest2658679-21grep07:15:021
265181399219,7cyclictest0-21swapper/011:40:110
2651813992115,5cyclictest3042440-21cstates11:55:060
2651815992017,1cyclictest0-21swapper/210:25:002
2651814992016,2cyclictest700-21rs:main1
2651814992015,3cyclictest274-21systemd-journal12:29:561
2651814992011,4cyclictest0-21swapper/110:10:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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