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2026-07-21 - 11:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jul 21, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145744021640,2sleep30-21swapper/322:06:063
132020821120,2sleep30-21swapper/320:26:033
150312921050,3sleep30-21swapper/322:36:083
12930962950,2sleep20-21swapper/220:01:092
15287672750,1sleep11528766-21ssh22:52:491
13799762730,1sleep01379973-21ssh21:11:120
1226314992522,2cyclictest664-21dbus-daemon00:20:020
1226315992417,2cyclictest69250irq/121-eno100:40:021
1226314992320,2cyclictest1633531-21apt00:05:000
1226316992211,6cyclictest0-21swapper/222:30:022
1226315992219,2cyclictest664-21dbus-daemon22:30:021
1226315992219,2cyclictest1611267-21sh23:50:011
1226314992213,8cyclictest1226312-21cyclictest21:57:240
3240591211,5phc2sys0-21swapper/319:06:023
1226316992119,1cyclictest0-21swapper/223:20:012
1226315992118,2cyclictest1500020-21systemd22:35:011
122631499217,6cyclictest0-21swapper/019:46:070
1226314992118,2cyclictest1226312-21cyclictest23:10:010
1226315992017,2cyclictest1603862-21cron23:45:011
1226315992017,2cyclictest1568026-21fschecks_count23:21:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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