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2026-08-15 - 00:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Aug 14, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4914212700,1sleep0491419-21ssh11:03:510
178462992716,6cyclictest430348-21grep10:20:251
178462992616,3cyclictest517186-21kthreadcore11:20:221
178461992522,2cyclictest672-21polkitd08:00:270
178462992421,2cyclictest425167-21systemctl10:20:011
178462992413,6cyclictest0-21swapper/109:25:011
178462992413,3cyclictest378490-21kthreadcore09:45:251
178462992412,3cyclictest613755-21kthreadcore12:25:231
178462992411,3cyclictest0-21swapper/111:55:211
178462992410,4cyclictest0-21swapper/110:00:221
178461992414,5cyclictest0-21swapper/011:50:220
178463992320,2cyclictest0-21swapper/211:15:022
178462992320,2cyclictest329592-21systemd-run09:15:021
178462992313,3cyclictest838-21gmain12:14:551
178462992313,3cyclictest453527-21runrttasks10:36:521
178462992312,3cyclictest0-21swapper/111:00:251
178462992310,3cyclictest0-21swapper/109:35:021
178461992315,4cyclictest0-21swapper/012:35:010
178462992219,2cyclictest664-21dbus-daemon10:55:021
178462992219,2cyclictest297696-21gpgconf08:50:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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