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2026-09-01 - 20:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Sep 01, 2026 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199697121020,2sleep30-21swapper/308:05:023
1918416993216,11cyclictest0-21swapper/010:04:500
19826482280,2sleep0241rcuc/007:54:530
191841699260,13cyclictest2079284-21grep09:04:570
191841699260,13cyclictest2079284-21grep09:04:570
191841699256,11cyclictest0-21swapper/012:00:560
191841699254,12cyclictest0-21swapper/010:24:350
1918416992516,8cyclictest932-1atopacctd09:30:020
191841699251,14cyclictest2300629-21ssh11:11:440
191841699250,12cyclictest2052659-21/usr/sbin/munin08:49:540
191841899241,7cyclictest0-21swapper/211:59:262
191841699245,14cyclictest0-21swapper/009:21:020
191841699244,14cyclictest1188-21runrttasks07:38:190
191841699244,14cyclictest1188-21runrttasks07:34:310
191841699244,14cyclictest1188-21runrttasks07:34:310
191841699244,11cyclictest0-21swapper/011:50:150
191841699244,11cyclictest0-21swapper/009:13:570
191841699243,16cyclictest1918750-21taskset07:11:210
191841699243,10cyclictest2314871-21kthreadcore11:19:500
191841699243,10cyclictest2314871-21kthreadcore11:19:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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