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2026-07-27 - 17:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jul 27, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121435821100,2sleep30-21swapper/312:20:013
117332421050,2sleep30-21swapper/311:50:553
111081921010,2sleep30-21swapper/311:10:033
10423882740,1sleep01042386-21ssh10:22:060
9982152720,1sleep0998213-21ssh09:53:080
11618742710,1sleep01161871-21ssh11:43:180
784055992724,2cyclictest790196-21pmu-power07:15:021
784055992724,2cyclictest1140235-21latency_hist11:30:011
784054992622,2cyclictest191rcu_preempt10:15:020
784054992513,2cyclictest191rcu_preempt09:14:410
784054992415,6cyclictest0-21swapper/011:40:030
784054992320,2cyclictest1095464-21wc11:00:000
3240591231,8phc2sys0-21swapper/311:20:463
784056992219,1cyclictest0-21swapper/211:10:012
784055992219,2cyclictest1193216-21cut12:05:491
784055992219,2cyclictest1125447-21munin-run11:20:011
784054992216,5cyclictest962424-21aten_repower_cu09:30:470
784054992214,7cyclictest948888-21kthreadcore09:20:520
784054992214,6cyclictest252575-1atop09:10:010
784055992118,2cyclictest1006276-21munin-run10:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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