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2026-08-29 - 06:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 29, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
297595921040,1sleep00-21swapper/021:39:550
30758992810,2sleep30-21swapper/322:37:473
31135582750,2sleep13113469-21ssh22:59:531
2213291270,4phc2sys0-21swapper/320:59:313
274958399247,10cyclictest0-21swapper/022:34:300
31830622230,2sleep20-21swapper/223:39:312
2749583992316,6cyclictest1011-21gdbus00:40:010
2749584992219,2cyclictest3192669-21ssh23:44:491
2749583992213,5cyclictest3085925-21aten_repower_vo22:44:470
2749584992112,4cyclictest778-21dbus-daemon20:50:031
2749583992112,5cyclictest2741742-21kworker/u16:0-nfsiod22:56:190
2749584992017,2cyclictest0-21swapper/119:15:031
2749584992013,3cyclictest3180009-21/usr/sbin/munin23:34:571
2749583992015,4cyclictest24648-21gmain22:06:550
2749583992013,6cyclictest2749581-21cyclictest23:30:010
30757802190,2sleep00-21swapper/022:37:310
2749585991916,1cyclictest0-21swapper/222:49:542
274958599191,10cyclictest0-21swapper/222:59:322
274958399199,4cyclictest932-1atopacctd23:10:230
274958399197,7cyclictest0-21swapper/000:29:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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