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2026-07-26 - 21:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jul 26, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
342120921530,1sleep13421211-21apt-key10:55:011
318973121040,1sleep10-21swapper/108:05:561
31219472770,2sleep30-21swapper/307:10:563
3117295992822,2cyclictest69250irq/121-eno109:20:551
3117295992714,3cyclictest3495675-21/usr/sbin/munin11:45:511
35296942260,2sleep30-21swapper/312:05:573
3117295992519,2cyclictest69250irq/121-eno110:20:011
3117295992514,3cyclictest3340853-21cpuspeed_turbos10:00:501
3117295992513,3cyclictest0-21swapper/111:30:551
3117295992512,7cyclictest0-21swapper/109:20:031
3117294992515,9cyclictest3282574-21cut09:20:510
3117295992421,2cyclictest3361923-21cron10:15:011
3117294992421,2cyclictest3546467-21awk12:20:010
3117294992411,7cyclictest3502444-21cron11:50:010
3117295992313,3cyclictest3461453-21kthreadcore11:20:551
3117294992316,6cyclictest10930-21cron11:05:000
3117294992316,2cyclictest69250irq/121-eno112:35:020
3117294992315,7cyclictest0-21swapper/007:40:010
3117294992314,5cyclictest3437658-21grep11:05:530
311729499230,5cyclictest3325701-21ssh09:50:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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