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2026-09-19 - 22:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Sep 19, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301406921110,2sleep30-21swapper/311:09:243
31636712440,1sleep03163672-21grep12:34:230
28257122330,1sleep10-21swapper/109:21:261
26537312260,2sleep30-21swapper/307:19:243
263897699243,16cyclictest0-21swapper/009:34:000
2638976992213,8cyclictest2948144-21latency_hist10:30:010
2638976992114,6cyclictest3031971-21kthreadcore11:19:230
263897899202,8cyclictest0-21swapper/210:24:002
2638977992013,3cyclictest2850825-21/usr/sbin/munin09:34:301
263897699209,5cyclictest2910520-21kthreadcore10:09:240
263897699205,9cyclictest2919502-21cut10:14:250
2638976992013,6cyclictest2978041-21kthreadcore10:49:240
2638976992011,6cyclictest3078068-21kthreadcore11:44:230
2213291200,2phc2sys0-21swapper/308:44:173
2638977991912,3cyclictest1188-21runrttasks09:51:281
2638977991910,4cyclictest2860078-21latency_hist09:40:031
263897699198,6cyclictest0-21swapper/012:14:000
263897699198,6cyclictest0-21swapper/009:40:020
263897699198,10cyclictest0-21swapper/011:49:000
263897699197,7cyclictest0-21swapper/010:24:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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