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2026-07-24 - 21:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jul 24, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
397146821030,2sleep03971094-21ssh11:51:010
364083421030,2sleep30-21swapper/307:56:023
384560721020,1sleep10-21swapper/110:26:011
40153422990,2sleep20-21swapper/212:21:012
37231472870,1sleep10-21swapper/109:05:011
3580903992320,2cyclictest4011030-21systemd-run12:20:011
358090299232,16cyclictest0-21swapper/012:31:060
3580903992220,1cyclictest3580900-21cyclictest12:25:021
3580903992211,4cyclictest0-21swapper/111:55:531
3240591220,2phc2sys0-21swapper/309:54:103
3580904992118,1cyclictest0-21swapper/212:05:012
3580904992118,1cyclictest0-21swapper/210:00:012
3580903992113,4cyclictest3823315-21kthreadcore10:11:011
358090299213,12cyclictest664-21dbus-daemon07:30:020
3580902992118,2cyclictest664-21dbus-daemon11:15:020
3580902992113,7cyclictest0-21swapper/011:05:020
3580902992110,6cyclictest0-21swapper/011:46:000
3580904992018,1cyclictest0-21swapper/211:15:022
3580903992017,2cyclictest3595855-21grep07:20:021
3580904991916,2cyclictest0-21swapper/209:51:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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