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2025-11-13 - 07:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Nov 12, 2025 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
379954021900,2sleep30-21swapper/311:03:503
385616621200,1sleep00-21swapper/011:35:460
348907421070,2sleep20-21swapper/207:35:502
3451047992719,3cyclictest0-21swapper/211:30:012
3451046992620,2cyclictest170550irq/121-eno109:35:471
3451046992616,3cyclictest3451043-21cyclictest12:00:411
3451046992515,2cyclictest170550irq/121-eno107:35:011
3451045992521,2cyclictest0-21swapper/012:10:020
3451046992419,3cyclictest3660870-21grep09:45:001
3451046992317,5cyclictest3766502-21sort10:45:421
345104599239,4cyclictest2033-21lldpd10:07:470
3451046992219,2cyclictest3502540-21grep07:50:011
345104599220,8cyclictest3556618-21unixbench_multi08:30:530
3451046992118,2cyclictest1700-21systemd-logind11:45:021
3451045992118,2cyclictest0-21swapper/011:30:010
3451045992112,8cyclictest0-21swapper/011:00:020
835298200,4rtkit-daemon3451043-21cyclictest10:58:151
835298200,3rtkit-daemon3451043-21cyclictest10:06:441
3451046992017,2cyclictest3922624-21latency_hist12:15:011
3451046992017,2cyclictest0-21swapper/108:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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