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2026-07-30 - 19:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 30, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246396021250,1sleep00-21swapper/010:45:550
246396021250,1sleep00-21swapper/010:45:550
247740821050,4sleep00-21swapper/010:54:360
255234221040,2sleep30-21swapper/311:45:423
25147422260,2sleep30-21swapper/311:20:003
2172482992421,2cyclictest2499669-21apt-key11:10:011
2172481992411,7cyclictest0-21swapper/009:20:390
2172483992321,1cyclictest0-21swapper/208:00:012
2172482992320,2cyclictest664-21dbus-daemon11:25:011
2172481992313,5cyclictest2620775-21kthreadcore12:30:590
2172481992313,5cyclictest0-21swapper/009:50:020
2172482992219,2cyclictest2253827-21apt-config08:15:011
2172482992216,2cyclictest191rcu_preempt10:16:041
2172482992214,3cyclictest0-21swapper/111:20:011
2172482992211,5cyclictest0-21swapper/108:56:461
2172481992215,6cyclictest0-21swapper/011:30:020
2172481992213,5cyclictest2427783-21kthreadcore10:20:590
2172481992212,6cyclictest0-21swapper/011:56:010
2172481992212,5cyclictest0-21swapper/009:11:010
2172481992210,7cyclictest0-21swapper/010:45:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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