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2026-05-16 - 11:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat May 16, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18073621510,1sleep0180734-21ssh23:48:560
40416462900,3sleep30-21swapper/319:55:193
41784722780,4sleep04178393-21ssh21:40:130
41596982400,1sleep1191rcu_preempt21:25:551
3976960993020,6cyclictest1-21systemd23:20:010
3976967992820,5cyclictest0-21swapper/220:40:002
3976963992825,2cyclictest3851875-21systemd-journal00:25:001
3976963992721,2cyclictest17350irq/127-ahci[0000:00:17.0]19:25:001
3976960992514,6cyclictest0-21swapper/022:40:010
397696099251,16cyclictest4118069-21latency_hist21:00:010
3976963992416,2cyclictest191rcu_preempt19:40:111
3976960992421,2cyclictest0-21swapper/021:50:000
3976963992316,2cyclictest17350irq/127-ahci[0000:00:17.0]20:40:001
3976963992316,2cyclictest134050irq/121-eno120:00:061
3976960992320,1cyclictest4086190-21gpgv20:35:000
3976960992319,3cyclictest249789-21grep00:35:000
3976960992314,2cyclictest5446-21systemd21:55:010
3976960992313,5cyclictest0-21swapper/000:10:010
3976960992311,5cyclictest0-21swapper/022:20:140
3976967992219,1cyclictest0-21swapper/222:20:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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