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2026-03-19 - 03:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Mar 19, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
152797521190,2sleep30-21swapper/323:21:333
155409221180,1sleep10-21swapper/123:36:341
153931621120,1sleep00-21swapper/023:26:350
11554042990,1sleep20-21swapper/219:15:012
16201582510,2sleep30-21swapper/300:11:393
15514772330,2sleep30-21swapper/323:34:443
1148334992410,4cyclictest0-21swapper/121:40:001
1148334992312,3cyclictest1527256-21fschecks_time23:21:311
1148334992311,7cyclictest1614655-21/usr/sbin/munin00:11:321
1148332992316,2cyclictest2902298rtkit-daemon20:41:320
1148332992310,6cyclictest0-21swapper/021:26:270
1148338992219,1cyclictest0-21swapper/200:35:022
114833499229,4cyclictest0-21swapper/122:11:341
1148334992219,2cyclictest1283755-21cron21:00:001
1148332992216,2cyclictest134050irq/121-eno121:56:340
1148332992211,2cyclictest1578500-21/usr/sbin/munin23:50:020
2649091211,10phc2sys0-21swapper/321:40:013
1148334992110,2cyclictest134050irq/121-eno100:01:361
114833299214,5cyclictest1200454-21sed19:51:330
1148332992115,2cyclictest191rcu_preempt00:35:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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