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2026-07-15 - 17:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 15, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
386508522090,2sleep30-21swapper/312:18:453
358501321260,2sleep30-21swapper/309:11:203
35162382320,2sleep13516241-21aten_repower_fr08:16:161
3434321992421,2cyclictest3552820-21grep08:45:021
3434320992414,6cyclictest3630724-21kthreadcore09:41:230
3434322992322,0cyclictest0-21swapper/209:55:012
3434322992219,1cyclictest0-21swapper/209:40:002
3434320992217,4cyclictest3539977-21latency_hist08:35:010
3434321992118,2cyclictest664-21dbus-daemon12:05:021
3434321992118,2cyclictest3627736-21sh09:40:001
3434321992017,2cyclictest662-21avahi-daemon07:20:011
3434321992017,2cyclictest3769086-21/usr/sbin/munin11:15:011
3434321992017,2cyclictest3739464-21cron10:55:001
3434321992017,2cyclictest0-21swapper/112:15:031
3434321992014,4cyclictest1-21systemd10:45:011
3434320992014,5cyclictest3586695-21kthreadcore09:11:220
3434320992014,1cyclictest35938402cut09:16:220
3434320992013,6cyclictest0-21swapper/012:05:010
3434320992010,5cyclictest0-21swapper/011:05:000
3434322991917,1cyclictest0-21swapper/210:37:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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