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2026-07-22 - 11:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 22, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
349909321050,1sleep10-21swapper/123:53:101
35322482670,1sleep03532251-21cut00:16:060
33529242330,1sleep10-21swapper/122:16:031
3106203993214,10cyclictest0-21swapper/021:15:580
34686622300,2sleep30-21swapper/323:31:123
310620399267,14cyclictest0-21swapper/021:50:590
3240591241,2phc2sys0-21swapper/323:36:073
3106204992219,2cyclictest3514883-21grep00:05:021
3106203992211,6cyclictest0-21swapper/023:01:080
3106204992118,2cyclictest3314023-21grep21:50:021
3106204992114,3cyclictest1053-21snmpd22:46:081
3106203992118,2cyclictest3218071-21sh20:40:020
3106203992112,4cyclictest664-21dbus-daemon22:55:010
3106203992111,6cyclictest0-21swapper/023:45:020
3106203992110,6cyclictest0-21swapper/023:58:030
3106203992110,6cyclictest0-21swapper/021:41:010
3106204992017,2cyclictest3471711-21irqcore23:36:041
3106204992017,2cyclictest3106201-21cyclictest00:20:031
3106204992013,3cyclictest3341977-21pmu-power22:06:121
3106203992017,2cyclictest3388508-21systemd-run22:40:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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