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2026-08-10 - 17:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Aug 10, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137990421490,1sleep11379901-21df_inode10:20:271
12881752580,1sleep11288174-21ssh09:17:421
14516342290,1sleep01451638-21sed11:05:390
14516342290,1sleep01451638-21sed11:05:390
12962162280,1sleep1351ktimers/109:23:391
12962162280,1sleep1351ktimers/109:23:391
1125727992421,2cyclictest1171240-21systemd-run07:45:020
1125727992413,6cyclictest0-21swapper/012:00:310
112572799241,11cyclictest1483201-21ssh11:30:010
1125729992320,1cyclictest0-21swapper/211:55:012
1125729992319,2cyclictest0-21swapper/207:20:012
1125729992219,1cyclictest0-21swapper/211:15:012
1125729992213,1cyclictest0-21swapper/209:10:012
1125729992213,1cyclictest0-21swapper/209:10:012
1125727992214,7cyclictest0-21swapper/008:40:010
1125727992211,6cyclictest662-21avahi-daemon09:15:020
1125727992210,5cyclictest0-21swapper/010:35:020
1157598210,5rtkit-daemon1300-21mta-sts-daemon11:11:341
1125729992116,3cyclictest0-21swapper/207:15:022
112572899214,5cyclictest69250irq/121-eno108:05:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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