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2025-12-28 - 00:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Dec 27, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7327952470,1sleep00-21swapper/009:58:250
7140322450,1sleep00-21swapper/009:48:230
498901992724,1cyclictest0-21swapper/210:45:002
498901992724,1cyclictest0-21swapper/210:45:002
49889999269,5cyclictest0-21swapper/009:53:180
498899992614,6cyclictest704148-21ssh09:43:200
498899992523,1cyclictest498897-21cyclictest12:03:300
498900992413,5cyclictest134050irq/121-eno111:23:331
6773152230,2sleep00-21swapper/009:28:190
498899992311,4cyclictest847187-21runrttasks10:59:530
498900992219,2cyclictest865377-21ls11:10:011
49889999227,6cyclictest0-21swapper/009:18:190
498899992211,5cyclictest988325-21kthreadcore12:18:260
10242942220,1sleep01024295-21kthreadcore12:38:240
5561312210,2sleep0498897-21cyclictest07:55:020
498901992118,1cyclictest0-21swapper/207:35:012
498900992118,2cyclictest983569-21sh12:15:001
498900992117,2cyclictest0-21swapper/109:35:011
498900992115,2cyclictest134050irq/121-eno109:23:261
49889999219,4cyclictest895110-21/usr/sbin/munin11:28:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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