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2026-07-12 - 14:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jul 12, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345719421120,2sleep30-21swapper/322:49:423
32506572280,2sleep20-21swapper/220:19:442
3163450992821,3cyclictest191rcu_preempt21:35:021
3163449992817,7cyclictest3163447-21cyclictest00:39:420
3163450992614,7cyclictest3337386-21sed21:29:401
3163450992512,8cyclictest3516865-21kthreadcore23:29:401
3163450992512,8cyclictest3489058-21latency23:09:421
3163450992421,2cyclictest3356844-21grep21:40:011
3163450992411,8cyclictest3482708-21latency_hist23:05:011
3163451992320,1cyclictest0-21swapper/222:45:012
3163450992319,3cyclictest3196590-21systemd19:35:011
3163450992319,3cyclictest3170069-21hddtemp_smartct19:15:021
3163450992314,3cyclictest0-21swapper/123:15:031
3163449992311,7cyclictest0-21swapper/021:54:440
3163449992311,6cyclictest0-21swapper/000:34:360
33335412220,2sleep30-21swapper/321:24:413
316345099228,6cyclictest0-21swapper/123:54:371
3163450992211,7cyclictest3429598-21kthreadcore22:29:421
3163450992211,5cyclictest1237-21mta-sts-daemon21:45:071
3163450992210,7cyclictest0-21swapper/120:45:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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