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2026-07-22 - 23:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 22, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278922710,1sleep127891-21ssh09:29:321
1468262710,1sleep0146824-21ssh10:50:030
41481522390,2sleep30-21swapper/308:31:113
4043300993311,20cyclictest0-21swapper/011:51:120
4043302992923,2cyclictest69250irq/121-eno112:21:051
4043300992817,4cyclictest40536-21kthreadcore09:36:070
4043300992613,5cyclictest255528-21open_files12:01:080
4043300992612,6cyclictest1300-21mta-sts-daemon10:05:230
4043300992612,6cyclictest0-21swapper/009:41:020
4043300992611,6cyclictest0-21swapper/011:46:010
4043300992519,5cyclictest198303-21cron11:25:000
4043300992514,4cyclictest181586-21grep11:11:070
4043302992416,3cyclictest118928-21kthreadcore10:31:041
404330099249,5cyclictest134447-21kthreadcore10:41:060
4043300992418,2cyclictest4174973-21gltestperf08:56:030
4043300992418,2cyclictest4160644-21proc_pri08:41:070
4043300992411,5cyclictest17788-21kthreadcore09:21:070
4043300992411,5cyclictest0-21swapper/010:15:000
404330099235,6cyclictest0-21swapper/012:20:020
404330099235,4cyclictest132082-21sh10:40:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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