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2026-08-23 - 05:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Aug 23, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295589722490,2sleep30-21swapper/300:10:063
285515821100,2sleep30-21swapper/323:15:023
271555121020,2sleep30-21swapper/321:55:053
27624422380,1sleep00-21swapper/022:22:110
29306852300,1sleep00-21swapper/023:55:040
28798952290,1sleep20-21swapper/223:29:442
28212872290,2sleep20-21swapper/222:55:052
2466648992912,12cyclictest2644673-21kthreadcore21:15:060
246664899279,14cyclictest2768126-21kthreadcore22:25:050
246664899278,11cyclictest2667788-21kthreadcore21:30:040
246664899277,2cyclictest1-21systemd20:40:030
246664999264,3cyclictest1188-21runrttasks23:48:391
246664899268,14cyclictest2466646-21cyclictest00:10:110
246664899258,10cyclictest0-21swapper/021:56:440
29405532240,1sleep00-21swapper/000:00:250
2466649992416,7cyclictest2533490-21appstreamcli20:00:021
2466649992415,8cyclictest2859121-21missed_timers23:15:051
246664899247,2cyclictest0-21swapper/021:41:450
246664899245,3cyclictest2630180-21/usr/sbin/munin21:10:100
246664899244,6cyclictest2906698-21/usr/sbin/munin23:45:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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