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2026-06-03 - 01:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jun 02, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
400148422210,2sleep30-21swapper/309:25:023
401828021010,2sleep30-21swapper/309:39:423
39852962510,1sleep00-21swapper/009:14:530
39866382480,1sleep00-21swapper/009:16:300
41162132390,1sleep04116215-21ssh10:43:360
41571012300,2sleep20-21swapper/211:09:472
3825556992719,3cyclictest0-21swapper/111:25:021
3825561992618,4cyclictest0-21swapper/209:34:402
382554899261,7cyclictest4008801-21true09:30:000
3825561992519,2cyclictest0-21swapper/212:29:432
3825548992519,5cyclictest4170437-21ps11:19:470
3825548992514,10cyclictest4140027-21idleruntime10:59:450
40408832240,2sleep04040823-21ssh09:54:420
3825548992418,5cyclictest4182888-21ssh11:25:010
382556199233,8cyclictest0-21swapper/209:44:412
382554899233,7cyclictest3941041-21munin-run08:40:010
3825548992319,3cyclictest3897193-21munin-run08:04:590
3825548992318,4cyclictest0-21swapper/010:50:020
3825548992310,8cyclictest4023829-21latency_hist09:40:020
382554899230,3cyclictest57560-21ssh12:10:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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