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2025-11-30 - 20:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Nov 30, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
164610821470,1sleep11646105-21df10:35:191
15942552300,1sleep00-21swapper/010:05:200
1349024992412,7cyclictest0-21swapper/007:35:010
1349024992316,6cyclictest1716350-21irqrtprio11:15:220
1349024992314,5cyclictest1753337-21kthreadcore11:35:230
1349026992219,1cyclictest0-21swapper/209:40:012
1349024992215,6cyclictest1632299-21kthreadcore10:25:230
1349024992214,5cyclictest1607646-21sed10:10:290
1349024992211,7cyclictest1508725-21kthreadcore09:15:250
1349026992118,1cyclictest0-21swapper/212:20:002
1349026992116,2cyclictest0-21swapper/209:30:002
1349025992118,2cyclictest1635-21dbus-daemon08:50:011
1349025992118,2cyclictest1355873-21kthreadcore07:15:021
1349024992113,7cyclictest1778721-21kthreadcore11:50:210
1349024992113,7cyclictest0-21swapper/012:20:000
1349024992112,5cyclictest1732774-21cstates11:25:170
302487291200,3phc2sys0-21swapper/309:55:023
16680902200,2sleep30-21swapper/310:45:273
16680902200,2sleep30-21swapper/310:45:273
1349026992018,1cyclictest0-21swapper/209:00:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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