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2026-07-10 - 17:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jul 10, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
67410321080,1sleep00-21swapper/011:24:010
5374452980,2sleep30-21swapper/309:49:453
5215002350,2sleep30-21swapper/309:39:433
33122999288,9cyclictest0-21swapper/010:05:030
331229992818,9cyclictest657742-21grep11:10:010
331229992810,12cyclictest711367-21aten_repower_po11:49:360
33122999270,5cyclictest517257-21ssh09:35:200
331229992617,5cyclictest724247-21/usr/sbin/munin11:55:010
33122999260,3cyclictest629968-21/usr/sbin/munin10:54:370
33122999255,14cyclictest769260-21sh12:25:340
331229992522,2cyclictest406497-21systemd08:10:010
331229992517,7cyclictest728135-21kthreadcore11:59:420
331229992515,8cyclictest781-21gmain09:10:020
33122999250,14cyclictest400012-21python308:04:500
33122999244,14cyclictest0-21swapper/012:34:350
33122999243,12cyclictest431284-21taskset08:30:020
33122999243,12cyclictest431284-21taskset08:30:020
331229992415,8cyclictest526390-21tr09:44:370
331229992415,8cyclictest0-21swapper/008:45:000
331229992414,6cyclictest331227-21cyclictest12:15:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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