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2026-08-27 - 08:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Aug 27, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31761442840,1sleep20-21swapper/200:36:242
2645703993110,8cyclictest2886964-21kthreadcore21:54:570
2645703993110,8cyclictest2886964-21kthreadcore21:54:570
264570399308,15cyclictest0-21swapper/022:35:010
2645703992715,11cyclictest2873813-21systemd-run21:45:010
2645703992715,11cyclictest2687475-21cut19:40:020
2645703992711,6cyclictest3020865-21kthreadcore23:09:560
264570399267,6cyclictest0-21swapper/022:45:010
264570399267,5cyclictest0-21swapper/000:29:530
264570399261,8cyclictest0-21swapper/023:44:350
2645703992613,4cyclictest2645701-21cyclictest23:55:030
2645703992613,4cyclictest2645701-21cyclictest19:54:420
2645703992612,2cyclictest3059827-21/usr/sbin/munin23:30:030
264570499251,3cyclictest1-21systemd21:00:031
264570399258,5cyclictest3134854-21kthreadcore00:14:550
264570399255,6cyclictest0-21swapper/019:28:390
264570399251,9cyclictest3147363-21cut00:20:000
2645703992511,6cyclictest3093664-21kthreadcore23:49:590
2645703992511,5cyclictest3009426-21acpi23:04:330
2645703992511,5cyclictest2739095-21kthreadcore20:19:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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