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2026-09-20 - 10:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Sep 20, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
395021021070,1sleep00-21swapper/021:50:030
37452942370,2sleep03745300-21kthreadcore19:34:230
3711384993014,12cyclictest55045-21kthreadcore00:39:240
37761012260,2sleep30-21swapper/319:55:023
371138499252,16cyclictest0-21swapper/021:19:020
371138499245,12cyclictest0-21swapper/023:28:430
371138499245,11cyclictest0-21swapper/022:50:170
371138499242,14cyclictest0-21swapper/023:25:020
3711384992415,8cyclictest4091116-21latency_hist23:10:010
371138499241,16cyclictest3831729-21/usr/sbin/munin20:39:280
371138499235,9cyclictest0-21swapper/022:15:030
371138499234,12cyclictest0-21swapper/023:50:520
371138499234,12cyclictest0-21swapper/022:12:080
371138499232,16cyclictest0-21swapper/000:18:580
371138499231,4cyclictest3728090-21runrttasks19:22:490
371138499231,3cyclictest3907944-21taskset21:28:390
371138499231,3cyclictest3797117-21taskset20:11:510
371138499231,14cyclictest4175784-21kthreadcore23:59:240
371138499231,14cyclictest4175784-21kthreadcore23:59:240
371138499231,13cyclictest0-21swapper/023:35:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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