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2026-06-30 - 23:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jun 30, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286818121470,2sleep20-21swapper/209:29:592
294702721080,4sleep12947029-21awk10:25:011
30238692700,1sleep13023868-21ssh11:16:231
29512952580,1sleep02951293-21ssh10:27:570
2693747993221,2cyclictest67250irq/126-eno111:55:011
2693746993210,21cyclictest0-21swapper/009:49:560
29760932290,2sleep30-21swapper/310:44:593
2693746992922,5cyclictest0-21swapper/012:25:010
2693746992919,9cyclictest1-21systemd10:50:010
2693747992818,3cyclictest0-21swapper/110:50:021
2693746992816,8cyclictest274-21systemd-journal12:17:010
2693746992719,4cyclictest67250irq/126-eno108:39:520
2693747992623,2cyclictest660-21dbus-daemon10:35:021
2693747992623,2cyclictest3051915-21latency_hist11:35:011
2693746992620,5cyclictest660-21dbus-daemon11:20:030
2693746992618,4cyclictest67250irq/126-eno107:29:530
2693746992614,11cyclictest3105720-21cpu12:14:500
2693746992613,9cyclictest2842861-21kthreadcore09:15:000
2693747992521,3cyclictest2814721-21missed_timers08:50:001
2693747992517,4cyclictest3110638-21ssh12:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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