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2026-02-22 - 15:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Feb 22, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247477621040,1sleep12474777-21dpkg08:05:011
282939221000,2sleep30-21swapper/311:45:013
26604622980,2sleep20-21swapper/210:10:012
24221362930,2sleep1341rcuc/107:22:091
26439282330,3sleep30-21swapper/310:02:013
26947482310,1sleep10-21swapper/110:28:281
24540342280,2sleep30-21swapper/307:47:113
2405888992315,3cyclictest2890158-21runrttasks12:17:371
2405888992315,3cyclictest1296-21polkitd09:40:011
2405888992219,2cyclictest2672008-21irqrtprio10:17:061
2405884992213,5cyclictest2697277-21/usr/sbin/munin10:32:110
26695152210,2sleep00-21swapper/010:15:080
2405894992119,1cyclictest0-21swapper/211:10:012
2405894992118,1cyclictest0-21swapper/209:40:012
2405884992111,6cyclictest2647662-21kthreadcore10:02:100
2649091200,2phc2sys0-21swapper/312:27:113
24261122200,1sleep00-21swapper/007:22:160
2405888992017,2cyclictest2412001-21latency_hist07:15:001
2405888992013,3cyclictest2765719-21runrttasks11:08:201
2405884992013,6cyclictest2815890-21kthreadcore11:37:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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