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2026-06-29 - 12:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 29, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13008021620,2sleep30-21swapper/322:05:033
4388521190,2sleep30-21swapper/321:05:033
5127121000,2sleep30-21swapper/321:10:043
3507782790,1sleep0350776-21ssh00:33:170
4095848993431,1cyclictest0-21swapper/221:50:032
4095844993124,2cyclictest67250irq/126-eno122:40:011
4095844992724,2cyclictest263373-21cut23:35:021
4095848992624,1cyclictest0-21swapper/223:05:022
4095844992521,3cyclictest4156330-21kthreadcore20:00:011
4095844992521,3cyclictest4156330-21kthreadcore20:00:011
4095842992522,2cyclictest302376-21kthreadcore00:00:040
12562250,1sleep01265-21kthreadcore20:30:010
4095848992422,1cyclictest0-21swapper/221:30:022
3153791247,2phc2sys0-21swapper/323:42:043
4095844992320,2cyclictest263820-21kthreadcore23:35:041
4095842992320,2cyclictest271165-21/usr/sbin/munin23:40:010
4095842992320,2cyclictest1-21systemd21:00:000
4095848992210,9cyclictest0-21swapper/223:45:002
4095844992219,2cyclictest660-21dbus-daemon22:10:001
4095842992219,2cyclictest361526-21kthreadcore00:40:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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