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2026-06-14 - 09:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jun 14, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13497422970,2sleep20-21swapper/220:35:272
16885272700,1sleep11688526-21ssh00:32:201
1238234992317,2cyclictest67250irq/126-eno122:35:311
1238234992317,2cyclictest67250irq/126-eno122:15:241
1238233992320,2cyclictest1375031-21munin-run21:00:010
1238233992214,4cyclictest1604210-21sed23:35:260
1238237992118,1cyclictest0-21swapper/221:22:372
1238234992118,2cyclictest1512656-21systemd22:35:011
1238234992118,2cyclictest1394741-21grep21:15:031
1238234992114,2cyclictest0-21swapper/121:35:011
1238234992112,1cyclictest191rcu_preempt22:06:521
1238233992118,2cyclictest1301859-21/usr/sbin/munin20:00:010
1238233992111,6cyclictest0-21swapper/021:15:010
1238233992111,5cyclictest0-21swapper/000:25:020
1238234992017,2cyclictest660-21dbus-daemon21:25:001
1238234992017,2cyclictest1579194-21sort23:20:031
1238234992011,1cyclictest191rcu_preempt19:35:231
1238234992011,1cyclictest191rcu_preempt19:35:231
1238237991916,1cyclictest0-21swapper/221:40:012
1238237991916,1cyclictest0-21swapper/219:15:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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