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2026-08-02 - 07:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Aug 02, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301374421100,2sleep03013741-21ssh23:51:210
269886721100,1sleep00-21swapper/020:10:020
27937022610,1sleep12793701-21ssh21:24:291
30661222560,1sleep13066121-21ssh00:28:141
2622897993624,6cyclictest0-21swapper/219:55:322
2622896992819,2cyclictest69250irq/121-eno121:35:031
2622896992623,2cyclictest0-21swapper/123:55:021
30700652250,0sleep03070068-21cut00:30:530
2622895992518,6cyclictest2893165-21kthreadcore22:30:550
2622896992414,3cyclictest1141-21ntpd23:30:321
262289599243,12cyclictest759-1atopacctd21:10:320
2622896992320,2cyclictest2629566-21latency19:15:021
262289599231,8cyclictest3033495-21cut00:05:590
1157598230,6rtkit-daemon36-21ksoftirqd/123:04:001
28224522220,2sleep20-21swapper/221:42:092
2622897992220,1cyclictest0-21swapper/221:35:032
2622897992219,1cyclictest0-21swapper/223:05:022
2622895992218,3cyclictest0-21swapper/019:35:010
2622895992213,5cyclictest0-21swapper/022:40:410
28287932210,1sleep12828795-21grub-editenv21:45:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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