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2026-08-01 - 12:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 01, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120630121050,2sleep30-21swapper/300:25:583
106150721050,3sleep30-21swapper/322:45:543
10056202720,1sleep01005618-21ssh22:07:350
768884992421,1cyclictest0-21swapper/223:05:012
768884992321,1cyclictest0-21swapper/221:45:022
768884992320,1cyclictest0-21swapper/200:25:012
768882992320,2cyclictest759-1atopacctd21:20:010
768882992320,2cyclictest1177311-21grep00:05:010
768882992315,7cyclictest0-21swapper/022:40:010
768883992219,2cyclictest886901-21dump-pmu-power20:45:001
768883992219,2cyclictest1216365-21cron00:35:011
768883992118,2cyclictest1-21systemd22:20:021
768883992118,2cyclictest0-21swapper/100:10:021
768882992118,2cyclictest774988-21open_inodes19:15:010
768882992111,6cyclictest0-21swapper/022:00:020
768883992017,2cyclictest1006813-21munin-run22:10:011
768883992017,2cyclictest0-21swapper/119:15:021
768883992013,3cyclictest981073-21kthreadcore21:50:581
768883992012,3cyclictest1306-21mta-sts-daemon23:58:211
768883992011,4cyclictest964055-21kthreadcore21:40:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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