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2026-05-11 - 01:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun May 10, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
193989121930,2sleep30-21swapper/309:10:203
18013152300,1sleep10-21swapper/107:20:211
1782505992616,9cyclictest1993779-21kthreadcore09:45:210
1782505992418,5cyclictest1789196-21kthreadcore07:15:020
1782505992417,5cyclictest2080784-21latency_hist10:45:020
1782505992410,9cyclictest0-21swapper/009:30:260
178250799238,6cyclictest0-21swapper/210:30:012
1782507992321,1cyclictest0-21swapper/212:20:582
178250599239,9cyclictest0-21swapper/010:15:140
1782505992318,4cyclictest1923533-21latency_hist09:00:000
1782505992316,6cyclictest1873034-21systemd08:20:010
1782505992316,5cyclictest0-21swapper/008:35:010
1782505992316,5cyclictest0-21swapper/008:05:010
1782505992315,4cyclictest134050irq/121-eno107:35:170
178250599231,18cyclictest0-21swapper/011:16:130
178250599231,14cyclictest2149462-21sh11:30:010
1782505992310,9cyclictest0-21swapper/010:25:010
1782505992310,12cyclictest0-21swapper/010:35:220
1782507992215,3cyclictest0-21swapper/209:15:132
1782505992215,5cyclictest0-21swapper/008:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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