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2026-07-16 - 06:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 16, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24566121910,1sleep30-21swapper/320:00:003
40551521010,1sleep1191rcu_preempt22:00:011
4883172360,4sleep00-21swapper/022:56:150
182481992522,2cyclictest188640-21missed_timers19:15:020
182481992320,2cyclictest664-21dbus-daemon21:50:010
182481992320,2cyclictest664-21dbus-daemon21:30:020
3240591220,1phc2sys0-21swapper/323:56:153
182482992219,2cyclictest664-21dbus-daemon21:25:011
182481992219,2cyclictest561129-21idleruntime-cro23:45:010
182481992213,8cyclictest1-21systemd21:10:020
182481992213,8cyclictest1-21systemd21:10:020
182481992213,5cyclictest460779-21kthreadcore22:36:220
182481992213,5cyclictest1307-21mta-sts-daemon21:34:270
182483992119,0cyclictest0-21swapper/200:05:022
182482992118,2cyclictest664-21dbus-daemon23:00:011
182482992118,2cyclictest0-21swapper/122:50:011
182481992112,5cyclictest499959-21missed_timers23:01:210
182482992018,1cyclictest331609-21/usr/sbin/munin21:10:031
182482992018,1cyclictest331609-21/usr/sbin/munin21:10:031
182482992017,2cyclictest442444-21cron22:25:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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