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2026-01-15 - 13:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jan 15, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7316592990,2sleep1731620-21gltestperf22:37:561
428800992617,2cyclictest134050irq/121-eno122:58:041
428800992415,3cyclictest1313-21gmain22:30:011
428800992311,3cyclictest0-21swapper/121:55:021
428801992220,1cyclictest0-21swapper/223:15:012
428801992219,1cyclictest0-21swapper/200:00:012
428800992211,2cyclictest134050irq/121-eno122:10:011
428799992216,2cyclictest134050irq/121-eno119:36:180
428799992212,6cyclictest920729-21kthreadcore00:22:590
428801992119,1cyclictest0-21swapper/221:00:022
428800992112,2cyclictest2902298rtkit-daemon23:59:451
428799992116,3cyclictest0-21swapper/000:40:010
428799992115,2cyclictest134050irq/121-eno123:45:020
428799992115,2cyclictest134050irq/121-eno122:07:520
428799992115,2cyclictest134050irq/121-eno122:05:010
428799992113,7cyclictest0-21swapper/021:20:010
428799992111,4cyclictest933255-21awk00:28:040
6943332200,2sleep20-21swapper/222:16:412
5400582200,2sleep0540043-21munin-run20:40:010
428800992016,3cyclictest473170-21timerwakeupswit19:43:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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