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2026-08-28 - 17:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Aug 28, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171272521100,2sleep30-21swapper/307:35:013
22093222590,0sleep12209319-21telnet12:39:321
21133732300,1sleep00-21swapper/011:44:510
1675933993016,7cyclictest2212467-21kthreadcore12:39:550
2447398260,12rtkit-daemon932-1atopacctd11:50:050
17685612260,2sleep10-21swapper/108:19:321
22001612240,2sleep00-21swapper/012:33:580
1675934992214,7cyclictest24615-21JS14:54:061
1675933992212,6cyclictest1867559-21kthreadcore09:24:550
1675935992118,1cyclictest0-21swapper/209:18:092
1675933992112,5cyclictest2089202-21kthreadcore11:29:550
17488542200,2sleep11748861-21irqcore08:04:531
17488542200,2sleep11748861-21irqcore08:04:531
1675934992017,2cyclictest24610-21gmain10:33:171
1675934992015,4cyclictest24617-21JS14:54:061
1675934992015,1cyclictest82050irq/121-eno112:05:231
1675934992014,2cyclictest82050irq/121-eno110:40:021
167593399208,7cyclictest0-21swapper/011:40:030
1675933992016,3cyclictest1-21systemd09:45:000
1675933992011,5cyclictest2178490-21kthreadcore12:19:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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