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2026-07-24 - 01:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 23, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205562821010,1sleep10-21swapper/111:21:151
19667102700,1sleep11966709-21ssh10:22:031
18716782290,1sleep10-21swapper/109:20:311
1707724992413,6cyclictest0-21swapper/010:20:020
1707725992316,3cyclictest2005685-21grep10:50:561
1707724992312,6cyclictest0-21swapper/009:31:040
1707726992215,3cyclictest0-21swapper/210:15:562
1707725992215,3cyclictest1976509-21head10:30:591
1707724992219,2cyclictest2123990-21dpkg12:10:020
1707724992218,2cyclictest2109265-21latency_hist12:00:030
1707724992212,6cyclictest0-21swapper/011:20:010
1707726992118,1cyclictest0-21swapper/210:40:022
170772599217,2cyclictest191rcu_preempt08:40:011
1707724992118,2cyclictest1982518-21cron10:35:010
1707724992118,2cyclictest1938060-21munin-run10:05:010
1707724992115,2cyclictest17750irq/127-ahci[0000:00:17.0]08:30:010
1707724992113,7cyclictest2131522-21awk12:15:010
1707724992111,5cyclictest0-21swapper/009:51:090
1707725992017,2cyclictest2168665-21latency_hist12:40:011
1707725992017,2cyclictest2126042-21kthreadcore12:11:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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