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2026-08-16 - 19:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Aug 16, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2690421150,3sleep30-21swapper/311:15:193
11284021100,2sleep20-21swapper/212:15:142
1046742470,2sleep20-21swapper/212:10:012
3888822992616,5cyclictest0-21swapper/010:45:020
3888822992616,5cyclictest0-21swapper/009:35:020
3888825992418,2cyclictest69250irq/121-eno111:18:011
3888825992418,2cyclictest69250irq/121-eno111:05:031
3888822992421,2cyclictest1-21systemd09:10:010
3888825992317,2cyclictest69250irq/121-eno112:20:011
3888822992315,4cyclictest40554-21kthreadcore11:25:170
3888828992219,1cyclictest0-21swapper/212:30:222
3888828992219,1cyclictest0-21swapper/208:20:002
3888825992219,2cyclictest3984123-21munin-plugin-st08:30:001
3888825992219,2cyclictest268-21systemd-journal11:30:001
3888825992216,2cyclictest69250irq/121-eno111:36:511
3888822992214,5cyclictest2411-21fschecks_time11:00:150
3888822992213,5cyclictest60897-21aten_repower_vo11:40:100
3888825992118,2cyclictest3971892-21idleruntime-cro08:20:001
3888825992115,2cyclictest69250irq/121-eno110:15:151
3888825992115,2cyclictest0-21swapper/109:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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