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2026-01-14 - 19:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jan 14, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
404301721050,2sleep20-21swapper/211:48:492
387958521010,3sleep30-21swapper/310:18:043
36138932470,2sleep30-21swapper/307:10:003
39950452290,3sleep10-21swapper/111:22:591
37745602270,1sleep20-21swapper/209:17:592
3614117992717,5cyclictest134050irq/121-eno112:15:011
3614123992421,1cyclictest0-21swapper/210:15:022
3614117992414,9cyclictest1288-1atopacctd10:23:021
3614117992414,8cyclictest3927522-21/usr/sbin/munin10:45:011
3614117992314,8cyclictest3873380-21apt-config10:15:011
3614117992215,6cyclictest0-21swapper/112:40:021
3614117992215,6cyclictest0-21swapper/112:40:021
3614117992213,8cyclictest3701330-21latency_hist08:20:001
3614117992212,9cyclictest3614108-21cyclictest10:28:021
3614117992211,2cyclictest0-21swapper/109:10:001
3614114992219,2cyclictest3652801-21sendmail07:40:000
3614114992219,2cyclictest3614108-21cyclictest11:20:000
361411799215,4cyclictest3974390-21aten_repower_fr11:12:541
3614117992113,7cyclictest4111962-21kthreadcore12:28:001
3614117992112,8cyclictest3945397-21latency_hist10:55:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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