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2026-06-28 - 21:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jun 28, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345918421050,2sleep30-21swapper/310:54:593
344192321050,2sleep13441909-21ssh10:44:551
35851752670,1sleep03585162-21ssh12:19:570
34441672460,2sleep30-21swapper/310:45:013
34537542320,3sleep30-21swapper/310:50:023
36033722310,1sleep20-21swapper/212:30:012
3155924993123,7cyclictest0-21swapper/008:50:010
3155924992818,9cyclictest3452910-21kthreadcore10:50:010
3155924992811,12cyclictest3509022-21acpi11:29:550
3155924992713,12cyclictest3368626-21kernelversion09:55:020
31893152260,2sleep20-21swapper/207:35:082
3155924992617,8cyclictest3581680-21grep12:15:020
315592499257,6cyclictest0-21swapper/011:24:550
315592499257,6cyclictest0-21swapper/011:14:550
315592499257,13cyclictest0-21swapper/008:15:010
3155926992421,1cyclictest0-21swapper/211:40:022
3155925992421,2cyclictest3347697-21kthreadcore09:40:031
3155924992422,1cyclictest3172601-21irqrtprio07:25:010
3155924992421,2cyclictest3345880-21munin-run09:40:000
315592499241,6cyclictest3208341-21sh07:54:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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