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2026-08-15 - 06:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 15, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118974821100,2sleep30-21swapper/320:15:163
12373642920,2sleep30-21swapper/320:50:263
13974392510,0sleep01397440-21/usr/sbin/munin22:45:060
1112419993519,11cyclictest759-1atopacctd22:10:201
14793742340,2sleep20-21swapper/223:40:152
13650662340,2sleep01364385-21ssh22:20:210
1112419993423,6cyclictest191rcu_preempt22:40:021
1112419993318,11cyclictest1271575-21latency_hist21:20:021
1112419992914,11cyclictest1402732-21grep22:45:251
1112419992820,7cyclictest664-21dbus-daemon22:25:001
13619652260,2sleep20-21swapper/222:20:192
1112419992620,2cyclictest69250irq/121-eno119:40:011
1112419992521,2cyclictest0-21swapper/122:05:041
1112419992517,7cyclictest759-1atopacctd22:30:011
1112418992417,6cyclictest1346027-21cpuspeed_turbos22:10:160
111241999239,9cyclictest1527223-21kthreadcore00:10:191
111241999234,10cyclictest1309-21mta-sts-daemon23:32:301
1112419992316,3cyclictest1326171-21kthreadcore21:55:221
111241999231,5cyclictest1034-21runrttasks19:31:141
1112419992315,7cyclictest1537030-21unixbench-2d00:15:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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