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2026-07-01 - 13:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 01, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
396632221060,1sleep00-21swapper/023:29:580
400195121020,1sleep00-21swapper/023:54:550
38981432970,2sleep30-21swapper/322:44:563
38680522740,2sleep10-21swapper/122:24:501
39321722290,1sleep13931625-21latency_hist23:05:021
38759972290,2sleep30-21swapper/322:29:533
3616646992825,1cyclictest0-21swapper/219:30:022
37264742270,1sleep03726475-21cut20:40:010
3616644992718,5cyclictest3843664-21grep22:05:020
3616644992522,2cyclictest3714579-21/usr/sbin/munin20:30:010
3616646992421,1cyclictest0-21swapper/220:55:022
3616645992421,2cyclictest4013086-21date00:00:011
3616644992414,6cyclictest0-21swapper/000:20:010
3616646992320,1cyclictest0-21swapper/222:30:012
3616645992320,2cyclictest693-21systemd-logind19:35:011
3616644992318,4cyclictest3777798-21sed21:20:030
3616644992314,5cyclictest3825223-21kthreadcore21:54:590
3616646992219,1cyclictest0-21swapper/221:05:022
3616645992220,1cyclictest0-21swapper/100:19:571
3616645992217,1cyclictest67250irq/126-eno122:44:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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