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2026-07-18 - 10:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jul 18, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22704221050,1sleep00-21swapper/000:36:420
13231421040,2sleep0101114-21kworker/0:1+events23:36:100
40563382740,2sleep30-21swapper/320:26:163
2064032730,1sleep0206401-21ssh00:25:240
41150702440,1sleep20-21swapper/221:11:192
2045242340,2sleep30-21swapper/300:21:263
3960796992919,2cyclictest69250irq/121-eno121:30:031
3960797992421,1cyclictest0-21swapper/221:45:012
3960796992414,3cyclictest3960794-21cyclictest21:55:031
3960796992413,2cyclictest1306-21mta-sts-daemon23:28:161
3960795992416,7cyclictest662-21avahi-daemon00:35:020
3960795992320,2cyclictest664-21dbus-daemon20:30:030
3960797992219,1cyclictest0-21swapper/222:05:012
3960796992217,3cyclictest4127857-21grep21:21:151
3960796992217,3cyclictest0-21swapper/123:25:021
3960795992216,2cyclictest69250irq/121-eno122:10:010
3960797992118,1cyclictest0-21swapper/221:30:012
3960796992118,2cyclictest4191457-21latency_hist22:05:021
3960796992118,2cyclictest190982-21systemd00:15:011
3960796992117,2cyclictest69250irq/121-eno100:16:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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