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2026-09-21 - 00:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Sep 20, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
82849322410,2sleep30-21swapper/309:49:213
79194022410,2sleep30-21swapper/309:29:203
10596672830,0sleep01059669-21latency_hist12:00:020
7821712710,1sleep0782174-21sort09:24:200
593464992819,8cyclictest940384-21kthreadcore10:54:210
593464992417,6cyclictest886200-21/usr/sbin/munin10:24:210
593466992319,2cyclictest0-21swapper/208:55:092
593464992314,8cyclictest836022-21kthreadcore09:54:200
593464992311,6cyclictest0-21swapper/009:10:020
593464992217,4cyclictest733736-21unixbench_multi08:49:280
593464992216,5cyclictest1017714-21/usr/sbin/munin11:39:230
593464992216,5cyclictest1017714-21/usr/sbin/munin11:39:230
593464992213,6cyclictest778-21dbus-daemon11:30:030
593464992211,6cyclictest0-21swapper/009:19:200
59346599219,3cyclictest836866-21kthreadcore09:54:211
593465992118,2cyclictest778-21dbus-daemon08:05:021
593465992118,2cyclictest778-21dbus-daemon08:05:021
593465992117,3cyclictest787193-21mailstats09:24:281
593465992112,3cyclictest1004351-21kthreadcore11:29:221
593464992114,6cyclictest871850-21kthreadcore10:14:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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