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2025-12-02 - 21:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Dec 02, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11734162990,1sleep10-21swapper/107:35:211
15620212980,1sleep11562029-21tr11:45:201
15418472810,2sleep11541849-21sed11:35:181
1138148992713,13cyclictest1583747-21awk12:00:000
1138148992612,6cyclictest0-21swapper/011:55:000
113814899259,7cyclictest0-21swapper/011:40:140
1138148992518,2cyclictest1592450-21turbostat12:05:000
1138148992513,7cyclictest0-21swapper/010:45:020
835298240,3rtkit-daemon491rcuog/207:29:551
1138148992412,7cyclictest0-21swapper/011:15:220
113814899239,6cyclictest0-21swapper/012:35:170
113814899239,5cyclictest0-21swapper/010:40:020
113814899232,9cyclictest1375345-21apt-get10:00:110
1138148992317,2cyclictest1629-21avahi-daemon11:15:020
1138148992311,7cyclictest0-21swapper/010:15:010
113814899229,5cyclictest0-21swapper/011:00:010
113814899229,5cyclictest0-21swapper/009:15:020
11433322210,2sleep20-21swapper/207:10:212
1138150992017,1cyclictest0-21swapper/208:05:002
113814999204,4cyclictest491rcuog/211:25:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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