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2026-08-24 - 19:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Aug 24, 2026 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200562322300,2sleep30-21swapper/312:29:573
17114242980,2sleep11711430-21kthreadcore09:45:021
18873812720,1sleep00-21swapper/011:22:350
18971142370,1sleep01897116-21ssh11:29:120
20184082310,2sleep12018413-21sd-close12:35:041
1481766992217,1cyclictest82050irq/121-eno109:20:001
1481759992212,5cyclictest0-21swapper/011:39:400
148176699217,5cyclictest0-21swapper/111:29:381
1481759992114,2cyclictest1521689-21/usr/sbin/munin07:40:020
1481759992110,6cyclictest0-21swapper/009:10:020
1481766992017,2cyclictest1818463-21kthreadcore10:45:011
1481766992017,2cyclictest1818463-21kthreadcore10:45:011
148175999203,9cyclictest1816844-21cpuspeed_turbos10:44:550
148175999203,9cyclictest1816844-21cpuspeed_turbos10:44:550
18639052190,2sleep20-21swapper/211:10:022
1481772991911,2cyclictest0-21swapper/207:25:022
1481766991916,2cyclictest1674663-21ssh09:25:031
1481759991910,5cyclictest1930642-21timerandwakeup11:45:060
1481759991910,5cyclictest1773014-21irqrtprio10:19:590
2213291180,1phc2sys0-21swapper/310:23:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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