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2026-09-01 - 01:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Aug 31, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
397646321570,1sleep13976462-21sshd-auth07:22:371
758272990,2sleep20-21swapper/210:30:012
1934202970,1sleep070-21kcompactd011:39:190
40923542360,1sleep04092357-21cut08:44:530
2786732290,4sleep0491rcuog/212:24:530
662172280,2sleep20-21swapper/210:24:522
39822302260,2sleep20-21swapper/207:24:552
3959742992314,5cyclictest201732-21runrttasks11:43:020
3959742992215,6cyclictest5641-21runrttasks09:51:360
3959742992214,4cyclictest144973-21kthreadcore11:09:490
395974299209,6cyclictest0-21swapper/009:39:510
395974299208,7cyclictest0-21swapper/011:34:510
3959742992013,6cyclictest286123-21kthreadcore12:29:510
3959742992013,5cyclictest1011-21gdbus10:10:020
2447398200,4rtkit-daemon798-21mta-sts-daemon10:36:120
3959744991916,1cyclictest0-21swapper/210:50:012
3959744991916,1cyclictest0-21swapper/209:51:432
3959744991916,1cyclictest0-21swapper/209:44:292
3959743991916,2cyclictest24615-21JS14:54:061
3959743991916,2cyclictest24615-21JS14:54:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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