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2026-06-12 - 10:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jun 12, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20371092990,3sleep02037107-21sed23:30:330
19659722670,1sleep11965971-21ssh22:45:251
20318932310,2sleep30-21swapper/323:30:203
1675852992517,7cyclictest2113102-21acpi00:25:180
1675852992413,6cyclictest0-21swapper/021:50:030
1675852992315,7cyclictest1748128-21kthreadcore20:05:280
1675852992314,5cyclictest2020657-21kthreadcore23:20:300
1675852992314,5cyclictest2020657-21kthreadcore23:20:300
1675853992219,2cyclictest1-21systemd19:20:011
1675853992216,2cyclictest1675850-21cyclictest23:55:021
1675853992213,4cyclictest2127241-21runrttasks00:34:251
1675852992219,2cyclictest2105032-21idleruntime-cro00:20:010
492398210,5rtkit-daemon1237-21mta-sts-daemon22:40:111
1675852992118,2cyclictest2127471-21latency_hist00:35:010
1675852992118,2cyclictest2009201-21cron23:15:010
1675852992118,2cyclictest1957390-21/usr/sbin/munin22:40:010
1675852992110,6cyclictest0-21swapper/021:10:280
3153791200,2phc2sys0-21swapper/322:38:193
1675853992013,2cyclictest0-21swapper/121:35:031
167585299209,6cyclictest0-21swapper/021:30:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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