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2026-07-28 - 10:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jul 28, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20617432840,1sleep02061741-21ssh23:21:050
20395732720,1sleep12039572-21ssh23:06:551
1714073992723,2cyclictest2040616-21cron23:10:010
1714073992421,2cyclictest1936628-21wc22:00:010
1714073992411,7cyclictest0-21swapper/023:30:450
171407499236,4cyclictest191rcu_preempt00:10:011
1157598230,7rtkit-daemon1307-21mta-sts-daemon00:29:590
1714075992219,1cyclictest0-21swapper/223:00:012
1714074992219,2cyclictest664-21dbus-daemon19:30:021
1714074992215,3cyclictest2004025-21/usr/sbin/munin22:45:581
1714075992118,1cyclictest0-21swapper/200:15:012
1714074992110,4cyclictest1862836-21unin-run21:10:021
1714073992118,2cyclictest1-21systemd22:40:010
1714073992111,6cyclictest0-21swapper/022:05:510
1714073992110,5cyclictest1307-21mta-sts-daemon21:10:180
1157598210,4rtkit-daemon1306-21mta-sts-daemon20:05:200
21236462200,2sleep30-21swapper/300:05:493
1714074992017,2cyclictest664-21dbus-daemon23:45:001
1714074992017,2cyclictest1885084-21wc21:25:021
1714074992015,4cyclictest2159480-21unin-run00:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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