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2026-07-02 - 21:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 02, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250082621070,3sleep30-21swapper/310:49:573
238359321040,1sleep20-21swapper/209:30:012
247310321010,3sleep30-21swapper/310:31:383
22195712960,2sleep20-21swapper/207:19:572
2206484993129,1cyclictest0-21swapper/207:40:022
2206483993128,2cyclictest2583746-21grep11:45:021
24356642300,2sleep20-21swapper/210:05:042
2206482992921,7cyclictest2450089-21latency_hist10:15:020
2206482992623,2cyclictest2598167-21grep11:55:020
2206483992522,2cyclictest660-21dbus-daemon10:10:011
220648299250,5cyclictest2398168-21latency_hist09:40:020
2206484992421,1cyclictest0-21swapper/211:55:012
2206483992421,2cyclictest0-21swapper/108:40:011
2206483992421,2cyclictest0-21swapper/108:40:011
2206482992421,2cyclictest2206480-21cyclictest07:15:010
2206484992320,1cyclictest0-21swapper/209:25:012
2206482992320,2cyclictest1-21systemd08:30:010
25735252220,2sleep20-21swapper/211:39:542
2206483992219,2cyclictest2413281-21sh09:50:011
2206483992219,2cyclictest0-21swapper/112:20:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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