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2026-09-11 - 10:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Sep 11, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168509621770,3sleep30-21swapper/323:59:303
153989721010,2sleep11537989-21kthreadcore22:34:371
153989721010,2sleep11537989-21kthreadcore22:34:371
16751572310,2sleep20-21swapper/223:52:512
12989532290,2sleep0241rcuc/020:04:360
2447398260,4rtkit-daemon1223334-21cyclictest00:34:470
1223336992611,11cyclictest1618519-21kthreadcore23:19:350
1223336992411,12cyclictest1223334-21cyclictest21:13:430
1223336992411,12cyclictest1223334-21cyclictest21:13:430
122333699238,5cyclictest1684869-21aten_repower_po23:59:230
122333699235,5cyclictest0-21swapper/000:15:350
1223336992314,3cyclictest24813-21gsd-housekeepin19:31:310
1223336992313,9cyclictest1479315-21tail21:59:420
1223336992311,3cyclictest1223334-21cyclictest20:29:340
122333699230,15cyclictest1253430-21basename19:30:010
122333699229,7cyclictest0-21swapper/023:09:120
1223336992212,6cyclictest1642067-21kthreadcore23:34:350
1223336992211,2cyclictest1550206-21cron22:40:010
1223336992211,10cyclictest1360065-21kthreadcore20:49:360
1223336992210,2cyclictest1347744-21kthreadcore20:39:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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