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2026-06-25 - 11:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jun 25, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127271521030,2sleep30-21swapper/300:35:083
125641421010,3sleep30-21swapper/300:25:063
11753582990,2sleep30-21swapper/323:30:073
11948072750,1sleep01194805-21ssh23:44:110
8486962330,2sleep30-21swapper/319:35:063
10368832300,2sleep20-21swapper/221:55:152
820366992517,7cyclictest1160336-21kthreadcore23:20:050
820369992421,1cyclictest0-21swapper/222:25:012
820369992414,1cyclictest0-21swapper/220:30:012
820369992320,1cyclictest0-21swapper/222:35:012
820368992320,2cyclictest0-21swapper/119:10:021
820366992313,6cyclictest0-21swapper/000:30:020
820366992312,6cyclictest0-21swapper/019:35:020
820368992219,2cyclictest1076959-21cstates22:25:031
820366992219,2cyclictest1136375-21sh23:05:010
820366992215,6cyclictest973045-21kthreadcore21:15:100
820366992215,6cyclictest973045-21kthreadcore21:15:100
820366992214,7cyclictest0-21swapper/023:30:010
820366992211,6cyclictest0-21swapper/022:55:020
820366992211,6cyclictest0-21swapper/021:35:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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