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2025-11-10 - 05:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Nov 10, 2025 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290905121020,1sleep10-21swapper/121:48:551
290905121020,1sleep10-21swapper/121:48:551
27772072310,2sleep10-21swapper/120:15:501
31495852270,1sleep0491rcuog/200:05:530
2692039992519,2cyclictest170550irq/121-eno100:25:011
2692037992317,5cyclictest1635-21dbus-daemon23:50:010
2692037992314,5cyclictest2932636-21grep22:00:520
2692037992313,6cyclictest1652-1atopacctd00:20:540
2692042992219,1cyclictest0-21swapper/200:00:002
2692039992219,2cyclictest2979062-21awk22:30:001
2692039992114,3cyclictest3192291-21kthreadcore00:30:551
2692037992117,2cyclictest1-21systemd23:45:020
2692037992115,5cyclictest2987720-21latency_hist22:35:010
2692037992115,5cyclictest2987720-21latency_hist22:35:010
2692037992113,4cyclictest3056948-21runrttasks23:14:440
2692037992111,5cyclictest0-21swapper/022:25:010
835298200,15rtkit-daemon170550irq/121-eno123:35:180
302487291200,3phc2sys0-21swapper/323:19:093
28631452200,2sleep20-21swapper/221:20:512
269203999209,2cyclictest1-21systemd22:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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