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2026-05-08 - 08:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri May 08, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156057621010,1sleep00-21swapper/023:51:470
15204332980,1sleep10-21swapper/123:25:261
15659192830,1sleep01565881-21ssh23:55:270
13413852440,1sleep11341386-21/usr/sbin/munin21:30:221
16010822340,2sleep10-21swapper/100:20:261
1155975992824,1cyclictest0-21swapper/221:00:012
1155973992724,2cyclictest0-21swapper/121:50:011
1155972992615,6cyclictest0-21swapper/021:10:010
1155973992421,2cyclictest1-21systemd00:20:001
1155973992320,2cyclictest1386281-21sh22:00:011
1155973992320,2cyclictest1-21systemd23:05:001
1155972992313,6cyclictest1482551-21kthreadcore23:00:260
1155975992218,2cyclictest0-21swapper/223:25:002
1155972992220,1cyclictest0-21swapper/021:40:000
1155972992216,5cyclictest1501222-21latency_hist23:15:020
383433398210,5rtkit-daemon3851704-21mta-sts-daemon22:24:150
1155975992118,1cyclictest0-21swapper/223:40:002
1155975992118,1cyclictest0-21swapper/222:35:002
1155973992113,4cyclictest1584820-21/usr/sbin/munin00:10:261
1155972992118,2cyclictest1221798-21cron20:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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