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2026-04-27 - 18:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Apr 27, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
221279921680,4sleep0191rcu_preempt07:40:460
221279921680,4sleep0191rcu_preempt07:40:450
225461221610,3sleep12254616-21kthreadcore08:15:411
217731821070,2sleep30-21swapper/307:15:393
24158362990,1sleep00-21swapper/010:10:430
22879052970,1sleep00-21swapper/008:40:440
22670652350,3sleep02267068-21kthreadcore08:25:420
2166912992817,6cyclictest2599357-21acpi12:15:310
2166912992810,13cyclictest0-21swapper/010:48:060
2166912992724,2cyclictest2188172-21http07:25:010
2166912992615,7cyclictest0-21swapper/010:20:020
216691299250,8cyclictest2440644-21ssh10:30:010
2166913992421,2cyclictest2166909-21cyclictest07:10:011
216691299249,7cyclictest0-21swapper/009:30:020
2166912992411,5cyclictest2617031-21kthreadcore12:25:380
216691299239,5cyclictest0-21swapper/011:45:330
2166912992314,5cyclictest2307796-21/usr/sbin/munin09:00:360
2166912992313,6cyclictest2564664-21grep11:50:400
2166912992312,6cyclictest2454113-21cat10:35:460
2166912992312,5cyclictest2478466-21latency_hist10:55:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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