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2026-07-27 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jul 27, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30571421060,1sleep30-21swapper/300:35:493
408612021000,1sleep00-21swapper/019:40:010
408612021000,1sleep00-21swapper/019:40:010
1699672350,4sleep00-21swapper/023:00:590
4047118992922,3cyclictest0-21swapper/200:00:002
4047116992719,3cyclictest191rcu_preempt22:50:020
4047117992620,2cyclictest69250irq/121-eno123:00:031
4047116992619,3cyclictest191rcu_preempt23:55:020
4047116992619,3cyclictest191rcu_preempt21:40:010
4047116992522,2cyclictest1-21systemd21:10:020
4047116992512,8cyclictest672-21polkitd22:10:020
4047117992421,2cyclictest664-21dbus-daemon19:15:031
4047117992421,2cyclictest664-21dbus-daemon19:15:031
4047117992421,2cyclictest0-21swapper/120:40:011
4047117992418,2cyclictest69250irq/121-eno100:25:021
4047116992421,2cyclictest23836-21grep21:25:010
4047116992414,6cyclictest204409-21kthreadcore23:25:550
4047116992412,7cyclictest0-21swapper/021:55:530
4047116992411,8cyclictest4102806-21kthreadcore19:50:550
4047118992315,3cyclictest0-21swapper/220:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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