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2026-07-31 - 11:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jul 31, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318678221060,2sleep03186784-21head20:15:360
34007682750,1sleep03400766-21ssh22:47:100
33425072380,1sleep00-21swapper/022:10:020
31431792340,2sleep30-21swapper/319:40:003
31203382320,2sleep30-21swapper/319:20:573
32988192260,2sleep20-21swapper/221:40:542
3104139992413,6cyclictest0-21swapper/022:40:000
3104139992315,5cyclictest1309-21mta-sts-daemon23:37:270
3104139992214,4cyclictest3451046-21kthreadcore23:20:590
3104139992214,4cyclictest3316180-21kthreadcore21:51:010
3104141992119,1cyclictest0-21swapper/200:35:362
3104141992118,1cyclictest0-21swapper/219:45:012
3104140992118,2cyclictest664-21dbus-daemon00:40:021
3104140992114,3cyclictest3433097-21irqcore23:10:571
3104140992110,4cyclictest3256568-21kthreadcore21:11:001
3104139992118,2cyclictest3303520-21xargs21:41:050
3104139992110,6cyclictest0-21swapper/021:56:050
3104141992017,1cyclictest0-21swapper/220:40:012
3104139992017,2cyclictest3110592-21wc19:15:020
3104139992016,3cyclictest3280416-21kthreadcore21:26:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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