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2026-07-11 - 12:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jul 11, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136082621070,2sleep30-21swapper/320:15:013
16812732690,1sleep11681272-21ssh00:02:351
15838442460,2sleep11583829-21ssh22:55:021
15182162290,2sleep20-21swapper/222:13:472
1279448992717,6cyclictest0-21swapper/022:30:010
3153791251,11phc2sys0-21swapper/320:10:013
14187672230,2sleep30-21swapper/321:04:423
1279449992219,2cyclictest0-21swapper/100:34:391
1279448992213,5cyclictest1580980-21kthreadcore22:54:430
1279448992211,6cyclictest0-21swapper/023:14:450
1279450992118,1cyclictest0-21swapper/200:10:012
127944899211,18cyclictest0-21swapper/021:54:400
1279448992111,5cyclictest0-21swapper/023:50:010
1279448992110,6cyclictest0-21swapper/022:45:010
1279448992110,6cyclictest0-21swapper/022:35:480
1279450992017,1cyclictest0-21swapper/220:15:012
1279450992016,2cyclictest0-21swapper/221:25:012
1279449992017,2cyclictest1-21systemd20:50:011
1279449992017,2cyclictest0-21swapper/122:20:021
1279449992014,5cyclictest1724488-21latency_hist00:30:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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