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2026-02-25 - 18:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Feb 25, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56102721580,1sleep0561024-21python312:32:080
36377521150,1sleep10-21swapper/110:42:031
54829721010,2sleep30-21swapper/312:27:023
4536782740,2sleep20-21swapper/211:32:062
4754062390,2sleep150995-21cyclictest11:46:201
4660212270,1sleep10-21swapper/111:40:271
50997992622,2cyclictest0-21swapper/010:05:010
50997992118,2cyclictest56968-21latency_hist07:15:020
50997992116,4cyclictest198923-21kworker/u16:3-events_power_efficient09:20:000
50997992112,5cyclictest338953-21sendmail_mailst10:27:100
50999992017,1cyclictest0-21swapper/212:20:002
50998992017,2cyclictest1288-1atopacctd12:05:011
50997992010,5cyclictest0-21swapper/012:15:010
5099999191,7cyclictest0-21swapper/212:30:012
50999991916,1cyclictest0-21swapper/211:52:002
50999991916,1cyclictest0-21swapper/210:39:102
50999991916,1cyclictest0-21swapper/207:20:002
50999991915,2cyclictest0-21swapper/209:55:012
5099899194,6cyclictest0-21swapper/111:26:561
50998991916,2cyclictest350072-21cron10:35:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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