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2026-01-13 - 17:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jan 13, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190048321910,3sleep30-21swapper/310:55:023
208280921600,2sleep30-21swapper/312:37:583
18941252770,2sleep01716647-21diskmemload10:52:580
17603692750,2sleep30-21swapper/309:38:023
1573895993222,3cyclictest1290-21dbus-daemon12:00:021
16421282300,2sleep20-21swapper/208:03:082
16658732290,2sleep30-21swapper/308:28:093
1573895992926,2cyclictest1710574-21basename09:05:011
19593502250,2sleep30-21swapper/311:28:043
1573895992515,2cyclictest134050irq/121-eno109:50:021
1573894992321,1cyclictest2017481-21latency_hist12:00:010
1573896992118,1cyclictest0-21swapper/210:50:002
157389499217,10cyclictest1884725-21cpuspeed_turbos10:47:570
1573894992118,2cyclictest1738228-21systemd-run09:25:000
1573894992118,2cyclictest0-21swapper/008:40:010
1573894992115,2cyclictest134050irq/121-eno108:32:570
1573894992112,4cyclictest1826080-21tr10:13:040
1573895992017,2cyclictest1-21systemd11:50:021
157389499207,7cyclictest2018-21lldpd10:22:200
1573894992017,2cyclictest2080591-21latency_hist12:35:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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