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2026-08-22 - 22:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 22, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159477921190,2sleep11403301-21cyclictest09:25:061
16451702960,2sleep30-21swapper/309:53:303
15939632690,0sleep01593969-21cut09:25:050
17503122350,2sleep20-21swapper/210:50:092
16599862330,1sleep20-21swapper/210:00:072
1403303992919,6cyclictest1584607-21909:20:030
17951472270,1sleep00-21swapper/011:15:130
1403304992414,6cyclictest1932476-21irqcore12:35:021
1403303992411,8cyclictest1905474-21munin-run12:20:020
1403304992317,2cyclictest82050irq/121-eno109:15:111
1403303992313,5cyclictest1856829-21kthreadcore11:50:060
1403303992312,6cyclictest376-21systemd-journal09:55:020
1403303992310,4cyclictest1801012-21kthreadcore11:20:060
140330399228,6cyclictest0-21swapper/010:35:100
140330399220,11cyclictest1611103-21munin-run09:35:010
140330499218,3cyclictest0-21swapper/111:50:011
140330499218,3cyclictest0-21swapper/111:50:011
1403304992111,6cyclictest1905344-21gltestperf12:20:011
140330399219,4cyclictest1624874-21kthreadcore09:40:090
140330399218,5cyclictest1895167-21runrttasks12:13:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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