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2026-06-05 - 19:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jun 05, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139626522200,3sleep30-21swapper/310:45:003
143328521540,1sleep30-21swapper/311:09:463
118589821140,2sleep01099339-21cyclictest08:19:430
143520221040,2sleep30-21swapper/311:12:423
12681302580,2sleep10-21swapper/109:21:081
11545992280,2sleep00-21swapper/007:54:430
1099342992622,3cyclictest1569590-21ssh12:40:021
1099342992522,2cyclictest1426699-21ssh11:05:011
1099341992414,6cyclictest1433453-21proc_pri11:09:470
1099343992320,1cyclictest0-21swapper/207:20:002
1099341992320,2cyclictest1127169-21systemd07:30:000
1099343992220,1cyclictest0-21swapper/211:40:022
1099343992219,1cyclictest0-21swapper/212:25:012
1099342992218,3cyclictest1252742-21grep09:10:011
109934199223,1cyclictest0-21swapper/010:24:420
1099341992211,6cyclictest0-21swapper/011:54:430
1099341992211,6cyclictest0-21swapper/011:00:000
1099341992211,6cyclictest0-21swapper/010:20:020
1099343992119,1cyclictest0-21swapper/212:10:012
1099343992118,1cyclictest0-21swapper/210:55:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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