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2026-06-27 - 00:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Jun 26, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39785052430,2sleep30-21swapper/311:40:023
3611905993330,2cyclictest765-1atopacctd12:00:011
3611906992724,1cyclictest0-21swapper/211:55:002
3611905992614,8cyclictest3880697-21/usr/sbin/munin10:35:101
3611906992522,1cyclictest0-21swapper/210:25:002
3611905992522,2cyclictest3777288-21ssh09:25:011
3611905992518,2cyclictest191rcu_preempt10:00:021
3611905992517,2cyclictest67250irq/126-eno110:10:011
3611905992419,4cyclictest3970826-21gltestperf11:35:021
3611904992421,2cyclictest3895974-21cstates10:45:010
3611905992320,2cyclictest3770050-21sed09:20:001
3611905992311,3cyclictest191rcu_preempt08:34:581
3153791231,2phc2sys0-21swapper/310:19:573
3611905992216,2cyclictest191rcu_preempt09:00:011
3611905992216,2cyclictest191rcu_preempt09:00:011
3611905992210,3cyclictest3953080-21timerwakeupswit11:20:111
3611905992210,3cyclictest191rcu_preempt09:44:581
361190499228,6cyclictest0-21swapper/010:40:030
3611904992219,2cyclictest3700244-21basename08:25:010
3611904992214,7cyclictest0-21swapper/009:40:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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