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2026-06-22 - 15:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 22, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36813221020,1sleep00-21swapper/007:45:050
5681662740,2sleep30-21swapper/310:15:003
322487993319,9cyclictest546088-21acpi10:00:030
32248799323,7cyclictest491rcuog/208:05:050
322487993113,15cyclictest561119-21apt10:10:040
322487993012,17cyclictest1247-21mta-sts-daemon11:24:500
322487992917,10cyclictest0-21swapper/011:25:020
32248799285,14cyclictest1020-21runrttasks09:36:080
322487992814,12cyclictest1242-21mta-sts-daemon11:15:090
322487992711,15cyclictest629806-21kthreadcore10:55:110
322487992711,14cyclictest1-21systemd07:35:020
32248799270,3cyclictest687200-21latency_hist11:35:000
322487992619,5cyclictest343454-21gmain07:25:010
32248799259,12cyclictest765-1atopacctd09:20:060
32248799257,12cyclictest0-21swapper/011:40:020
32248799256,4cyclictest0-21swapper/010:01:070
32248799253,16cyclictest0-21swapper/009:25:180
32248799253,16cyclictest0-21swapper/009:25:180
32248799252,11cyclictest520646-21kthreadcore09:40:120
322487992519,5cyclictest613160-21sh10:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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