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2026-05-09 - 09:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat May 09, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3085862992616,6cyclictest3378342-21kthreadcore22:40:210
308586399240,9cyclictest3361122-21munin-run22:30:011
3085863992320,2cyclictest1290-21dbus-daemon22:25:001
3085863992316,2cyclictest36-21ksoftirqd/100:00:001
3085863992315,3cyclictest36-21ksoftirqd/122:00:011
3085862992320,2cyclictest3952751-21ntpd21:35:150
3085862992320,2cyclictest1296-21polkitd20:45:010
3085862992314,5cyclictest3478371-21kthreadcore23:45:240
3085863992219,2cyclictest3163610-21grep20:10:011
3085863992212,5cyclictest3122565-21tr19:35:221
308586399220,9cyclictest3543869-21munin-run00:30:001
308586399220,15cyclictest0-21swapper/122:00:161
3085862992217,2cyclictest0-21swapper/021:20:010
383433398210,4rtkit-daemon3851705-21mta-sts-daemon19:40:070
35176422210,1sleep20-21swapper/200:10:232
33145192210,1sleep00-21swapper/021:58:460
3085864992119,1cyclictest0-21swapper/223:50:012
308586399215,10cyclictest3212407-21tr20:45:231
308586399213,12cyclictest1-21systemd21:35:021
3085863992118,2cyclictest3505670-21latency_hist00:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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