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2026-09-11 - 23:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Fri Sep 11, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27027822930,2sleep30-21swapper/311:24:343
24362372850,1sleep00-21swapper/008:49:330
26334022460,2sleep12633140-21ssh10:44:351
27942052390,1sleep10-21swapper/112:15:031
25197482270,2sleep00-21swapper/009:39:390
229926199239,4cyclictest2265110-21kworker/u16:1-events_unbound10:29:260
28038422220,2sleep10-21swapper/112:21:561
2299261992211,7cyclictest2782397-21kthreadcore12:09:390
229926199217,8cyclictest0-21swapper/009:29:140
2299261992112,5cyclictest2697156-21latency_hist11:20:020
2299261992012,7cyclictest2570522-21kthreadcore10:09:390
23312842190,1sleep00-21swapper/007:34:340
229926599193,7cyclictest0-21swapper/209:24:112
229926599192,13cyclictest0-21swapper/209:54:112
2299265991912,3cyclictest0-21swapper/210:16:172
2299263991916,2cyclictest24617-21JS14:54:061
2299263991916,2cyclictest24610-21gmain12:17:251
2299263991911,2cyclictest61901-21gmain07:14:341
2299261991912,6cyclictest24615-21JS14:54:060
2213291191,3phc2sys0-21swapper/310:41:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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