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2026-09-08 - 09:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Sep 08, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
362761321880,2sleep30-21swapper/323:20:033
35209202730,2sleep30-21swapper/322:20:023
36096532370,2sleep30-21swapper/323:10:013
34590212360,2sleep30-21swapper/321:45:023
37446622340,2sleep00-21swapper/000:27:590
36581882320,2sleep30-21swapper/323:39:393
34679322310,1sleep20-21swapper/221:50:022
322871799300,8cyclictest3396922-21munin-run21:10:020
3228717992816,10cyclictest191rcu_preempt23:10:010
322871799274,18cyclictest0-21swapper/022:14:160
322871799270,20cyclictest3396756-21diskmemload22:39:170
322871799267,9cyclictest191rcu_preempt22:44:180
3228717992514,7cyclictest191rcu_preempt21:59:360
322871799251,12cyclictest0-21swapper/023:44:170
3228717992510,5cyclictest16-21ksoftirqd/000:39:420
322871799250,14cyclictest3314719-21cut20:14:250
322871799250,14cyclictest0-21swapper/019:59:170
322871799249,10cyclictest3688567-21latency23:54:410
322871799242,11cyclictest16-21ksoftirqd/000:15:000
3228717992411,7cyclictest3585776-21cstates22:59:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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