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2026-07-16 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 16, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124695521060,1sleep00-21swapper/008:46:190
12302262930,2sleep30-21swapper/308:31:193
14840682700,1sleep01484066-21ssh11:30:190
11656962310,2sleep20-21swapper/207:41:172
1125752992512,6cyclictest0-21swapper/012:30:010
1125752992421,2cyclictest664-21dbus-daemon09:10:020
1125753992320,2cyclictest1535827-21dump-pmu-power12:05:011
1125753992320,2cyclictest1439357-21grep11:00:011
1125752992320,2cyclictest1521170-21grep11:55:030
14924772220,2sleep20-21swapper/211:36:152
1125753992118,2cyclictest1365102-21latency_hist10:10:031
1125752992118,2cyclictest1238616-21systemd-run08:40:020
1125752992117,2cyclictest0-21swapper/011:00:020
1125752992112,5cyclictest1472375-21kthreadcore11:21:200
112575299209,6cyclictest0-21swapper/009:26:120
112575299208,6cyclictest0-21swapper/010:16:110
1125752992017,2cyclictest664-21dbus-daemon09:20:020
1125752992017,2cyclictest1170874-21grep07:45:020
1125752992010,6cyclictest0-21swapper/011:16:110
1125752992010,5cyclictest0-21swapper/011:40:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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