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2026-08-10 - 04:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Aug 10, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44208821030,2sleep30-21swapper/322:10:363
6352212810,1sleep0635219-21ssh00:21:480
4361992700,1sleep0436197-21ssh22:08:210
2367142340,3sleep1236719-21kthreadcore19:35:371
199398992312,6cyclictest0-21swapper/000:10:020
199400992219,1cyclictest0-21swapper/220:20:012
199400992219,1cyclictest0-21swapper/219:15:012
199400992212,1cyclictest0-21swapper/220:35:382
199399992219,2cyclictest466529-21cron22:30:011
199398992219,2cyclictest205440-21systemd19:15:010
199398992211,6cyclictest0-21swapper/022:50:330
5129992210,2sleep1512811-21ssh23:00:321
3240591211,1phc2sys0-21swapper/300:14:553
199399992118,2cyclictest636340-21systemd-run00:25:011
19939899219,6cyclictest0-21swapper/022:45:110
19939899219,6cyclictest0-21swapper/022:45:110
1157598210,3rtkit-daemon11574-21rtkit-daemon20:52:590
4298652200,3sleep30-21swapper/322:05:113
199400992018,1cyclictest0-21swapper/221:40:022
199400992017,1cyclictest0-21swapper/221:30:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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