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2026-07-06 - 23:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jul 06, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157522721630,2sleep30-21swapper/311:09:493
148323821130,1sleep10-21swapper/110:08:551
146679821000,2sleep30-21swapper/309:55:023
15436922840,2sleep30-21swapper/310:49:453
1251253993721,11cyclictest1429064-21unin-run09:30:000
1251254992926,2cyclictest1578581-21latency_hist11:10:021
1251253992917,5cyclictest1614293-21kthreadcore11:34:480
1251253992720,2cyclictest0-21swapper/011:50:030
1251254992516,3cyclictest1645087-21ssh11:54:561
125125499244,6cyclictest1278037-21cron07:30:011
1251254992320,2cyclictest660-21dbus-daemon11:40:011
1251253992312,6cyclictest0-21swapper/012:19:420
1251255992220,1cyclictest0-21swapper/210:15:022
1251254992219,2cyclictest765-1atopacctd09:45:011
1251254992218,2cyclictest1399680-21systemd09:10:031
1251253992215,2cyclictest0-21swapper/011:40:020
125125399221,16cyclictest1303605-21diskstats07:54:460
492398210,3rtkit-daemon1247-21mta-sts-daemon12:37:160
1251255992118,1cyclictest0-21swapper/210:44:482
125125399217,8cyclictest0-21swapper/009:49:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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