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2026-04-09 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Apr 09, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13762392880,2sleep30-21swapper/309:46:043
13561772820,1sleep01356175-21ssh09:31:300
14018752720,1sleep11401874-21ssh10:03:581
1166739992825,1cyclictest0-21swapper/211:55:032
1166737992522,2cyclictest1342011-21grep09:25:010
15721252230,2sleep1341rcuc/111:56:051
14768652230,1sleep00-21swapper/010:54:030
1166739992321,1cyclictest0-21swapper/210:50:022
1166739992320,1cyclictest0-21swapper/210:00:002
1166737992311,7cyclictest0-21swapper/012:20:570
383433398220,3rtkit-daemon3851702-21mta-sts-daemon08:31:070
12884822220,0sleep070-21kcompactd008:45:060
1166739992220,1cyclictest0-21swapper/207:15:012
1166738992219,2cyclictest1530091-21pool-packagekit11:30:011
1166738992214,4cyclictest1363306-21timerandwakeup09:36:181
1166739992119,1cyclictest0-21swapper/212:30:022
1166738992115,2cyclictest134050irq/121-eno110:25:011
1166738992113,3cyclictest1561891-21irqrtprio11:51:031
1166737992118,2cyclictest1348492-21tail09:26:110
1166737992118,2cyclictest1296-21polkitd08:05:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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