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2026-01-07 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jan 07, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
132426221020,1sleep00-21swapper/023:31:500
137453321010,2sleep30-21swapper/323:58:143
9856782350,1sleep00-21swapper/019:58:170
11612522310,2sleep20-21swapper/221:59:022
922779992920,4cyclictest0-21swapper/121:48:051
922776992522,2cyclictest1340616-21idleruntime-cro23:40:000
10608412230,2sleep30-21swapper/321:03:123
922779992220,1cyclictest0-21swapper/122:40:001
922779992219,2cyclictest1322985-21systemd-run23:30:011
922776992210,4cyclictest1308951-21kthreadcore23:23:110
2902298220,5rtkit-daemon1170433-21ssh22:04:300
922779992118,2cyclictest1429807-21latency_hist00:30:001
922776992118,2cyclictest1047078-21/usr/sbin/munin20:50:000
922776992112,5cyclictest1406784-21kthreadcore00:18:120
2902298210,6rtkit-daemon929174-21munin-node23:16:310
2902298210,5rtkit-daemon0-21swapper/000:07:480
2902298210,3rtkit-daemon1091438-21gmain21:50:300
922790992018,1cyclictest0-21swapper/223:45:002
922790992018,1cyclictest0-21swapper/221:20:022
922790992017,1cyclictest0-21swapper/222:38:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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