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2025-12-29 - 06:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Dec 29, 2025 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
364929821000,2sleep30-21swapper/320:33:233
35602942340,2sleep20-21swapper/219:20:002
3545908992522,2cyclictest70-21kcompactd022:30:011
36216132240,1sleep10-21swapper/120:13:171
3545907992415,5cyclictest3814731-21if_err_enp1s022:18:220
3545908992320,2cyclictest3820607-21grep22:20:021
3545908992118,2cyclictest3865306-21ssh22:45:001
3545908992118,2cyclictest1290-21dbus-daemon00:30:021
354590799212,5cyclictest4001050-40updatedb.mlocat00:00:010
3545907992118,2cyclictest3802295-21grep22:10:000
3545907992114,6cyclictest0-21swapper/022:53:220
354590799211,16cyclictest0-21swapper/000:01:180
2649091210,2phc2sys0-21swapper/322:58:483
3545908992018,1cyclictest3633104-21awk20:20:011
3545908992017,2cyclictest3729968-21/usr/sbin/munin21:30:011
3545908992017,2cyclictest3669629-21latency_hist20:50:001
3545908992017,2cyclictest3552209-21ls19:15:011
3545908992012,3cyclictest3760919-21irqrtprio21:48:251
354590799207,8cyclictest3861597-21kthreadcore22:43:230
3545907992017,2cyclictest1290-21dbus-daemon00:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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