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2026-07-09 - 18:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jul 09, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299575021550,2sleep30-21swapper/311:30:023
30542362710,1sleep13054234-21ssh12:09:481
28182542690,1sleep02818252-21ssh09:30:030
2639104993316,12cyclictest2938421-21tr10:54:391
2639104992813,11cyclictest2865091-21irqcore10:04:421
2639105992623,1cyclictest0-21swapper/210:33:502
263910499264,13cyclictest2840824-1ssh09:46:081
263910499240,14cyclictest2960107-21sh11:09:141
3153791230,10phc2sys0-21swapper/308:54:363
263910499233,15cyclictest2833238-21taskset09:40:351
263910499231,14cyclictest2944887-21taskset10:57:551
263910499231,13cyclictest2989679-21runrttasks11:29:251
263910499231,13cyclictest2974725-21sh11:18:471
263910499231,13cyclictest2878519-21runrttasks10:13:181
263910499231,13cyclictest2696553-21taskset07:55:531
263910499231,12cyclictest1020-21runrttasks09:10:561
2639104992310,7cyclictest2813731-21kthreadcore09:29:441
263910499230,13cyclictest2826079-21taskset09:36:231
263910499230,12cyclictest2660366-21taskset07:28:401
2639105992219,1cyclictest0-21swapper/211:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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