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2025-09-17 - 00:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Sep 16, 2025 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201041021490,2sleep30-21swapper/307:24:253
24994652970,2sleep30-21swapper/312:34:283
1995382992314,5cyclictest2422646-21kthreadcore11:49:330
1995384992219,1cyclictest0-21swapper/210:25:012
1995383992213,4cyclictest2168706-21needreboot09:24:361
1995382992219,2cyclictest2124959-21cat08:55:000
1995382992212,6cyclictest2275032-21systemd10:25:010
1995384992118,1cyclictest0-21swapper/210:35:022
1995383992118,2cyclictest2196238-21systemd09:40:011
1995383992113,2cyclictest176650irq/121-eno111:50:001
1995382992113,4cyclictest2402793-21if_enp1s0.811:39:310
22134472200,2sleep30-21swapper/309:49:483
1995383992017,2cyclictest2407732-21grep11:40:001
1995383992017,2cyclictest0-21swapper/110:50:011
1995383992012,4cyclictest2386084-21kthreadcore11:29:401
1995382992017,2cyclictest2058495-21tr08:00:000
1995382992011,5cyclictest1666-21polkitd10:35:020
2555591190,2phc2sys0-21swapper/311:54:383
2555591190,2phc2sys0-21swapper/310:26:123
2555591190,2phc2sys0-21swapper/309:30:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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