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2026-09-24 - 20:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Sep 24, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127239721070,1sleep01272400-21cut12:19:140
120490021050,1sleep01204901-21sh11:41:060
9992572970,1sleep00-21swapper/009:44:160
77158099316,14cyclictest0-21swapper/010:42:090
77158099271,2cyclictest1283474-21awk12:25:000
771580992510,14cyclictest956482-21phc2sys-jitter09:19:190
2447398240,3rtkit-daemon1206-21snmpd10:06:261
2447398240,3rtkit-daemon1206-21snmpd10:06:261
771582992320,1cyclictest0-21swapper/211:05:012
77158299231,10cyclictest0-21swapper/211:48:532
77158099239,2cyclictest17850irq/132-ahci[0000:00:17.0]09:55:000
771580992313,9cyclictest942211-21cpuspeed_turbos09:14:090
771580992312,10cyclictest1026100-21kthreadcore09:59:170
77158099231,10cyclictest0-21swapper/010:29:230
771580992310,12cyclictest1085862-21kthreadcore10:34:150
77158199228,9cyclictest778-21dbus-daemon11:55:021
771581992215,6cyclictest24615-21JS14:54:061
77158099225,5cyclictest0-21swapper/011:04:220
77158099222,6cyclictest0-21swapper/007:34:160
77158099221,8cyclictest0-21swapper/011:24:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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