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2026-07-14 - 07:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Jul 14, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
105995721020,1sleep00-21swapper/000:23:280
98280921010,2sleep0982810-21cut23:31:260
7649192990,1sleep10-21swapper/121:06:181
10610022920,1sleep20-21swapper/200:25:342
621561992314,5cyclictest1040539-21kthreadcore00:11:250
621561992310,7cyclictest0-21swapper/019:51:200
621563992219,1cyclictest0-21swapper/223:20:012
621562992219,2cyclictest1053039-21sh00:20:011
621561992219,2cyclictest826486-21kthreadcore21:46:260
621561992214,7cyclictest0-21swapper/019:40:010
621561992213,5cyclictest1000124-21sshd23:42:200
621563992118,1cyclictest0-21swapper/219:25:012
621561992118,2cyclictest785368-21idleruntime-cro21:20:010
621561992118,2cyclictest1023369-21grep00:00:010
621561992110,6cyclictest0-21swapper/022:00:020
621563992018,1cyclictest0-21swapper/222:40:022
621563992017,1cyclictest0-21swapper/221:20:012
621561992018,1cyclictest837450-21ssh21:55:000
621563991917,1cyclictest0-21swapper/222:30:032
621563991917,1cyclictest0-21swapper/220:16:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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