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2026-01-15 - 19:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Jan 15, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159281521170,1sleep20-21swapper/209:03:012
146132921030,1sleep00-21swapper/007:17:560
18783442300,2sleep11878349-21turbostat.cron11:45:001
1451827992615,2cyclictest134050irq/121-eno109:18:021
1451826992421,2cyclictest1707688-21cron10:10:010
1451829992321,1cyclictest0-21swapper/212:35:012
1451826992310,7cyclictest0-21swapper/010:02:520
1451827992219,2cyclictest1887259-21idleruntime-cro11:50:001
1451826992219,2cyclictest1526907-21latency_hist08:10:000
1451826992217,1cyclictest16154422kthreadcore09:18:020
1451826992216,2cyclictest0-21swapper/010:51:030
1451826992116,4cyclictest1822556-21needreboot11:13:030
1451826992113,6cyclictest0-21swapper/009:50:010
1451826992017,2cyclictest1941043-21latency_hist12:20:010
1451826992017,2cyclictest1857910-21kthreadcore11:33:000
1451826992015,4cyclictest1949833-21cron12:25:000
1451826992015,4cyclictest1949833-21cron12:25:000
145182699200,7cyclictest1976734-21munin-run12:40:010
145182699200,7cyclictest1916740-21expr12:07:530
1451829991916,1cyclictest0-21swapper/210:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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