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2026-08-31 - 12:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Aug 31, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316199121120,2sleep30-21swapper/322:14:523
340486721090,1sleep03404868-21timerandwakeup00:29:590
320197321000,2sleep03201970-21ssh22:35:020
31602722500,3sleep00-21swapper/022:14:210
33202622310,1sleep00-21swapper/023:44:490
31574202290,1sleep03157422-21grep22:09:560
2883838992811,12cyclictest778-21dbus-daemon21:30:010
288383899274,13cyclictest0-21swapper/023:12:090
2883838992710,9cyclictest3355674-21cut00:04:500
2883838992510,11cyclictest3179926-21kthreadcore22:24:510
2883838992414,9cyclictest376-21systemd-journal19:35:010
288383899241,13cyclictest0-21swapper/023:32:440
288383899241,12cyclictest0-21swapper/022:25:350
288383899239,9cyclictest3125031-21sh21:54:280
288383899238,13cyclictest82050irq/121-eno122:45:520
288383899234,11cyclictest3363131-21rm00:08:480
288383899231,5cyclictest1188-21runrttasks19:14:340
288383899231,3cyclictest3038997-21runrttasks21:04:430
2883838992312,9cyclictest2956892-21cut20:04:490
288383899231,16cyclictest0-21swapper/023:35:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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