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2026-07-08 - 16:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 08, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78700921090,2sleep1752931-21cyclictest07:39:451
118205921020,2sleep11182060-21kthreadcore12:19:471
7582262840,1sleep10-21swapper/107:14:481
11474982760,1sleep01147496-21ssh11:57:260
8343762330,2sleep30-21swapper/308:15:013
75293399257,13cyclictest0-21swapper/011:24:400
11870502250,2sleep20-21swapper/212:24:452
752935992314,3cyclictest0-21swapper/207:24:402
75293399227,6cyclictest0-21swapper/010:50:010
752933992219,2cyclictest865375-21gpgconf08:40:010
752933992212,5cyclictest0-21swapper/012:20:010
75293399221,12cyclictest1-21systemd07:20:000
752935992118,1cyclictest0-21swapper/209:25:012
752934992114,3cyclictest911851-21gltestperf09:19:431
752934992114,3cyclictest1063496-21kthreadcore10:59:471
752934992114,2cyclictest492398rtkit-daemon11:20:381
752933992110,6cyclictest0-21swapper/010:17:410
492398210,4rtkit-daemon1237-21mta-sts-daemon08:28:581
752935992017,1cyclictest0-21swapper/211:46:412
752935992017,1cyclictest0-21swapper/210:45:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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