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2025-11-20 - 09:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Thu Nov 20, 2025 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172110721110,1sleep00-21swapper/021:10:370
1611437992724,2cyclictest1834024-21munin-run22:20:000
161144299236,9cyclictest1635-21dbus-daemon21:05:011
1611442992312,5cyclictest0-21swapper/123:05:271
1611437992314,4cyclictest1656183-21/usr/sbin/munin20:20:400
1611444992218,2cyclictest0-21swapper/219:40:002
1611437992219,2cyclictest1680488-21grep20:40:010
1611437992215,6cyclictest1803881-21cron22:00:000
161144499212,7cyclictest0-21swapper/223:30:012
161143799218,7cyclictest0-21swapper/022:05:270
1611437992110,6cyclictest0-21swapper/021:40:280
17152762200,1sleep01715279-21cut21:05:360
1611444992017,1cyclictest0-21swapper/200:25:012
161144299208,5cyclictest1635-21dbus-daemon23:40:011
1611442992017,2cyclictest1629-21avahi-daemon23:20:001
1611442992013,3cyclictest2005257-21kthreadcore00:20:341
1611442992012,3cyclictest0-21swapper/121:00:001
1611437992017,2cyclictest1996496-21cut00:15:010
1611437992017,2cyclictest1635-21dbus-daemon21:50:010
1611437992014,5cyclictest1629-21avahi-daemon23:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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