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2026-07-08 - 10:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Jul 08, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2303552990,1sleep00-21swapper/000:14:470
1444122690,1sleep1144411-21ssh23:16:051
2200062490,2sleep30-21swapper/300:09:413
4003372992826,1cyclictest0-21swapper/222:10:032
4003370992619,5cyclictest698-21in:imuxsock00:00:020
4003370992610,10cyclictest0-21swapper/021:39:400
4003370992513,8cyclictest152827-21runrttasks23:24:040
4003370992418,5cyclictest698-21in:imuxsock19:40:010
4003370992415,8cyclictest17948-21latency_hist21:50:010
400337099238,6cyclictest4008225-21cut19:14:510
400337099238,10cyclictest0-21swapper/000:24:120
4003370992317,5cyclictest0-21swapper/021:00:000
4003370992312,9cyclictest0-21swapper/000:40:020
4003370992310,9cyclictest142800-21kthreadcore23:14:500
400337199229,5cyclictest0-21swapper/121:44:401
4003371992219,2cyclictest99208-21apt-get22:45:011
4003371992214,3cyclictest0-21swapper/123:35:011
400337099228,9cyclictest0-21swapper/023:19:450
4003370992217,4cyclictest195782-21latency_hist23:50:000
4003370992216,5cyclictest4024186-21latency_hist19:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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