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2025-11-25 - 05:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue Nov 25, 2025 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
313538221050,2sleep30-21swapper/319:40:023
332283421040,1sleep00-21swapper/021:54:320
329420921030,1sleep00-21swapper/021:35:370
352252021010,2sleep20-21swapper/223:47:202
35746772840,2sleep20-21swapper/200:17:262
3096430992421,2cyclictest3541544-21sendmail-msp00:00:011
3096430992418,2cyclictest170550irq/121-eno121:45:011
3096429992313,6cyclictest3538220-21phc2sys-jitter23:55:320
3096429992312,6cyclictest0-21swapper/000:05:010
3096431992219,1cyclictest0-21swapper/222:15:012
3096430992219,2cyclictest3096428-21cyclictest23:40:011
3096429992219,2cyclictest3610910-21munin-run00:40:000
3096429992219,2cyclictest1-21systemd19:15:020
3096429992212,6cyclictest3455947-21kthreadcore23:10:280
835298210,6rtkit-daemon3102531-21munin-node23:29:130
3096431992119,1cyclictest0-21swapper/221:00:022
3096430992118,2cyclictest3297270-21grep21:40:021
3096430992118,2cyclictest1-21systemd00:15:001
3096430992113,3cyclictest0-21swapper/123:50:011
3096430992112,4cyclictest0-21swapper/122:30:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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