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2026-07-20 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jul 20, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6263142980,1sleep20-21swapper/211:20:022
7239662420,2sleep30-21swapper/312:26:083
284688992724,2cyclictest1-21systemd09:00:010
284688992522,2cyclictest663210-21grep11:45:010
284688992514,6cyclictest0-21swapper/012:35:010
284690992320,1cyclictest0-21swapper/209:15:032
284688992312,5cyclictest542039-21kthreadcore10:21:110
284688992213,5cyclictest0-21swapper/010:05:010
284690992119,1cyclictest0-21swapper/211:00:012
284690992118,1cyclictest0-21swapper/212:40:012
28468999213,11cyclictest664-21dbus-daemon08:45:011
284689992118,2cyclictest440552-21sh09:15:001
284689992112,2cyclictest555553-21kthreadcore10:31:111
284689992110,3cyclictest1309-21mta-sts-daemon11:04:481
28468899219,6cyclictest0-21swapper/010:51:020
284688992118,2cyclictest1-21systemd07:20:020
284688992114,6cyclictest0-21swapper/011:20:010
284688992111,6cyclictest0-21swapper/010:46:140
284688992110,6cyclictest0-21swapper/012:16:350
1157598210,3rtkit-daemon10930-21cron11:11:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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