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2026-07-26 - 14:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sun Jul 26, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244583522040,2sleep30-21swapper/322:25:503
242963221510,1sleep02429630-21ssh22:12:530
239694421310,2sleep12396841-21ssh21:50:571
26237322450,1sleep02623733-21expr00:25:520
22929822290,1sleep20-21swapper/220:35:562
2185771992522,1cyclictest0-21swapper/220:05:002
2185771992321,1cyclictest0-21swapper/220:30:022
2185771992320,1cyclictest0-21swapper/223:40:022
2185771992219,1cyclictest0-21swapper/222:30:022
2185771992219,1cyclictest0-21swapper/221:55:012
2185771992219,1cyclictest0-21swapper/221:10:022
2185770992219,2cyclictest2224368-21cron19:40:011
2185770992217,3cyclictest2566714-21kthreadcore23:45:561
2185765992211,6cyclictest0-21swapper/000:33:050
2185765992211,6cyclictest0-21swapper/000:33:050
2185771992119,1cyclictest0-21swapper/223:30:012
2185771992118,1cyclictest0-21swapper/222:25:012
2185771992111,3cyclictest0-21swapper/220:57:402
2185765992110,6cyclictest0-21swapper/021:15:010
2185771992017,1cyclictest0-21swapper/223:20:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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