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2026-08-22 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Aug 22, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78442522420,2sleep30-21swapper/323:40:043
75699021060,2sleep20-21swapper/223:25:032
8915492480,2sleep1891545-21munin-run00:40:021
5300272450,1sleep10-21swapper/121:17:031
5624732280,0sleep0562478-21kthreadcore21:35:060
4615012250,2sleep1461502-21kthreadcore20:30:051
350660992515,6cyclictest813-21systemd-logind22:35:030
350660992514,7cyclictest615891-21kthreadcore22:05:060
350662992411,8cyclictest596024-21kthreadcore21:55:041
350660992414,6cyclictest847620-21kthreadcore00:15:020
350662992320,2cyclictest522752-21cpu21:14:591
350660992314,5cyclictest24617-21JS14:54:060
350662992215,6cyclictest621442-21systemd-run22:10:021
350662992214,7cyclictest711498-21ssh23:00:031
350662992214,7cyclictest458771-21latency_hist20:30:011
6888382210,4sleep1351ktimers/122:45:061
350662992113,7cyclictest501575-21kthreadcore21:00:021
350662992113,7cyclictest417196-21turbostat20:00:011
350662992112,8cyclictest733110-21kthreadcore23:10:061
350662992112,8cyclictest350657-21cyclictest00:05:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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