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2026-02-11 - 07:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Feb 11, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
52144921040,1sleep20-21swapper/222:17:232
43533721020,2sleep30-21swapper/321:27:273
38416421020,2sleep30-21swapper/320:55:003
4088862390,1sleep10-21swapper/121:12:261
4065512370,1sleep30-21swapper/321:12:243
254369992820,2cyclictest134050irq/121-eno121:10:021
254369992819,2cyclictest134050irq/121-eno122:37:201
6894042260,2sleep20-21swapper/223:51:462
254369992413,2cyclictest134050irq/121-eno121:25:001
25436999230,22cyclictest768273-21perf00:35:011
254368992316,6cyclictest558753-21kthreadcore22:37:260
254368992211,6cyclictest0-21swapper/021:15:000
254369992118,2cyclictest1290-21dbus-daemon00:30:011
254369992118,2cyclictest1290-21dbus-daemon00:30:011
254368992119,1cyclictest705737-21apt00:00:010
254368992112,5cyclictest318066-21cut20:02:200
254368992110,6cyclictest0-21swapper/022:05:020
2649091201,5phc2sys0-21swapper/322:12:173
2649091200,2phc2sys0-21swapper/322:59:463
254370992017,1cyclictest0-21swapper/221:32:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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