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2026-05-18 - 17:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon May 18, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5793672990,3sleep30-21swapper/309:25:043
6133742970,2sleep20-21swapper/209:45:112
7078012900,1sleep00-21swapper/010:47:460
5149882880,2sleep00-21swapper/008:35:120
6485652430,0sleep0648562-21cut10:10:070
4726212310,2sleep20-21swapper/208:00:122
402810992414,9cyclictest0-21swapper/012:25:010
402811992315,3cyclictest627186-21kthreadcore09:55:091
402810992321,1cyclictest467867-21/usr/sbin/munin08:00:000
402811992219,2cyclictest601686-21grep09:40:011
402811992218,3cyclictest3824565-21in:imuxsock09:05:011
402810992219,2cyclictest861369-21cron12:30:000
402810992118,2cyclictest442670-21sh07:40:000
402810992117,3cyclictest1290-21dbus-daemon07:15:010
402810992113,7cyclictest691329-21runrttasks10:35:150
402810992113,6cyclictest0-21swapper/009:55:020
402810992112,7cyclictest0-21swapper/012:10:030
383433398210,5rtkit-daemon171ktimers/008:17:420
402811992017,2cyclictest838661-21latency_hist12:15:031
402811992017,2cyclictest800517-21latency_hist11:50:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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