You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-19 - 06:29
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Aug 19, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46092721070,2sleep30-21swapper/323:00:133
19629621010,1sleep10-21swapper/119:49:501
3815322930,3sleep30-21swapper/322:05:143
5603632700,0sleep1560365-21grep00:05:201
4649212320,1sleep00-21swapper/023:02:540
4143682320,2sleep20-21swapper/222:30:062
150489993121,2cyclictest69250irq/121-eno122:00:011
150489993015,2cyclictest69250irq/121-eno100:29:481
150490992522,2cyclictest0-21swapper/222:10:012
150488992513,6cyclictest0-21swapper/021:49:480
150488992421,2cyclictest369488-21awk22:00:010
150490992319,2cyclictest0-21swapper/223:30:122
150489992320,2cyclictest289172-21grep21:05:021
150489992219,2cyclictest465841-21ssh23:05:011
150489992216,1cyclictest69250irq/121-eno121:20:031
150488992212,5cyclictest298147-21kthreadcore21:10:120
150490992112,1cyclictest0-21swapper/222:15:022
150489992118,2cyclictest714-21gdbus21:00:001
150489992118,2cyclictest547612-21dump-pmu-power00:00:001
150489992116,3cyclictest458642-21latency_hist23:00:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional