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2026-06-02 - 00:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 01, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20689672670,1sleep02068965-21ssh09:29:380
21421312610,1sleep20-21swapper/210:14:542
1890478992721,5cyclictest1290-21dbus-daemon10:15:001
1890478992521,3cyclictest2043842-21grep09:10:001
383433398240,8rtkit-daemon3851704-21mta-sts-daemon09:20:240
1890477992416,3cyclictest2256439-21ssh11:30:020
189047799240,19cyclictest2197529-21/usr/sbin/munin10:54:450
189047799240,19cyclictest2197529-21/usr/sbin/munin10:54:450
1890479992320,1cyclictest0-21swapper/212:40:002
1890479992320,1cyclictest0-21swapper/210:25:012
1890478992321,1cyclictest501rcuop/207:14:511
20567862220,2sleep12056290-21ssh09:19:501
1890479992219,1cyclictest0-21swapper/207:50:002
1890478992219,2cyclictest1290-21dbus-daemon12:30:001
1890477992218,2cyclictest1962405-21sh08:05:020
2649091215,2phc2sys0-21swapper/307:19:493
21722212210,2sleep00-21swapper/010:34:520
1890479992119,1cyclictest0-21swapper/207:15:012
1890479992118,1cyclictest0-21swapper/208:05:012
1890478992118,2cyclictest0-21swapper/111:35:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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