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2025-06-28 - 22:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jun 28, 2025 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33559062860,1sleep30-21swapper/308:35:013
33594172450,0sleep13359421-21tr08:35:271
3250773992817,3cyclictest3531105-21cstates10:25:221
32623202260,1sleep10-21swapper/107:15:241
3250772992515,6cyclictest1761-21gdbus11:40:020
25010912518,3phc2sys0-21swapper/312:03:523
25010912518,3phc2sys0-21swapper/311:23:323
25010912518,2phc2sys0-21swapper/312:25:563
25010912517,3phc2sys0-21swapper/309:38:543
25010912418,3phc2sys0-21swapper/312:17:253
25010912418,3phc2sys0-21swapper/310:26:593
25010912418,2phc2sys0-21swapper/312:34:223
25010912418,2phc2sys0-21swapper/312:23:323
25010912418,2phc2sys0-21swapper/312:13:303
25010912418,2phc2sys0-21swapper/311:43:083
25010912418,2phc2sys0-21swapper/310:54:573
25010912418,2phc2sys0-21swapper/310:01:593
25010912418,2phc2sys0-21swapper/309:42:353
25010912418,2phc2sys0-21swapper/309:32:293
25010912418,2phc2sys0-21swapper/308:08:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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