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2026-05-12 - 16:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Tue May 12, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184876921810,3sleep30-21swapper/311:59:393
180892021000,2sleep30-21swapper/311:30:253
17659012440,1sleep10-21swapper/111:05:181
1434753993216,7cyclictest0-21swapper/012:25:010
1434754992925,2cyclictest134050irq/121-eno109:30:241
18435712250,1sleep11843575-21cut11:55:201
1434755992421,1cyclictest0-21swapper/212:35:012
1434755992421,1cyclictest0-21swapper/212:35:002
1434754992311,2cyclictest491rcuog/211:54:031
1434754992219,2cyclictest1441302-21latency_hist07:15:011
1434754992219,2cyclictest0-21swapper/109:50:231
1434754992216,2cyclictest1869843-21python312:10:251
1434754992216,2cyclictest134050irq/121-eno109:20:021
1434754992216,2cyclictest134050irq/121-eno109:20:021
1434754992118,2cyclictest1582388-21/usr/sbin/munin09:05:001
1434754992118,2cyclictest1493775-21systemd07:55:001
143475399219,7cyclictest0-21swapper/009:15:130
143475399219,7cyclictest0-21swapper/009:15:130
1434753992117,3cyclictest1879421-21wc12:20:000
2649091201,9phc2sys0-21swapper/307:05:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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