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2025-11-26 - 20:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Wed Nov 26, 2025 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200889821490,2sleep30-21swapper/308:45:283
202347421050,1sleep10-21swapper/109:00:211
21645852940,2sleep30-21swapper/310:23:553
20829862420,1sleep10-21swapper/109:35:281
23514872410,1sleep20-21swapper/212:10:272
20759452280,2sleep12075944-21ssh09:31:031
1886612992619,2cyclictest170550irq/121-eno111:20:291
1886612992611,10cyclictest0-21swapper/110:35:011
1886612992416,3cyclictest2159233-21kthreadcore10:20:371
1886611992416,7cyclictest0-21swapper/009:55:010
1886612992313,3cyclictest2116695-21kthreadcore09:55:281
1886612992313,3cyclictest2088734-21irqrtprio09:40:361
1886612992312,3cyclictest2152445-21kthreadcore10:15:281
1886611992316,6cyclictest2357218-21wc12:15:220
1886611992316,6cyclictest2091772-21kthreadcore09:40:380
1886611992315,4cyclictest2309615-21missed_timers11:45:300
1886611992311,8cyclictest2075143-21grep09:30:370
19127652220,0sleep11912764-21users07:25:321
1886612992219,2cyclictest1937460-21idleruntime-cro07:50:001
1886612992211,5cyclictest0-21swapper/111:00:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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