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2026-01-10 - 05:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Sat Jan 10, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2823577992822,2cyclictest134050irq/121-eno123:40:011
32039152260,1sleep10-21swapper/123:19:431
30144082250,1sleep03014410-21switchtime21:33:130
2823577992213,4cyclictest0-21swapper/121:35:011
2823573992218,2cyclictest0-21swapper/000:20:020
2823582992118,1cyclictest0-21swapper/221:00:012
2823577992112,4cyclictest0-21swapper/122:10:011
2823573992119,1cyclictest2830201-21grep19:15:020
2823573992110,6cyclictest0-21swapper/023:18:090
31665952200,2sleep30-21swapper/322:58:123
2823582992017,1cyclictest0-21swapper/221:50:012
2823582992017,1cyclictest0-21swapper/221:34:482
2823577992017,2cyclictest1329-21rs:main1
2823577992017,2cyclictest1326-21systemd-logind21:55:021
282357399209,6cyclictest0-21swapper/023:08:060
2902298190,4rtkit-daemon0-21swapper/022:58:240
2823582991917,1cyclictest0-21swapper/222:20:022
2823582991916,1cyclictest0-21swapper/222:51:372
2823582991916,1cyclictest0-21swapper/222:04:182
2823582991916,1cyclictest0-21swapper/200:23:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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