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2026-06-22 - 08:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 22, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
379102921090,2sleep20-21swapper/221:45:122
3585687992421,2cyclictest3717679-21gdbus20:55:010
358568999237,11cyclictest39048782sleep223:05:052
3585688992317,2cyclictest67250irq/126-eno121:40:121
3585687992320,2cyclictest3592326-21munin-run19:15:020
3585688992219,2cyclictest3897452-21systemd23:00:021
3585687992220,1cyclictest4000412-21latency_hist00:10:010
3585689992118,1cyclictest0-21swapper/200:10:012
3585688992118,2cyclictest3985522-21cmp00:00:001
3585688992118,2cyclictest3717850-21systemd20:55:021
3585688992118,2cyclictest0-21swapper/100:40:011
3585688992117,2cyclictest0-21swapper/100:15:021
3585688992114,6cyclictest3947053-21uptime23:30:191
3585688992114,3cyclictest3960760-21kthreadcore23:40:141
3585688992113,3cyclictest0-21swapper/123:28:481
3585687992118,2cyclictest3779681-21sendmail21:40:010
3585687992116,3cyclictest274-21systemd-journal21:24:560
3585687992114,6cyclictest3935197-21irqcore23:25:100
3585687992111,5cyclictest0-21swapper/022:55:070
3153791210,3phc2sys0-21swapper/322:55:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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