You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-19 - 10:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Mon Jan 19, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2869222460,0sleep1286926-21ptp4l-jitter20:48:001
2699602300,2sleep30-21swapper/320:37:483
163603992915,2cyclictest11systemd22:15:010
163603992812,15cyclictest0-21swapper/000:07:490
163603992613,5cyclictest677293-21switchtime00:32:590
163610992516,6cyclictest0-21swapper/220:20:012
163603992514,10cyclictest541163-21kthreadcore23:17:560
163603992513,8cyclictest586627-21kthreadcore23:42:560
163603992511,10cyclictest609595-21cpu23:57:510
163603992417,5cyclictest0-21swapper/021:45:010
163603992413,10cyclictest0-21swapper/023:10:010
163603992412,4cyclictest564687-21aten_repower_vo23:32:490
163603992412,11cyclictest511510-21cstates23:02:520
163603992412,11cyclictest0-21swapper/021:12:480
163603992411,9cyclictest430900-21cpuspeed_turbos22:17:490
163604992320,2cyclictest0-21swapper/123:35:021
163604992312,6cyclictest0-21swapper/122:50:011
163603992317,5cyclictest1290-21dbus-daemon23:30:010
163603992313,9cyclictest397469-21kthreadcore21:57:570
2902298220,2rtkit-daemon29021-21rtkit-daemon22:48:550
16360399229,5cyclictest0-21swapper/000:38:500
163603992218,3cyclictest0-21swapper/000:26:280
163603992216,5cyclictest263308-21cron20:30:000
163603992215,2cyclictest580505-21/usr/sbin/munin23:40:000
163603992215,2cyclictest508816-21latency_hist23:00:010
163603992215,2cyclictest275515-21sh20:40:010
163603992211,10cyclictest640838-21ssh00:12:560
163604992118,2cyclictest661095-21systemd00:25:011
163604992118,2cyclictest493868-21tail22:52:521
16360399219,4cyclictest0-21swapper/021:10:000
16360399217,5cyclictest0-21swapper/000:22:570
163603992114,2cyclictest455334-21sh22:30:000
163603992114,2cyclictest1-21systemd20:50:000
163603992114,2cyclictest0-21swapper/021:40:000
163603992114,2cyclictest0-21swapper/019:15:020
163603992113,3cyclictest192775-21kthreadcore19:32:540
2649091200,2phc2sys0-21swapper/321:15:123
2649091200,1phc2sys0-21swapper/323:09:303
163610992017,1cyclictest0-21swapper/222:15:012
163604992012,3cyclictest673443-21kthreadcore00:32:541
163604992011,4cyclictest163597-21cyclictest23:10:281
163604992011,4cyclictest0-21swapper/122:40:001
16360399207,5cyclictest0-21swapper/022:38:010
163603992013,2cyclictest347601-21latency_hist21:30:020
163603992013,2cyclictest226805-21munin-plugin-st20:00:010
2649091191,2phc2sys0-21swapper/323:21:573
163610991916,1cyclictest0-21swapper/222:55:012
163610991916,1cyclictest0-21swapper/221:54:032
163604991916,2cyclictest392246-21latency_hist21:55:011
163604991916,2cyclictest311727-21diskmemload23:20:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional