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2026-02-27 - 16:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Fri Feb 27, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4050950992421,2cyclictest285651-21grep11:50:001
4050950992418,2cyclictest191rcu_preempt10:21:591
4050951992220,1cyclictest0-21swapper/208:15:022
405095099228,9cyclictest338583-21cron12:20:001
4050950992216,2cyclictest134050irq/121-eno109:57:001
4050950992215,2cyclictest191rcu_preempt12:37:011
4050950992214,3cyclictest37337-21kthreadcore09:27:021
4050950992214,3cyclictest191rcu_preempt09:50:021
3357882220,1sleep20-21swapper/212:17:032
4050951992118,1cyclictest0-21swapper/211:40:022
4050950992115,2cyclictest191rcu_preempt11:57:031
4050950992115,2cyclictest191rcu_preempt11:09:521
4050950992112,4cyclictest61939-21cut09:42:021
4050950992112,4cyclictest18924-21cut09:17:011
4050950992111,4cyclictest13931-21cut09:15:021
405095099210,9cyclictest120066-21/usr/sbin/munin10:17:071
405095099204,10cyclictest4164852-21cut08:42:001
405095099204,10cyclictest358874-21cut12:31:581
4050950992014,2cyclictest191rcu_preempt12:21:401
4050950992014,2cyclictest191rcu_preempt11:27:001
4050950992014,2cyclictest134050irq/121-eno110:50:021
4050950992012,4cyclictest200334-21irqcore11:02:001
4050950992011,4cyclictest118658-21sed10:15:001
4050949992017,2cyclictest4174735-21sh08:50:000
4050949992012,4cyclictest36008-21kthreadcore09:27:010
4050949992011,5cyclictest208157-21aten_repower_cu11:06:540
4050949992010,6cyclictest0-21swapper/011:35:010
4050951991917,1cyclictest0-21swapper/207:10:002
405095099199,2cyclictest0-21swapper/110:01:571
405095099199,2cyclictest0-21swapper/109:54:171
405095099198,6cyclictest0-21swapper/108:02:041
405095099197,6cyclictest4183334-21kthreadcore08:57:021
405095099196,2cyclictest0-21swapper/112:10:451
405095099194,9cyclictest4074208-21kthreadcore07:27:021
405095099194,9cyclictest286954-21sh11:51:211
405095099193,10cyclictest271874-21cut11:42:011
405095099193,10cyclictest0-21swapper/107:45:011
4050950991916,2cyclictest4050947-21cyclictest09:10:021
4050950991915,2cyclictest4150362-21latency_hist08:30:021
4050950991913,2cyclictest191rcu_preempt09:31:561
4050950991911,3cyclictest251754-21/usr/sbin/munin11:32:011
405094999199,5cyclictest0-21swapper/011:56:570
405094999194,13cyclictest191rcu_preempt09:16:540
4050949991916,2cyclictest1290-21dbus-daemon12:35:010
4050949991913,5cyclictest368713-21kthreadcore12:37:010
4050949991913,1cyclictest4065038-21users07:17:070
405095199181,4cyclictest0-21swapper/210:51:552
405095099189,4cyclictest29154-21/usr/sbin/munin09:22:071
405095099189,4cyclictest29154-21/usr/sbin/munin09:22:071
405095099188,2cyclictest0-21swapper/110:09:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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