You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-27 - 00:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Thu Mar 26, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
363730921170,2sleep30-21swapper/309:35:013
38715452960,1sleep13871548-21cut11:51:221
38622972920,2sleep13862301-21cut11:46:211
36186622390,2sleep30-21swapper/309:22:393
3446666993327,3cyclictest1-21systemd10:10:010
3446666992614,8cyclictest1327-21in:imuxsock09:50:020
3446668992320,1cyclictest0-21swapper/209:20:012
3446667992320,2cyclictest3886707-21apt-key12:00:011
3446668992118,1cyclictest0-21swapper/212:21:162
3446668992118,1cyclictest0-21swapper/209:00:002
3446667992117,3cyclictest3768506-21kernelversion10:51:241
344666799211,4cyclictest3748832-21munin-run10:40:011
3446668992018,1cyclictest0-21swapper/211:40:012
3446668992017,1cyclictest0-21swapper/212:40:002
3446667992017,2cyclictest3570305-21apt-key08:50:001
3446667992016,3cyclictest0-21swapper/108:45:001
3446667992014,4cyclictest3453022-21munin-run07:15:011
3446667992013,3cyclictest3732703-21/usr/sbin/munin10:31:281
3446667992012,1cyclictest191rcu_preempt08:20:531
3446667992011,4cyclictest0-21swapper/112:30:001
3446666992017,2cyclictest3852544-21latency_hist11:40:020
3446666992017,2cyclictest3731626-21latency_hist10:30:010
3446668991916,1cyclictest0-21swapper/209:40:012
3446668991916,1cyclictest0-21swapper/209:35:002
3446667991916,2cyclictest0-21swapper/108:35:011
3446667991913,3cyclictest601rcuop/310:22:021
3446667991912,3cyclictest36-21ksoftirqd/112:20:001
344666699199,5cyclictest0-21swapper/009:55:020
344666699199,5cyclictest0-21swapper/009:31:290
3446666991911,4cyclictest3606722-21kthreadcore09:16:250
344666899189,2cyclictest0-21swapper/209:21:182
344666899184,2cyclictest0-21swapper/209:29:122
344666899181,9cyclictest0-21swapper/210:20:012
3446668991816,1cyclictest0-21swapper/212:30:012
3446668991816,1cyclictest0-21swapper/209:55:012
3446668991816,1cyclictest0-21swapper/209:50:022
3446668991815,1cyclictest0-21swapper/212:00:002
3446668991815,1cyclictest0-21swapper/208:36:192
344666799182,3cyclictest191rcu_preempt11:00:011
3446667991815,2cyclictest3895294-21cron12:05:001
3446667991812,2cyclictest3751114-21kthreadcore10:41:241
344666699188,5cyclictest0-21swapper/011:11:250
344666699187,6cyclictest0-21swapper/010:25:010
3446666991815,2cyclictest3860934-21latency_hist11:45:000
3446666991815,2cyclictest3453060-21tail07:15:010
3446666991815,2cyclictest1996-21runrttasks08:35:010
3446666991815,2cyclictest0-21swapper/012:00:000
2649091180,2phc2sys0-21swapper/310:31:503
344666899174,1cyclictest0-21swapper/212:04:222
3446668991714,1cyclictest0-21swapper/211:10:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional