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2025-06-17 - 02:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Mon Jun 16, 2025 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57208721090,2sleep30-21swapper/310:40:253
3151382870,2sleep10-21swapper/107:55:201
2499691300,2getstats0-21swapper/308:36:433
2499691280,2getstats0-21swapper/312:26:453
257044992716,6cyclictest0-21swapper/010:05:000
257045992522,2cyclictest0-21swapper/111:20:011
257044992517,7cyclictest559596-21/usr/sbin/munin10:35:020
257044992515,9cyclictest1695-21dbus-daemon12:05:010
25010912517,2phc2sys0-21swapper/309:20:593
25010912418,2phc2sys0-21swapper/311:35:063
25010912418,2phc2sys0-21swapper/311:16:463
25010912418,2phc2sys0-21swapper/310:55:223
25010912418,2phc2sys0-21swapper/310:34:303
25010912418,2phc2sys0-21swapper/310:03:353
25010912418,2phc2sys0-21swapper/309:43:393
25010912417,3phc2sys0-21swapper/309:52:293
25010912417,2phc2sys0-21swapper/310:11:533
25010912417,2phc2sys0-21swapper/309:10:253
74249422319,3sleep30-21swapper/312:17:213
257044992314,5cyclictest284193-21aten_repower_en07:30:170
25010912318,3phc2sys0-21swapper/312:32:003
25010912318,3phc2sys0-21swapper/312:11:363
25010912318,3phc2sys0-21swapper/312:02:063
25010912318,3phc2sys0-21swapper/311:49:523
25010912318,3phc2sys0-21swapper/311:31:443
25010912318,3phc2sys0-21swapper/311:29:003
25010912318,3phc2sys0-21swapper/311:01:343
25010912318,3phc2sys0-21swapper/310:38:143
25010912318,3phc2sys0-21swapper/310:15:453
25010912318,3phc2sys0-21swapper/310:06:073
25010912318,3phc2sys0-21swapper/309:59:013
25010912318,3phc2sys0-21swapper/309:46:353
25010912318,3phc2sys0-21swapper/309:37:093
25010912318,3phc2sys0-21swapper/309:15:453
25010912318,3phc2sys0-21swapper/308:02:393
25010912318,3phc2sys0-21swapper/307:21:163
25010912317,2phc2sys0-21swapper/310:21:153
25010912317,2phc2sys0-21swapper/309:30:133
25010912317,2phc2sys0-21swapper/308:59:433
25010912317,2phc2sys0-21swapper/308:08:443
25010912317,2phc2sys0-21swapper/307:55:583
25010912317,2phc2sys0-21swapper/307:46:083
25010912317,2phc2sys0-21swapper/307:15:123
25010912317,2phc2sys0-21swapper/307:15:113
25010912317,2phc2sys0-21swapper/307:14:433
25010912316,2phc2sys0-21swapper/312:20:233
70802522218,2sleep30-21swapper/311:58:183
61734022218,2sleep30-21swapper/311:05:273
43658122218,2sleep30-21swapper/309:25:283
257046992220,1cyclictest0-21swapper/212:10:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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