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2026-02-07 - 10:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Sat Feb 07, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62148221610,2sleep20-21swapper/219:27:342
6865792730,1sleep10-21swapper/120:22:311
8226232710,1sleep20-21swapper/221:52:372
595850992515,8cyclictest0-21swapper/200:40:022
10981712250,2sleep20-21swapper/200:32:242
595848992414,5cyclictest0-21swapper/022:20:010
595850992316,3cyclictest0-21swapper/222:52:232
595850992314,1cyclictest0-21swapper/221:00:012
595850992213,1cyclictest0-21swapper/221:20:012
595849992219,2cyclictest971481-21ssh23:20:011
595848992219,2cyclictest920852-21unixbench_singl22:47:360
595848992218,3cyclictest1042747-1atop00:00:020
595848992214,7cyclictest794278-21kthreadcore21:37:310
595848992214,4cyclictest788818-21latency_hist21:35:010
595848992211,6cyclictest0-21swapper/000:22:350
595850992119,1cyclictest0-21swapper/222:20:012
59585099211,8cyclictest0-21swapper/222:00:012
595850992118,1cyclictest0-21swapper/200:07:342
595850992113,1cyclictest0-21swapper/220:05:002
595849992118,2cyclictest0-21swapper/121:00:011
595849992116,1cyclictest491rcuog/220:50:001
595849992115,2cyclictest134050irq/121-eno100:35:021
595848992113,4cyclictest1089350-21cstates00:27:240
59585099201,5cyclictest0-21swapper/220:10:012
595849992017,2cyclictest967808-21sh23:15:011
595849992016,3cyclictest1288-1atopacctd23:45:001
595849992012,4cyclictest1021290-21kthreadcore23:47:291
595849992012,1cyclictest601rcuop/320:12:351
59584899209,6cyclictest0-21swapper/023:52:340
595848992017,2cyclictest997972-21awk23:35:000
595848992017,2cyclictest602003-21cpuspeed19:15:010
2649091201,2phc2sys0-21swapper/322:13:163
2649091200,3phc2sys0-21swapper/321:30:013
7370402190,1sleep20-21swapper/221:02:312
595850991916,1cyclictest0-21swapper/219:15:012
595849991916,2cyclictest634320-21dump-pmu-power19:40:001
595849991916,2cyclictest1290-21dbus-daemon23:10:011
59584899198,6cyclictest0-21swapper/021:30:010
595848991916,2cyclictest664546-21grep20:05:000
595848991916,2cyclictest1329-21rs:main0
595848991913,5cyclictest827016-21cut21:57:260
595848991910,5cyclictest893258-21kthreadcore22:32:300
595850991816,1cyclictest0-21swapper/222:50:012
595850991815,1cyclictest0-21swapper/223:30:002
595850991815,1cyclictest0-21swapper/223:05:002
595850991815,1cyclictest0-21swapper/221:27:342
595850991814,2cyclictest0-21swapper/223:10:022
595850991814,2cyclictest0-21swapper/223:00:002
595849991815,2cyclictest833315-21munin-run22:00:001
595849991815,2cyclictest640384-21turbostat19:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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