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2026-03-14 - 09:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Sat Mar 14, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
373126321110,2sleep30-21swapper/319:56:493
408313721080,1sleep14083140-21aten_repower_en23:41:351
367518021060,2sleep30-21swapper/319:15:023
3668607993017,8cyclictest3914036-21latency_hist22:05:010
366860799288,10cyclictest0-21swapper/022:41:340
37196572270,1sleep00-21swapper/019:50:010
3668607992711,9cyclictest0-21swapper/023:45:000
366860799268,2cyclictest0-21swapper/000:25:190
366860799260,18cyclictest3918630-21kthreadcore22:06:410
3668607992519,5cyclictest1326-21systemd-logind23:55:010
3668607992514,10cyclictest4121311-21kthreadcore00:01:410
3668607992511,13cyclictest3970089-21kthreadcore22:36:410
366860799248,10cyclictest4068688-21kthreadcore23:31:400
3668607992418,5cyclictest3896499-21grep21:55:020
3668607992416,7cyclictest3838848-21cut21:21:410
3668607992414,9cyclictest257-21systemd-journal21:49:550
3668607992413,10cyclictest3944855-21kthreadcore22:21:420
3668609992319,2cyclictest0-21swapper/219:25:002
3668608992320,2cyclictest1290-21dbus-daemon20:30:021
3668607992312,7cyclictest191rcu_preempt00:21:380
3668607992311,11cyclictest0-21swapper/022:20:000
366860799229,12cyclictest3950255-21/usr/sbin/munin22:26:400
366860799229,12cyclictest0-21swapper/022:55:010
366860799229,11cyclictest0-21swapper/000:15:010
366860799223,6cyclictest16-21ksoftirqd/019:51:380
366860799220,4cyclictest3898655-21irqrtprio21:56:390
39957652210,2sleep30-21swapper/322:51:393
3668608992118,2cyclictest3707176-21sendmail19:40:001
3668608992117,3cyclictest1426-21gdbus21:30:011
3668608992115,5cyclictest3675821-21cut19:15:021
366860799214,6cyclictest0-21swapper/021:02:430
366860799211,9cyclictest3931654-21cat22:15:020
366860799211,7cyclictest3689942-21df19:26:370
366860799211,7cyclictest3689942-21df19:26:370
3668607992110,9cyclictest4050655-21kthreadcore23:21:410
2902298210,5rtkit-daemon0-21swapper/021:26:280
2902298210,4rtkit-daemon3668605-21cyclictest19:37:570
2902298210,3rtkit-daemon3668605-21cyclictest23:38:510
2902298210,3rtkit-daemon3668605-21cyclictest20:31:290
3668608992018,1cyclictest3668605-21cyclictest00:30:011
3668608992014,5cyclictest3437812-21kworker/u16:1-writeback22:56:361
366860799209,9cyclictest0-21swapper/023:26:370
366860799207,3cyclictest501rcuop/220:35:080
366860799206,3cyclictest0-21swapper/023:16:390
366860799206,2cyclictest501rcuop/219:13:490
366860799206,1cyclictest491rcuog/220:26:400
366860799206,1cyclictest191rcu_preempt21:10:180
366860799205,9cyclictest0-21swapper/021:42:300
366860799205,9cyclictest0-21swapper/021:42:300
366860799205,3cyclictest191rcu_preempt23:49:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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