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2026-02-10 - 14:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackeslot2.osadl.org (updated Tue Feb 10, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283615821600,2sleep30-21swapper/323:32:263
288278721540,1sleep02882788-21ssh23:58:400
27867672920,2sleep10-21swapper/123:06:511
28013982580,1sleep1341rcuc/123:12:321
27561332380,2sleep20-21swapper/222:47:282
29445672360,2sleep10-21swapper/100:32:361
2432093993117,4cyclictest2888675-21runrttasks00:02:261
2432093992817,2cyclictest134050irq/121-eno100:07:231
26972062230,2sleep10-21swapper/122:16:171
2432093992320,2cyclictest2579585-21apt-key21:10:011
2649091221,9phc2sys0-21swapper/320:50:013
2432094992219,1cyclictest0-21swapper/200:25:002
2432093992216,2cyclictest134050irq/121-eno123:02:211
2432092992217,1cyclictest24889841systemd-run19:55:010
2432094992118,1cyclictest0-21swapper/223:12:242
2432094992118,1cyclictest0-21swapper/220:20:012
2432093992114,2cyclictest134050irq/121-eno121:25:011
243209299217,5cyclictest2910508-21wc00:15:000
2432092992115,5cyclictest2941874-21kthreadcore00:32:270
2432092992115,1cyclictest0-21swapper/023:30:000
2432092992115,1cyclictest0-21swapper/023:30:000
2432094992018,1cyclictest0-21swapper/223:40:012
2432094992017,1cyclictest0-21swapper/219:57:272
2432094992017,1cyclictest0-21swapper/219:22:262
243209299205,9cyclictest2720230-21cut22:27:270
243209299205,10cyclictest2706856-21aten2.4-expect22:22:200
2432094991917,1cyclictest0-21swapper/221:57:262
2432094991916,1cyclictest0-21swapper/222:32:262
2432094991916,1cyclictest0-21swapper/222:17:222
2432094991916,1cyclictest0-21swapper/221:27:252
2432094991916,1cyclictest0-21swapper/221:12:312
2432094991916,1cyclictest0-21swapper/219:40:012
2432094991916,1cyclictest0-21swapper/219:12:252
2432094991916,1cyclictest0-21swapper/200:32:212
2432094991915,2cyclictest0-21swapper/223:02:262
2432094991915,2cyclictest0-21swapper/222:25:002
2432094991915,2cyclictest0-21swapper/200:07:252
243209299194,9cyclictest2751364-21aten2.4-expect22:47:190
2432092991916,2cyclictest2856618-21cron23:45:000
2432092991915,1cyclictest491rcuog/223:54:270
2432092991913,5cyclictest2638582-21kthreadcore21:42:270
2649091180,2phc2sys0-21swapper/323:14:073
2649091180,2phc2sys0-21swapper/322:29:233
2432094991815,1cyclictest0-21swapper/223:57:302
2432094991815,1cyclictest0-21swapper/223:50:012
2432094991815,1cyclictest0-21swapper/222:02:262
2432094991815,1cyclictest0-21swapper/221:45:012
2432094991815,1cyclictest0-21swapper/220:50:012
2432094991815,1cyclictest0-21swapper/219:45:012
2432094991815,1cyclictest0-21swapper/200:10:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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