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2026-05-28 - 06:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Thu May 28, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
706147996836,31cyclictest739423-21kworker/1:221:00:141
706147996542,22cyclictest715777-21kworker/1:219:40:141
70614799650,63cyclictest0-21swapper/122:05:081
706147996461,2cyclictest0-21swapper/121:34:031
706147996444,18cyclictest416013-1kworker/1:2H19:55:011
70614799640,63cyclictest0-21swapper/123:45:281
706147996343,18cyclictest818473-21kworker/1:222:40:001
70614799630,62cyclictest0-21swapper/123:40:271
70614799630,62cyclictest0-21swapper/122:47:591
70614799630,62cyclictest0-21swapper/121:43:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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