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2026-03-24 - 21:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Tue Mar 24, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1049205997539,17cyclictest1178187-21kworker/1:111:05:231
104920599701,67cyclictest0-21swapper/110:22:271
104920599670,1cyclictest0-21swapper/107:33:021
104920599670,1cyclictest0-21swapper/107:14:461
1049205996647,18cyclictest1191145-21kworker/1:211:20:161
1049205996545,18cyclictest1250643-21kworker/1:312:30:141
1049205996455,5cyclictest1169422-21fschecks_time10:50:151
1049205996442,19cyclictest1068377-21kworker/1:008:30:111
1049205996441,20cyclictest1085360-21kworker/1:009:05:111
1049205996346,16cyclictest1082944-21kworker/1:109:00:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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