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2026-02-09 - 10:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Feb 09, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4136653997142,27cyclictest87831-21kworker/1:123:15:181
4136653997041,27cyclictest42105-21kworker/1:022:35:141
4136653997039,28cyclictest4570-21kworker/1:021:45:131
413665399686,1cyclictest239591350irq/16-snd_hda_22:53:451
413665399671,2cyclictest0-21swapper/122:18:221
4136653996636,28cyclictest3929274-1kworker/1:1H20:40:001
4136653996635,17cyclictest3929274-1kworker/1:1H22:55:161
413665399661,2cyclictest0-21swapper/123:02:201
4136653996537,17cyclictest83300-21kworker/1:223:10:141
413665399650,2cyclictest0-21swapper/119:53:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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