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2026-07-28 - 11:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Tue Jul 28, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3620102996947,21cyclictest3753346-21kworker/1:023:00:171
3620102996461,2cyclictest0-21swapper/123:15:231
3620102996246,15cyclictest3683113-21kworker/1:021:49:561
3620102996245,16cyclictest1810835-1kworker/1:0H19:51:141
3620102996242,18cyclictest3714805-21kworker/1:122:25:161
3620102996242,18cyclictest3714805-21kworker/1:122:25:151
362010299620,59cyclictest3810278-21needreboot23:55:191
3620102996144,16cyclictest1810835-1kworker/1:0H22:10:061
3620102996056,2cyclictest0-21swapper/100:27:391
3620102996042,17cyclictest3821357-21kworker/1:300:10:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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