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2026-02-25 - 12:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Feb 25, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
525937996562,2cyclictest0-21swapper/122:06:061
525937996360,1cyclictest632756-21ssh22:30:141
525937996344,18cyclictest702710-21kworker/1:200:00:131
525937996260,1cyclictest0-21swapper/123:50:211
52593799622,59cyclictest0-21swapper/119:14:061
525937996158,2cyclictest0-21swapper/123:38:461
525937996041,17cyclictest557171-21kworker/1:121:05:141
525937996038,20cyclictest2094356-1kworker/1:2H20:05:001
525937995942,15cyclictest649613-21kworker/1:123:05:131
525937995942,15cyclictest2094356-1kworker/1:2H00:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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