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2026-01-24 - 15:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sat Jan 24, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3564730996460,2cyclictest3736193-21/usr/sbin/munin23:45:001
356473099620,61cyclictest0-21swapper/121:46:371
3564730996132,26cyclictest3043249-1kworker/1:1H20:25:001
3564725996155,4cyclictest825361-1kworker/0:2H21:39:590
3564730996058,1cyclictest0-21swapper/123:12:271
3564730996043,16cyclictest3643740-21kworker/1:222:05:131
3564730996043,16cyclictest3633401-21kworker/1:121:50:131
3564730996040,18cyclictest3666491-21kworker/1:022:35:121
3564730995944,14cyclictest3745505-21kworker/1:323:55:141
3564730995944,14cyclictest3588737-21kworker/1:220:25:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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