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2026-04-20 - 13:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Apr 20, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43391599640,62cyclictest0-21swapper/122:35:141
43391599640,1cyclictest574065-21kworker/1:323:31:591
433915996245,15cyclictest518817-21kworker/1:022:10:141
43391599620,61cyclictest0-21swapper/121:38:291
433915996044,14cyclictest592586-21kworker/1:223:53:591
433915995944,14cyclictest498539-21kworker/1:021:45:151
433915995938,19cyclictest538008-21kworker/1:322:50:001
433915995843,14cyclictest592586-21kworker/1:223:42:021
433915995843,14cyclictest531744-21kworker/1:222:27:221
433915995843,14cyclictest457920-21kworker/1:020:41:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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