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2026-02-19 - 05:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Thu Feb 19, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133898399671,64cyclictest0-21swapper/100:25:471
133898399660,47cyclictest0-21swapper/123:05:121
133898399650,5cyclictest1489067-21fschecks_count23:20:141
1338983996360,2cyclictest0-21swapper/121:47:171
133898399630,62cyclictest0-21swapper/122:08:431
133898399630,1cyclictest0-21swapper/122:13:111
133898399630,1cyclictest0-21swapper/120:43:111
1338983996259,2cyclictest0-21swapper/123:50:221
1338983996258,2cyclictest0-21swapper/121:30:001
133898399620,1cyclictest0-21swapper/119:29:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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