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2025-12-10 - 04:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Dec 10, 2025 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185751099671,1cyclictest0-21swapper/120:14:461
1857510996644,20cyclictest1954173-21kworker/1:100:10:001
1857510996644,20cyclictest1954173-21kworker/1:100:10:001
185751099660,2cyclictest0-21swapper/122:27:081
1857510996559,3cyclictest0-21swapper/100:00:161
1857510996461,2cyclictest0-21swapper/123:25:281
1857510996461,2cyclictest0-21swapper/120:07:161
1857510996436,27cyclictest1867948-1kworker/1:2H20:35:001
1857510996247,14cyclictest1936362-21kworker/1:123:15:151
1857510996242,18cyclictest1954173-21kworker/1:100:25:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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