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2026-01-13 - 03:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Tue Jan 13, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2668236996648,17cyclictest2752455-21kworker/1:100:05:151
266823699631,61cyclictest0-21swapper/122:57:581
266823699621,60cyclictest0-21swapper/120:27:531
266823699620,60cyclictest0-21swapper/120:55:441
2668236996143,17cyclictest2701105-21kworker/1:021:07:031
266823699610,60cyclictest0-21swapper/120:16:281
2668236996043,16cyclictest2726264-21kworker/1:222:20:171
2668236996043,16cyclictest1032281-1kworker/1:2H19:25:161
2668236996042,17cyclictest2722122-21kworker/1:322:25:141
2668236996042,17cyclictest2722122-21kworker/1:322:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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