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2026-03-23 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Mar 23, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
47787299691,65cyclictest0-21swapper/108:15:211
477872996813,54cyclictest634-21sshd08:50:341
477872996359,2cyclictest0-21swapper/108:30:131
477872996346,16cyclictest600855-21kworker/1:110:55:141
477872996143,17cyclictest497539-21kworker/1:008:10:191
47787299610,60cyclictest0-21swapper/110:16:271
477872996042,17cyclictest552061-21kworker/1:209:55:131
477872995956,2cyclictest26350irq/16-i801_smb11:45:061
477872995943,15cyclictest648233-21kworker/1:212:05:261
477872995943,15cyclictest495370-21kworker/1:208:00:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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