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2026-06-15 - 22:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Jun 15, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184604499650,63cyclictest0-21swapper/120:00:141
184604499650,3cyclictest1808780-21sshd20:47:101
184604499640,2cyclictest0-21swapper/123:53:111
184604499620,11cyclictest0-21swapper/120:57:381
1846044996143,16cyclictest2002344-21kworker/1:123:48:131
1846048996047,2cyclictest3478920-1kworker/3:0H00:09:373
1846044996042,17cyclictest1979136-21kworker/1:023:15:141
1846044996042,17cyclictest1933218-21kworker/1:022:30:101
1846044996030,29cyclictest3140025-1kworker/1:0H20:19:591
1846044995943,15cyclictest1870736-21kworker/1:120:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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