You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-18 - 19:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sun Jan 18, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2487941996741,25cyclictest2590972-21kworker/1:010:44:591
248794199660,64cyclictest0-21swapper/110:19:551
2487945996242,18cyclictest1607117-1kworker/2:1H11:50:132
2487941996235,26cyclictest2183320-1kworker/1:2H08:20:001
2487941996143,17cyclictest2675599-21kworker/1:012:10:141
2487941996143,17cyclictest2623019-21kworker/1:011:05:161
2487941996143,17cyclictest2590972-21kworker/1:010:30:121
2487941996143,17cyclictest2576685-21kworker/1:210:20:141
2487941996126,33cyclictest2487759-21kworker/1:007:15:121
2487941996044,15cyclictest2541567-21kworker/1:009:45:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional