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2026-02-02 - 09:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Feb 02, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
213075996247,14cyclictest397987-21kworker/1:000:06:081
213075996044,15cyclictest233488-21kworker/1:220:20:481
213075996042,17cyclictest354487-21kworker/1:023:15:131
213075996042,16cyclictest1725608-1kworker/1:0H21:05:151
213075995944,14cyclictest266424-21kworker/1:221:30:131
213075995943,15cyclictest291005-21kworker/1:122:10:221
213075995943,14cyclictest1725608-1kworker/1:0H21:40:111
213075995942,16cyclictest1725608-1kworker/1:0H22:33:511
213075995843,14cyclictest408162-21kworker/1:300:25:011
213075995843,14cyclictest384392-21kworker/1:023:51:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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