You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-17 - 06:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sat Jan 17, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3708312996764,2cyclictest0-21swapper/120:19:021
3708312996562,2cyclictest0-21swapper/122:40:221
3708312996561,2cyclictest0-21swapper/100:20:311
370831299650,63cyclictest0-21swapper/123:58:071
370831299650,63cyclictest0-21swapper/120:21:461
3708312996461,2cyclictest0-21swapper/122:25:151
370831299640,63cyclictest0-21swapper/121:55:211
370831299640,63cyclictest0-21swapper/120:02:281
370831299640,63cyclictest0-21swapper/100:00:211
370831299640,62cyclictest0-21swapper/122:11:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional