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2026-07-19 - 10:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sun Jul 19, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2873258996441,21cyclictest2872207-21kworker/1:219:20:141
287325899641,62cyclictest0-21swapper/120:42:361
2873258996345,17cyclictest2897300-21kworker/1:320:30:141
2873258996238,23cyclictest2963136-21kworker/1:022:15:121
2873258996157,2cyclictest0-21swapper/119:11:301
2873257996157,2cyclictest2870302-21kworker/0:119:11:300
2873258996045,14cyclictest2893060-21kworker/1:220:25:011
2873258995944,14cyclictest2931521-21kworker/1:121:35:181
2873258995941,17cyclictest2952433-21kworker/1:122:00:141
2873258995843,14cyclictest2885072-21kworker/1:319:50:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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