You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-18 - 06:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sun Jan 18, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
86192997044,25cyclictest203534-21kworker/1:022:40:121
86192996939,29cyclictest263922-21kworker/1:000:00:131
86187996641,4cyclictest825361-1kworker/0:2H22:37:460
86192996361,1cyclictest0-21swapper/119:25:321
86192996242,18cyclictest184858-21kworker/1:222:37:461
86201996145,7cyclictest1451643-1kworker/3:0H22:35:163
86192996139,15cyclictest97856-21kworker/1:320:25:161
86192996138,14cyclictest263922-21kworker/1:023:55:181
8619299612,56cyclictest150518-21fschecks_count21:40:141
86192996058,1cyclictest0-21swapper/120:03:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional