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2026-01-25 - 04:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sun Jan 25, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4123175996439,24cyclictest333-21kworker/1:121:50:061
4123175996360,2cyclictest0-21swapper/121:19:001
4123175996338,24cyclictest4142052-21kworker/1:020:30:361
412317599630,62cyclictest0-21swapper/119:47:531
412317599630,62cyclictest0-21swapper/119:12:251
4123175996260,1cyclictest0-21swapper/119:25:501
4123175996243,18cyclictest4162026-21kworker/1:021:25:151
4123175996044,15cyclictest75323-21kworker/1:023:17:361
4123175996044,15cyclictest4142052-21kworker/1:020:19:551
4123175996044,15cyclictest4137413-21kworker/1:220:00:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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