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2026-03-12 - 21:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Thu Mar 12, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280398299680,4cyclictest2889240-21fschecks_time10:05:121
2803982996639,25cyclictest2805373-21kworker/1:207:35:121
2803982996536,27cyclictest2888810-21kworker/1:010:20:401
2803982996437,26cyclictest2641011-1kworker/1:2H08:10:131
2803982996244,16cyclictest2935515-21kworker/1:311:00:121
2803982996236,25cyclictest2974267-21kworker/1:012:05:141
2803982996142,17cyclictest2840469-21kworker/1:309:10:141
2803982996134,25cyclictest2641011-1kworker/1:2H08:45:151
2803982996043,15cyclictest2875143-21kworker/1:009:55:271
2803982996043,15cyclictest2805373-21kworker/1:207:45:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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