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2026-02-17 - 16:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Tue Feb 17, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
259357799650,63cyclictest2630630-21fschecks_count09:05:141
259357799640,1cyclictest0-21swapper/109:51:141
2593577996144,16cyclictest2699627-21kworker/1:110:30:141
2593577996055,3cyclictest2602308-21fschecks_time07:35:131
2593577996044,15cyclictest2590595-21kworker/1:207:10:151
2593577996043,16cyclictest2759242-21kworker/1:311:39:451
2593577996043,16cyclictest2098532-1kworker/1:1H11:25:061
2593577995956,2cyclictest0-21swapper/107:50:051
2593577995944,14cyclictest2633297-21kworker/1:309:45:111
2593577995943,15cyclictest2618961-21kworker/1:308:40:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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