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2026-04-22 - 23:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Apr 22, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3877297997728,47cyclictest3908526-21kworker/1:109:05:131
3877297997341,30cyclictest3978461-21kworker/1:010:35:131
3877297997042,26cyclictest3883743-21kworker/1:107:30:141
3877297996936,31cyclictest3891541-21kworker/1:208:00:131
3877297996762,3cyclictest0-21swapper/112:18:381
3877297996737,29cyclictest1804462-1kworker/1:2H12:00:141
3877297996638,27cyclictest1804462-1kworker/1:2H07:15:021
387729799660,64cyclictest3893092-21cron08:00:001
387729799650,63cyclictest3914980-21diskmemload11:42:401
3877297996433,29cyclictest4072711-21kworker/1:112:25:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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