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2026-03-14 - 00:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Fri Mar 13, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3358410997541,32cyclictest3372972-21kworker/1:308:30:011
335841099734,2cyclictest0-21swapper/108:06:271
3358410997239,31cyclictest3490640-21kworker/1:311:45:161
335841099720,70cyclictest634-21sshd12:29:551
335841099720,70cyclictest634-21sshd12:29:551
3358410997037,31cyclictest3480215-21kworker/1:111:00:001
3358410996846,19cyclictest3372972-21kworker/1:308:00:131
3358410996845,20cyclictest3490640-21kworker/1:311:30:011
3358410996835,31cyclictest2641011-1kworker/1:2H09:10:001
3358410996727,38cyclictest2641011-1kworker/1:2H08:39:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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