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2026-02-18 - 17:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Feb 18, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3154966997437,36cyclictest3164543-21kworker/1:008:00:141
3154966997341,30cyclictest3273599-21kworker/1:010:45:151
315496699700,1cyclictest3185180-21systemctl08:45:001
3154966996939,28cyclictest3341845-21kworker/1:212:05:131
3154966996936,31cyclictest2098532-1kworker/1:1H07:15:001
3154966996638,27cyclictest2098532-1kworker/1:1H12:10:131
315496699662,62cyclictest0-21swapper/108:27:421
3154966996540,23cyclictest3201538-21kworker/1:209:45:011
3154966996461,2cyclictest0-21swapper/107:29:391
3154966996443,19cyclictest3158332-21kworker/1:207:35:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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