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2026-02-22 - 12:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sun Feb 22, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3010105996840,26cyclictest3043632-21kworker/1:220:55:131
301010599661,63cyclictest0-21swapper/119:55:231
301010599661,3cyclictest3046158-21kworker/1:321:09:341
3010105996563,1cyclictest0-21swapper/123:45:201
3010105996460,2cyclictest0-21swapper/123:58:351
3010105996335,26cyclictest2492156-1kworker/1:1H20:50:131
301010599630,2cyclictest0-21swapper/122:10:151
3010105996258,2cyclictest0-21swapper/121:13:061
3010105996246,15cyclictest3118574-21kworker/1:122:35:151
3010105996235,26cyclictest2492156-1kworker/1:1H21:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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