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2026-02-20 - 05:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Fri Feb 20, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189756499661,63cyclictest0-21swapper/121:22:321
1897564996243,18cyclictest1909109-21kworker/1:119:45:141
1897564996243,18cyclictest1909109-21kworker/1:119:45:141
1897564996242,18cyclictest2012722-21kworker/1:122:40:131
1897564996230,31cyclictest2448156-1kworker/1:2H19:15:001
1897564996144,16cyclictest1915284-21kworker/1:220:15:181
1897564996143,17cyclictest2075186-21kworker/1:123:53:401
1897564996143,17cyclictest1978171-21kworker/1:322:00:011
1897564996143,17cyclictest1934063-21kworker/1:121:06:321
1897564996143,17cyclictest1904467-21kworker/1:219:30:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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