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2026-06-28 - 02:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sat Jun 27, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1948876996741,25cyclictest2019757-21kworker/1:309:47:561
1948876996461,2cyclictest0-21swapper/108:14:251
1948876996445,18cyclictest2143814-21kworker/1:212:05:161
1948876996142,18cyclictest1962088-21kworker/1:107:55:151
1948902996050,8cyclictest2427282-1kworker/2:0H10:25:152
1948876996043,16cyclictest1962088-21kworker/1:108:20:311
1948902995943,14cyclictest2427282-1kworker/2:0H07:45:302
1948876995957,1cyclictest0-21swapper/109:53:041
1948876995942,15cyclictest2088945-21kworker/1:211:15:161
1948876995941,17cyclictest4145554-1kworker/1:0H07:23:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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