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2026-07-22 - 11:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Jul 22, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323046997542,32cyclictest529880-21kworker/1:300:20:131
323046997141,28cyclictest529880-21kworker/1:300:25:161
323046997037,31cyclictest41282-1kworker/1:2H00:15:141
323046996835,32cyclictest481622-21kworker/1:223:25:131
323046996740,26cyclictest328065-21kworker/1:219:30:141
323046996734,31cyclictest371682-21kworker/1:221:35:151
323046996733,31cyclictest539544-21kworker/1:100:35:151
32304699671,63cyclictest0-21swapper/121:16:291
323046996640,25cyclictest385569-21kworker/1:121:45:151
323046996540,24cyclictest449586-21kworker/1:122:55:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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