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2026-03-04 - 13:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Mar 04, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154164996460,2cyclictest181960-21cat20:35:161
15416499640,2cyclictest0-21swapper/122:15:201
15416499630,62cyclictest0-21swapper/119:33:071
154164996159,1cyclictest0-21swapper/120:15:371
154164996144,16cyclictest290545-21kworker/1:223:15:021
154164996143,16cyclictest352411-21kworker/1:200:35:131
15416499610,60cyclictest0-21swapper/121:05:221
154164996043,16cyclictest262894-21kworker/1:122:35:121
154164996042,17cyclictest185640-21kworker/1:120:50:131
154164995942,16cyclictest347995-21kworker/1:100:25:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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