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2026-01-29 - 08:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Thu Jan 29, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2232480997153,17cyclictest2248999-21kworker/1:320:00:171
2232480996742,22cyclictest2344062-21kworker/1:023:20:151
2232480996663,2cyclictest0-21swapper/122:02:301
2232480996662,2cyclictest0-21swapper/100:16:301
2232480996360,2cyclictest0-21swapper/120:18:071
2232480996358,2cyclictest0-21swapper/123:41:171
2232480996343,18cyclictest2237466-21kworker/1:019:30:001
2232480996244,17cyclictest2256663-21kworker/1:020:45:131
2232480996242,19cyclictest2248999-21kworker/1:320:15:011
2232480996242,18cyclictest2301652-21kworker/1:221:47:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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