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2026-01-22 - 19:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Thu Jan 22, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2448072997134,35cyclictest2518096-21kworker/1:221:55:151
2448072997039,29cyclictest2478819-21kworker/1:120:55:141
2448072996841,26cyclictest2465407-21kworker/1:220:10:141
2448072996834,33cyclictest1497982-1kworker/1:2H23:05:011
244807299670,66cyclictest0-21swapper/122:20:381
2448072996635,29cyclictest1497982-1kworker/1:2H21:30:011
2448072996534,29cyclictest1497982-1kworker/1:2H00:15:001
244807299651,3cyclictest0-21swapper/123:57:271
2448072996238,22cyclictest1497982-1kworker/1:2H20:50:011
2448072996044,15cyclictest2612660-21kworker/1:123:50:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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