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2026-02-14 - 16:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sat Feb 14, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
968092997641,33cyclictest967986-21kworker/1:307:10:151
968092996938,29cyclictest1035596-21kworker/1:209:50:011
968092996836,30cyclictest1123165-21kworker/1:111:50:121
968092996644,21cyclictest1106543-21kworker/1:011:10:231
968092996641,24cyclictest3896207-1kworker/1:0H08:30:001
968092996535,18cyclictest967986-21kworker/1:307:15:151
96809299650,3cyclictest3715721-21snmpd12:00:001
968092996443,20cyclictest3896207-1kworker/1:0H07:45:061
968092996440,23cyclictest1102085-21kworker/1:211:25:011
968092996438,25cyclictest1073214-21kworker/1:110:35:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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