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2026-02-20 - 23:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Fri Feb 20, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6203499661,63cyclictest0-21swapper/107:13:541
6203499640,2cyclictest0-21swapper/107:42:011
62034996341,20cyclictest189259-21kworker/1:110:55:151
6203499630,1cyclictest0-21swapper/108:56:311
6203499620,2cyclictest198527-21sshd11:04:251
62034996157,2cyclictest0-21swapper/107:38:301
62034996041,17cyclictest230744-21kworker/1:111:50:121
6203499600,59cyclictest211667-21kworker/1:411:20:141
62034995943,15cyclictest99986-21kworker/1:309:10:311
62034995943,15cyclictest204833-21kworker/1:311:20:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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