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2026-02-13 - 15:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Fri Feb 13, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40127299671,1cyclictest0-21swapper/111:53:411
40127299660,3cyclictest0-21swapper/108:07:121
401272996461,2cyclictest0-21swapper/111:44:111
401272996359,2cyclictest0-21swapper/112:05:131
40127299630,61cyclictest0-21swapper/107:10:311
401272996241,19cyclictest420750-21kworker/1:108:30:141
40127299620,61cyclictest0-21swapper/108:27:401
401272996159,1cyclictest0-21swapper/107:45:211
401272996140,19cyclictest2493819-1kworker/1:2H08:20:001
401272995956,2cyclictest0-21swapper/110:52:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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