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2026-01-14 - 05:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Wed Jan 14, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2921616997132,37cyclictest676632-1kworker/1:0H22:00:001
292161699640,1cyclictest0-21swapper/119:55:541
292161699630,61cyclictest0-21swapper/100:10:491
2921616996236,15cyclictest2991931-21kworker/1:023:05:151
2921616996141,19cyclictest2975197-21kworker/1:322:35:121
2921616996058,1cyclictest0-21swapper/100:00:121
2921616996057,2cyclictest0-21swapper/123:00:061
2921616996042,16cyclictest676632-1kworker/1:0H23:40:141
2921616996041,18cyclictest2954609-21kworker/1:221:05:001
2921616996038,20cyclictest676632-1kworker/1:0H21:39:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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