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2026-09-14 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Sep 14, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1829071997366,5cyclictest1875639-21kworker/u8:209:30:311
1829071997143,19cyclictest279107-1kworker/1:2H12:20:001
182907199690,67cyclictest1998798-21fschecks_time11:35:161
1829071996529,17cyclictest279107-1kworker/1:2H12:15:001
1829071996460,2cyclictest0-21swapper/107:30:241
182907199640,63cyclictest329-21jbd2/mmcblk0p2-08:40:361
1829071996242,19cyclictest1934983-21kworker/1:110:35:181
1829071996044,15cyclictest1908517-21kworker/1:310:15:011
1829071996044,15cyclictest1834087-21kworker/1:207:45:001
1829071996043,16cyclictest2044952-21kworker/1:112:35:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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