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2026-08-03 - 13:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Aug 03, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2667515996936,32cyclictest2703888-21kworker/1:221:10:001
2667515996344,18cyclictest2725799-21kworker/1:121:34:591
2667515996342,20cyclictest2665936-21kworker/1:019:10:141
2667515996337,15cyclictest2812436-21kworker/1:323:12:071
2667515996245,16cyclictest2748412-21kworker/1:222:25:011
2667515996242,18cyclictest2818897-21kworker/1:223:40:131
2667515996143,16cyclictest2854562-21kworker/1:300:20:141
2667515996044,15cyclictest2748412-21kworker/1:222:13:021
2667515996044,15cyclictest2725799-21kworker/1:121:35:161
2667515996044,15cyclictest2697965-21kworker/1:120:45:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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