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2026-06-19 - 01:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Thu Jun 18, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1612639997341,30cyclictest1435208-1kworker/1:1H11:55:061
1612639997140,29cyclictest1620944-21kworker/1:107:35:151
1612639997038,31cyclictest1435208-1kworker/1:1H09:16:391
1612639996938,28cyclictest1435208-1kworker/1:1H10:20:261
1612639996937,30cyclictest1691625-21kworker/1:110:00:141
1612639996937,30cyclictest1691625-21kworker/1:110:00:131
1612639996864,2cyclictest0-21swapper/108:55:261
1612639996737,28cyclictest1621761-21kworker/1:307:50:011
1612639996554,3cyclictest0-21swapper/108:51:171
1612639996542,21cyclictest1810510-21kworker/1:312:15:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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