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2026-01-19 - 15:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Mon Jan 19, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3093471997131,38cyclictest2546748-1kworker/1:0H12:05:011
309347199650,63cyclictest3272706-21ssh11:50:141
309347199650,2cyclictest3242586-21mailstats11:15:211
3093471996459,3cyclictest0-21swapper/107:33:181
3093471996444,18cyclictest3093281-21kworker/1:207:15:131
309347199630,62cyclictest0-21swapper/111:31:231
3093471996236,25cyclictest3109260-21kworker/1:208:00:131
3093471996041,17cyclictest3246383-21kworker/1:311:25:011
3093471995854,2cyclictest0-21swapper/110:25:051
3093471995840,17cyclictest3116604-21kworker/1:008:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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