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2026-08-09 - 15:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sun Aug 09, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1271153996460,2cyclictest0-21swapper/122:36:011
1271153996460,2cyclictest0-21swapper/120:45:371
1271153996235,26cyclictest1361651-21kworker/1:022:15:141
127115399620,61cyclictest0-21swapper/123:30:511
127115399620,2cyclictest0-21swapper/121:15:001
127115399610,1cyclictest0-21swapper/123:10:061
1271153996042,17cyclictest1303159-21kworker/1:320:50:151
1271153996036,21cyclictest1445403-21kworker/1:323:50:131
1271153995944,14cyclictest1396803-21kworker/1:122:50:061
1271153995943,15cyclictest1356839-21kworker/1:222:07:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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