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2026-02-21 - 12:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Sat Feb 21, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2432291996850,15cyclictest224664-1kworker/2:0H23:55:132
2432291996850,15cyclictest224664-1kworker/2:0H23:55:132
243228899650,2cyclictest0-21swapper/100:00:131
2432288996462,1cyclictest0-21swapper/100:18:131
2432288996462,1cyclictest0-21swapper/100:18:131
2432288996461,2cyclictest0-21swapper/123:40:481
2432288996461,2cyclictest0-21swapper/100:09:551
243228899640,61cyclictest2462070-21fschecks_count20:40:131
2432288996360,2cyclictest0-21swapper/122:19:061
243228899630,61cyclictest0-21swapper/123:11:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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