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2026-01-30 - 09:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Fri Jan 30, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2772321996745,20cyclictest2803395-21kworker/1:320:50:141
2772321996646,18cyclictest2967444-21kworker/1:000:15:141
2772321996562,2cyclictest0-21swapper/121:20:211
2772321996562,2cyclictest0-21swapper/121:20:211
2772321996439,23cyclictest2938188-21kworker/1:023:40:061
2772321996343,18cyclictest2890240-21kworker/1:022:45:141
277232199630,2cyclictest0-21swapper/122:35:361
2772321996243,17cyclictest2774479-21kworker/1:219:40:141
2772321996241,19cyclictest2827131-21kworker/1:221:40:141
2772321996143,17cyclictest2840753-21kworker/1:121:49:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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