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2026-01-20 - 16:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot3.osadl.org (updated Tue Jan 20, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3697441996829,19cyclictest3713498-21kworker/1:008:05:161
369744199631,61cyclictest0-21swapper/112:30:451
369744199630,61cyclictest590-21dbus-daemon12:40:011
3697441996259,2cyclictest0-21swapper/109:20:251
3697441996158,2cyclictest0-21swapper/110:13:221
3697441996044,15cyclictest3838212-21kworker/1:311:15:261
3697441996044,15cyclictest3795172-21kworker/1:210:28:221
3697441996044,15cyclictest3735416-21kworker/1:009:25:121
3697441996043,16cyclictest3718137-21kworker/1:108:24:551
3697441996043,16cyclictest3697250-21kworker/1:207:25:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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