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2026-03-03 - 23:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot3.osadl.org (updated Tue Mar 03, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1972967996842,25cyclictest1995262-21kworker/1:008:25:161
197296799681,65cyclictest2069405-21fschecks_count10:20:131
197296799660,64cyclictest2010991-21diskmemload10:25:171
1972967996440,22cyclictest1141641-1kworker/1:1H11:15:001
1972967996342,19cyclictest2111289-21kworker/1:011:20:131
197296799630,61cyclictest0-21swapper/109:50:021
1972967996259,2cyclictest0-21swapper/110:45:211
1972967996242,19cyclictest2061235-21kworker/1:310:10:151
1972967996241,18cyclictest2000150-21kworker/1:108:40:141
1972967996240,20cyclictest1978256-21kworker/1:007:50:151
1972967996143,16cyclictest1141641-1kworker/1:1H07:45:311
1972967996142,17cyclictest1974584-21kworker/1:307:25:171
1972967996055,3cyclictest0-21swapper/107:43:011
197296799600,2cyclictest2015096-21systemd-run09:15:001
1972967995956,2cyclictest0-21swapper/111:25:321
1972967995956,2cyclictest0-21swapper/108:13:371
1972967995956,2cyclictest0-21swapper/108:13:371
1972967995941,17cyclictest2079538-21kworker/1:110:34:551
1972967995941,17cyclictest2039861-21kworker/1:309:45:151
1972967995939,19cyclictest1141641-1kworker/1:1H09:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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