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2025-11-25 - 10:14

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Tue Nov 25, 2025 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4135162991082,3cyclictest131rcu_preempt21:45:022
4135155991021,98cyclictest0-21swapper/000:35:030
413516099896,5cyclictest23-21ksoftirqd/121:00:021
413515599681,4cyclictest131rcu_preempt21:50:010
413515599666,7cyclictest121ksoftirqd/022:28:200
413515599664,9cyclictest12-21ksoftirqd/023:40:010
413515599664,9cyclictest12-21ksoftirqd/023:40:000
413515599642,5cyclictest131rcu_preempt22:04:210
413516699634,9cyclictest37-21ksoftirqd/300:00:003
413515599636,10cyclictest12-21ksoftirqd/022:45:000
413515599627,25cyclictest131rcu_preempt20:05:020
4135160996014,7cyclictest23-21ksoftirqd/123:30:021
4135155996017,6cyclictest131rcu_preempt20:25:000
4135155996010,6cyclictest131rcu_preempt23:10:020
413515599596,5cyclictest131rcu_preempt20:00:020
413515599591,7cyclictest121ksoftirqd/022:10:210
413515599591,11cyclictest12-21ksoftirqd/000:15:000
4135155995910,5cyclictest131rcu_preempt22:20:010
4135162995838,15cyclictest235-21systemd-journal00:15:002
413515599589,5cyclictest131rcu_preempt20:15:020
413515599586,8cyclictest12-21ksoftirqd/020:50:020
4135155995813,5cyclictest131rcu_preempt19:45:020
4135155995711,5cyclictest131rcu_preempt19:50:020
413516099566,7cyclictest23-21ksoftirqd/100:30:021
413515599567,6cyclictest131rcu_preempt23:00:010
413515599566,11cyclictest12-21ksoftirqd/020:30:020
413515599562,5cyclictest131rcu_preempt00:10:020
413516699551,5cyclictest131rcu_preempt23:40:013
413516699551,5cyclictest131rcu_preempt23:40:003
413516099559,10cyclictest23-21ksoftirqd/123:20:021
413516099558,8cyclictest23-21ksoftirqd/119:20:001
413516099555,8cyclictest23-21ksoftirqd/122:30:011
413515599558,6cyclictest131rcu_preempt00:40:020
413515599554,6cyclictest12-21ksoftirqd/023:05:020
4135155995524,8cyclictest12-21ksoftirqd/022:40:030
413515599551,5cyclictest131rcu_preempt21:24:210
4135155995515,10cyclictest12-21ksoftirqd/019:40:010
413516099549,9cyclictest23-21ksoftirqd/121:55:021
413516099544,8cyclictest23-21ksoftirqd/121:40:011
413516099544,8cyclictest23-21ksoftirqd/120:45:021
413516099543,8cyclictest23-21ksoftirqd/120:40:001
413516099542,18cyclictest23-21ksoftirqd/122:50:021
413516099542,18cyclictest23-21ksoftirqd/122:50:021
413515599547,9cyclictest12-21ksoftirqd/021:55:020
413515599546,8cyclictest12-21ksoftirqd/020:10:010
413515599546,6cyclictest131rcu_preempt23:15:020
4135155995413,6cyclictest131rcu_preempt00:00:020
4135155995410,5cyclictest131rcu_preempt22:50:020
4135155995410,5cyclictest131rcu_preempt22:50:020
413516699536,8cyclictest37-21ksoftirqd/321:20:003
413516099539,8cyclictest23-21ksoftirqd/119:50:011
413516099537,9cyclictest23-21ksoftirqd/100:02:561
413516099536,10cyclictest23-21ksoftirqd/122:55:011
413516099533,9cyclictest23-21ksoftirqd/121:05:011
413516099533,10cyclictest23-21ksoftirqd/119:45:021
4135160995321,9cyclictest23-21ksoftirqd/122:00:011
4135160995313,11cyclictest23-21ksoftirqd/122:25:021
4135160995311,10cyclictest23-21ksoftirqd/120:50:021
413515599539,11cyclictest12-21ksoftirqd/021:15:000
413515599538,8cyclictest12-21ksoftirqd/022:00:000
413515599537,9cyclictest12-21ksoftirqd/000:30:000
413515599536,7cyclictest12-21ksoftirqd/023:55:020
413515599536,7cyclictest12-21ksoftirqd/023:55:020
413515599535,9cyclictest12-21ksoftirqd/000:05:000
4135155995344,5cyclictest4135158-21ls19:10:020
4135155995310,7cyclictest131rcu_preempt21:40:010
4135155995310,5cyclictest131rcu_preempt19:30:020
413516699525,8cyclictest37-21ksoftirqd/323:25:023
4135166995232,9cyclictest37-21ksoftirqd/321:35:003
4135166995223,21cyclictest361rcuc/322:00:023
4135162995245,5cyclictest30-21ksoftirqd/222:35:022
4135162995245,5cyclictest30-21ksoftirqd/222:35:022
413516099529,9cyclictest23-21ksoftirqd/120:25:011
413516099528,8cyclictest23-21ksoftirqd/123:00:021
413516099528,7cyclictest23-21ksoftirqd/121:17:001
413516099525,9cyclictest23-21ksoftirqd/100:15:011
413516099525,11cyclictest23-21ksoftirqd/121:45:011
413516099524,10cyclictest23-21ksoftirqd/100:40:011
413515599529,5cyclictest131rcu_preempt23:30:020
413515599523,7cyclictest12-21ksoftirqd/021:30:020
413515599523,40cyclictest4149698-21modprobe23:50:000
413515599522,8cyclictest12-21ksoftirqd/021:45:010
4135155995214,10cyclictest12-21ksoftirqd/020:20:020
4135155995213,11cyclictest12-21ksoftirqd/020:30:020
4135155995212,6cyclictest131rcu_preempt21:10:020
4135155995210,5cyclictest131rcu_preempt21:20:030
413516099517,7cyclictest23-21ksoftirqd/122:05:021
413516099516,7cyclictest23-21ksoftirqd/123:35:021
413516099515,9cyclictest23-21ksoftirqd/123:40:021
413516099515,9cyclictest23-21ksoftirqd/123:40:021
413516099513,9cyclictest23-21ksoftirqd/100:25:021
4135160995134,13cyclictest272-21dbus-daemon20:15:011
413516099512,10cyclictest23-21ksoftirqd/119:15:011
413515599519,5cyclictest131rcu_preempt00:20:000
413515599517,6cyclictest131rcu_preempt23:20:010
413515599516,7cyclictest12-21ksoftirqd/000:25:020
413515599516,5cyclictest131rcu_preempt19:15:010
413515599515,8cyclictest12-21ksoftirqd/023:25:010
4135155995111,6cyclictest131rcu_preempt23:45:000
4135155995111,6cyclictest131rcu_preempt22:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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