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2026-01-24 - 10:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Sat Jan 24, 2026 00:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3734578999926,70cyclictest12-21ksoftirqd/020:00:020
3734578999086,2cyclictest0-21swapper/020:05:020
373457899891,84cyclictest0-21swapper/019:55:010
373457899861,78cyclictest0-21swapper/020:35:020
3734578996864,2cyclictest0-21swapper/019:25:030
373458999669,5cyclictest131rcu_preempt21:30:012
373458999669,5cyclictest131rcu_preempt21:30:012
3734589996613,18cyclictest131rcu_preempt22:00:002
373457899661,32cyclictest12-21ksoftirqd/000:30:020
373459299656,9cyclictest37-21ksoftirqd/321:15:013
373458599658,52cyclictest3784026-21ssh22:45:031
373458599656,8cyclictest23-21ksoftirqd/121:40:001
3734585996523,9cyclictest23-21ksoftirqd/100:30:011
373458999649,6cyclictest131rcu_preempt22:40:002
373458999649,6cyclictest131rcu_preempt22:40:002
3734589996412,6cyclictest131rcu_preempt21:40:002
373458599648,9cyclictest23-21ksoftirqd/100:00:021
3734592996310,6cyclictest131rcu_preempt00:05:013
3734592996310,6cyclictest131rcu_preempt00:05:013
373458999632,5cyclictest131rcu_preempt21:45:022
3734592996210,6cyclictest131rcu_preempt00:00:023
3734589996210,6cyclictest131rcu_preempt19:20:022
3734589996210,5cyclictest131rcu_preempt23:55:022
3734578996254,5cyclictest3734584-21grep19:10:020
3734585996144,13cyclictest3467602-21systemd-journal23:40:001
3734585996113,5cyclictest131rcu_preempt21:35:021
373457899617,6cyclictest131rcu_preempt21:00:000
373457899612,20cyclictest3786195-21cat22:50:010
373457899611,28cyclictest131rcu_preempt00:10:450
3734592996017,6cyclictest131rcu_preempt00:30:003
373458999606,6cyclictest131rcu_preempt21:20:002
3734585996022,11cyclictest23-21ksoftirqd/100:40:021
3734585996016,6cyclictest131rcu_preempt23:11:081
3734585996016,11cyclictest23-21ksoftirqd/122:27:201
3734585996016,10cyclictest23-21ksoftirqd/121:50:021
3734578996016,10cyclictest131rcu_preempt21:38:440
3734592995938,16cyclictest1-21systemd19:25:023
3734592995918,14cyclictest37-21ksoftirqd/322:55:023
3734592995912,6cyclictest131rcu_preempt21:40:013
373458999595,5cyclictest131rcu_preempt19:40:022
373458999591,5cyclictest131rcu_preempt20:50:022
373458599596,10cyclictest23-21ksoftirqd/100:25:011
373458599594,8cyclictest23-21ksoftirqd/100:10:001
3734585995914,6cyclictest131rcu_preempt23:28:271
3734578995924,31cyclictest12-21ksoftirqd/022:28:100
373459299584,6cyclictest37-21ksoftirqd/300:10:013
3734592995832,10cyclictest37-21ksoftirqd/300:15:043
3734592995814,13cyclictest37-21ksoftirqd/323:00:023
373458999586,6cyclictest131rcu_preempt00:40:012
3734589995818,7cyclictest131rcu_preempt20:00:002
373458599589,9cyclictest23-21ksoftirqd/100:14:251
373458599586,9cyclictest23-21ksoftirqd/121:40:271
3734585995815,6cyclictest131rcu_preempt23:00:201
3734585995815,5cyclictest131rcu_preempt00:30:051
3734585995812,5cyclictest131rcu_preempt22:20:031
3734578995828,14cyclictest3760965-21ssh21:54:390
373457899581,23cyclictest131rcu_preempt22:39:200
373457899581,23cyclictest131rcu_preempt22:39:190
373459299578,6cyclictest131rcu_preempt23:30:013
373459299576,5cyclictest131rcu_preempt22:15:003
373459299574,5cyclictest131rcu_preempt23:10:023
3734592995712,18cyclictest131rcu_preempt23:55:013
3734592995710,6cyclictest131rcu_preempt21:05:013
373458999579,5cyclictest131rcu_preempt00:10:022
373458999577,6cyclictest131rcu_preempt19:25:002
373458999575,6cyclictest131rcu_preempt22:20:022
373458999573,6cyclictest131rcu_preempt00:05:022
373458999573,6cyclictest131rcu_preempt00:05:012
3734589995732,10cyclictest30-21ksoftirqd/200:00:002
3734589995711,6cyclictest131rcu_preempt21:23:512
373458599579,12cyclictest23-21ksoftirqd/122:05:011
373458599579,12cyclictest23-21ksoftirqd/122:05:011
373458599577,9cyclictest23-21ksoftirqd/122:41:411
373458599577,11cyclictest23-21ksoftirqd/100:20:011
3734585995713,6cyclictest131rcu_preempt22:40:021
3734585995713,6cyclictest131rcu_preempt22:40:011
3734585995713,5cyclictest131rcu_preempt21:25:391
3734585995713,5cyclictest131rcu_preempt21:25:381
3734585995711,7cyclictest131rcu_preempt21:10:021
3734585995711,6cyclictest131rcu_preempt23:05:231
3734585995711,5cyclictest131rcu_preempt22:35:011
3734585995711,14cyclictest23-21ksoftirqd/120:05:021
3734578995748,4cyclictest12-21ksoftirqd/022:05:020
3734578995748,4cyclictest12-21ksoftirqd/022:05:010
373457899572,39cyclictest19350irq/34-mmc123:05:030
373459299568,6cyclictest131rcu_preempt21:35:013
3734592995626,11cyclictest37-21ksoftirqd/322:50:023
3734592995615,8cyclictest37-21ksoftirqd/322:45:013
3734592995612,6cyclictest131rcu_preempt20:35:023
3734592995612,5cyclictest131rcu_preempt23:00:423
3734592995610,6cyclictest131rcu_preempt20:25:013
373458999565,6cyclictest131rcu_preempt20:42:082
373458999565,6cyclictest131rcu_preempt00:25:002
3734589995619,9cyclictest30-21ksoftirqd/200:15:022
3734589995614,11cyclictest30-21ksoftirqd/222:45:012
373458599569,5cyclictest131rcu_preempt22:14:411
373458599568,6cyclictest131rcu_preempt21:52:471
373458599563,9cyclictest23-21ksoftirqd/120:49:071
3734585995618,5cyclictest131rcu_preempt21:18:131
3734585995614,5cyclictest131rcu_preempt21:25:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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