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2026-01-22 - 21:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Thu Jan 22, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3103069999017,6cyclictest131rcu_preempt21:40:040
310306999698,33cyclictest131rcu_preempt23:01:570
3103069996732,20cyclictest12-21ksoftirqd/022:34:380
3103069996620,30cyclictest12-21ksoftirqd/022:42:040
310306999651,4cyclictest131rcu_preempt21:13:210
310306999651,4cyclictest131rcu_preempt21:13:210
310306999651,42cyclictest0-21swapper/023:16:500
3103069996419,30cyclictest12-21ksoftirqd/022:55:400
3103074996330,15cyclictest23-21ksoftirqd/121:49:451
310306999637,5cyclictest131rcu_preempt22:13:500
310306999632,30cyclictest131rcu_preempt22:50:030
310306999626,50cyclictest3131771-21modprobe22:00:000
310306999624,40cyclictest0-21swapper/022:55:010
3103069996216,6cyclictest131rcu_preempt21:50:020
310306999618,32cyclictest131rcu_preempt00:27:100
3103079995934,16cyclictest37-21ksoftirqd/323:33:043
3103069995926,5cyclictest131rcu_preempt21:10:020
310306999592,5cyclictest131rcu_preempt22:18:430
310306999592,5cyclictest131rcu_preempt22:18:430
3103069995914,41cyclictest12-21ksoftirqd/023:13:570
3103074995833,17cyclictest23-21ksoftirqd/100:19:121
310306999587,32cyclictest131rcu_preempt22:20:470
3103069995815,7cyclictest131rcu_preempt22:40:000
3103079995724,23cyclictest37-21ksoftirqd/321:38:583
3103074995737,8cyclictest23-21ksoftirqd/122:15:001
310306999577,6cyclictest131rcu_preempt00:11:270
3103069995719,34cyclictest16850irq/134-800000021:31:240
3103069995719,34cyclictest16850irq/134-800000021:31:240
3103069995718,6cyclictest0-21swapper/023:53:300
310306999571,40cyclictest3178149-21ssh23:42:040
3103069995710,22cyclictest131rcu_preempt21:44:200
3103079995624,21cyclictest37-21ksoftirqd/323:14:193
3103076995627,9cyclictest30-21ksoftirqd/223:00:002
3103076995614,5cyclictest131rcu_preempt22:53:162
3103069995635,13cyclictest12-21ksoftirqd/021:15:320
3103069995619,32cyclictest16850irq/134-800000000:30:380
3103069995617,34cyclictest12-21ksoftirqd/023:10:010
3103069995513,38cyclictest12-21ksoftirqd/022:26:120
3103079995431,12cyclictest37-21ksoftirqd/322:03:293
3103079995427,16cyclictest37-21ksoftirqd/322:09:213
3103079995427,16cyclictest37-21ksoftirqd/322:09:213
3103079995420,17cyclictest37-21ksoftirqd/323:37:403
3103074995425,19cyclictest23-21ksoftirqd/122:28:211
310306999545,5cyclictest131rcu_preempt21:00:020
310306999545,40cyclictest12-21ksoftirqd/023:45:350
3103069995426,13cyclictest3114694-21ssh21:21:520
3103069995426,13cyclictest3114694-21ssh21:21:520
3103069995419,31cyclictest16850irq/134-800000000:04:010
3103069995418,32cyclictest16850irq/134-800000023:24:010
3103069995418,32cyclictest16850irq/134-800000023:24:010
3103069995418,32cyclictest16850irq/134-800000000:23:300
3103069995418,31cyclictest16850irq/134-800000000:39:350
3103069995417,6cyclictest16850irq/134-800000022:03:320
310306999541,36cyclictest3116304-21ssh21:25:210
3103079995324,15cyclictest37-21ksoftirqd/322:33:193
3103076995325,11cyclictest30-21ksoftirqd/200:00:002
310306999534,11cyclictest3186043-40mandb00:00:000
3103069995334,15cyclictest275-21dbus-daemon19:40:000
3103069995334,15cyclictest275-21dbus-daemon19:39:590
3103069995326,12cyclictest3176528-21ssh23:38:350
3103069995319,6cyclictest16850irq/134-800000022:08:030
3103069995319,6cyclictest16850irq/134-800000022:08:030
3103069995319,30cyclictest16850irq/134-800000000:17:050
3103069995317,5cyclictest131rcu_preempt00:08:220
3103079995231,10cyclictest37-21ksoftirqd/321:20:203
3103079995231,10cyclictest37-21ksoftirqd/321:20:203
3103076995234,13cyclictest275-21dbus-daemon21:30:002
3103076995220,14cyclictest275-21dbus-daemon21:40:002
310306999524,44cyclictest12-21ksoftirqd/019:53:270
3103069995217,6cyclictest16850irq/134-800000023:30:080
3103069995217,31cyclictest16850irq/134-800000021:52:050
3103079995117,22cyclictest37-21ksoftirqd/323:07:563
310307699511,46cyclictest1-21systemd19:15:012
3103076995114,5cyclictest131rcu_preempt00:25:002
3103076995111,5cyclictest131rcu_preempt21:15:012
3103076995111,5cyclictest131rcu_preempt21:15:012
3103069995115,31cyclictest16850irq/134-800000023:29:390
310306999511,44cyclictest131rcu_preempt20:31:430
3103079995018,21cyclictest37-21ksoftirqd/323:17:203
3103079995018,21cyclictest37-21ksoftirqd/322:16:113
3103079995018,21cyclictest37-21ksoftirqd/322:16:113
310307999501,30cyclictest361rcuc/319:50:023
310307699506,8cyclictest30-21ksoftirqd/200:36:452
3103076995034,12cyclictest3467602-21systemd-journal19:25:002
3103076995031,15cyclictest1-21systemd00:05:012
3103076995024,11cyclictest30-21ksoftirqd/223:25:012
3103076995024,11cyclictest30-21ksoftirqd/223:25:012
3103076995012,6cyclictest131rcu_preempt22:06:272
3103076995012,6cyclictest131rcu_preempt22:06:272
3103074995015,9cyclictest23-21ksoftirqd/121:35:011
3103074995015,9cyclictest23-21ksoftirqd/121:35:011
3103079994932,11cyclictest309-21in:imuxsock23:45:013
310307699498,6cyclictest131rcu_preempt19:55:022
3103076994935,10cyclictest30-21ksoftirqd/223:52:202
3103074994935,9cyclictest275-21dbus-daemon22:25:001
3103074994934,11cyclictest275-21dbus-daemon22:35:021
3103074994934,11cyclictest0-21swapper/123:40:011
3103074994922,12cyclictest23-21ksoftirqd/121:44:561
310306999496,5cyclictest131rcu_preempt19:29:270
310306999496,10cyclictest3106630-21munin-run20:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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