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2026-09-23 - 02:21

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Tue Sep 22, 2026 12:45:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113485599753,9cyclictest12-21ksoftirqd/012:00:010
113485599753,42cyclictest12-21ksoftirqd/011:15:030
113485599734,38cyclictest12-21ksoftirqd/009:30:010
1134855997114,29cyclictest131rcu_preempt10:08:240
1134868996757,7cyclictest37-21ksoftirqd/311:55:033
113485599653,11cyclictest121ksoftirqd/009:44:510
1134863996314,12cyclictest30-21ksoftirqd/211:55:002
1134863996310,5cyclictest131rcu_preempt11:19:592
113485599639,5cyclictest131rcu_preempt08:15:000
113485599636,30cyclictest12-21ksoftirqd/011:00:000
1134863996252,7cyclictest30-21ksoftirqd/210:15:032
1134863996252,7cyclictest30-21ksoftirqd/210:15:022
113485599623,6cyclictest121ksoftirqd/009:50:570
113485599623,6cyclictest121ksoftirqd/009:50:570
1134855996221,5cyclictest131rcu_preempt10:43:560
1134855996221,5cyclictest131rcu_preempt10:43:550
1134855996216,10cyclictest12-21ksoftirqd/009:20:000
1134855996214,6cyclictest131rcu_preempt07:20:020
113486399617,7cyclictest30-21ksoftirqd/209:20:022
1134863996110,5cyclictest131rcu_preempt10:55:022
1134863996110,5cyclictest131rcu_preempt10:55:012
113485599618,21cyclictest12-21ksoftirqd/009:47:370
113485599615,11cyclictest12-21ksoftirqd/008:10:010
113485599613,30cyclictest131rcu_preempt11:45:030
1134868996033,15cyclictest37-21ksoftirqd/309:45:393
113485599603,20cyclictest1164403-21unin-run10:00:010
1134855996031,13cyclictest1208938-21latency_hist11:35:020
1134855996031,13cyclictest1208938-21latency_hist11:35:020
1134855996027,29cyclictest151rcuc/010:19:530
1134855996027,29cyclictest151rcuc/010:19:530
113485599602,44cyclictest12-21ksoftirqd/010:02:380
1134855996012,5cyclictest131rcu_preempt11:40:010
1134863995912,6cyclictest131rcu_preempt09:24:322
1134863995911,6cyclictest131rcu_preempt08:49:592
113485599595,27cyclictest131rcu_preempt11:08:010
1134855995949,6cyclictest16950irq/224-800000009:10:030
1134855995949,6cyclictest16950irq/224-800000009:10:030
113485599593,5cyclictest131rcu_preempt12:25:380
1134855995932,12cyclictest1218067-21ssh11:54:220
113485599591,8cyclictest1181083-21latency_hist10:35:020
1134868995825,23cyclictest37-21ksoftirqd/309:32:243
1134868995811,6cyclictest131rcu_preempt12:40:023
1134863995850,5cyclictest30-21ksoftirqd/212:05:012
1134863995850,5cyclictest30-21ksoftirqd/212:05:012
1134863995834,7cyclictest1216050-21kworker/2:012:19:012
113485599586,29cyclictest12-21ksoftirqd/011:27:220
113485599583,9cyclictest12-21ksoftirqd/012:40:000
1134855995822,32cyclictest1190360-21sed10:55:020
1134855995822,32cyclictest1190360-21sed10:55:010
1134855995810,6cyclictest131rcu_preempt10:48:220
1134868995716,6cyclictest131rcu_preempt10:45:013
1134868995716,6cyclictest131rcu_preempt10:45:013
113486899571,5cyclictest131rcu_preempt10:55:013
113486899571,5cyclictest131rcu_preempt10:55:013
113486399576,6cyclictest131rcu_preempt10:00:002
113485599578,18cyclictest131rcu_preempt07:50:020
113485599578,18cyclictest131rcu_preempt07:50:010
113485599577,22cyclictest131rcu_preempt10:25:380
113485599572,11cyclictest12-21ksoftirqd/008:20:010
113486899568,10cyclictest37-21ksoftirqd/308:45:013
113486899568,10cyclictest37-21ksoftirqd/308:45:003
1134868995627,9cyclictest37-21ksoftirqd/311:20:013
113486899562,6cyclictest131rcu_preempt11:40:013
113486399568,5cyclictest131rcu_preempt07:10:022
1134863995611,6cyclictest131rcu_preempt09:30:012
1134863995611,5cyclictest131rcu_preempt09:37:032
113485599567,11cyclictest12-21ksoftirqd/012:05:020
113485599567,11cyclictest12-21ksoftirqd/012:05:020
113485599565,15cyclictest131rcu_preempt11:04:050
113485599564,13cyclictest309-21in:imuxsock07:40:000
113485599563,16cyclictest12-21ksoftirqd/008:49:590
1134855995625,15cyclictest1151664-21ssh09:32:370
1134855995621,31cyclictest12-21ksoftirqd/012:08:250
1134855995616,6cyclictest131rcu_preempt08:00:010
1134855995615,37cyclictest12-21ksoftirqd/012:33:310
113485599561,14cyclictest120-21kswapd012:20:000
1134868995531,8cyclictest37-21ksoftirqd/311:32:113
1134868995531,8cyclictest37-21ksoftirqd/311:32:103
113486899552,4cyclictest131rcu_preempt10:40:013
1134868995515,11cyclictest37-21ksoftirqd/310:30:013
113486399557,6cyclictest131rcu_preempt12:40:002
113486399555,7cyclictest131rcu_preempt09:40:052
1134863995511,9cyclictest131rcu_preempt11:15:012
1134863995510,6cyclictest131rcu_preempt11:00:002
1134855995514,5cyclictest131rcu_preempt12:20:540
1134855995514,36cyclictest131rcu_preempt09:36:340
113486899548,6cyclictest131rcu_preempt11:50:003
113486899544,10cyclictest37-21ksoftirqd/310:04:013
1134868995424,21cyclictest37-21ksoftirqd/311:03:543
113486399548,6cyclictest131rcu_preempt10:40:012
113486399548,4cyclictest131rcu_preempt11:03:452
113486399546,11cyclictest30-21ksoftirqd/211:32:502
113486399546,11cyclictest30-21ksoftirqd/211:32:502
1134863995422,6cyclictest131rcu_preempt12:06:072
113486399541,7cyclictest1211344-21systemctl11:40:002
1134863995414,6cyclictest131rcu_preempt08:30:002
113486399541,14cyclictest30-21ksoftirqd/209:14:182
1134858995413,24cyclictest0-21swapper/111:35:031
1134858995413,24cyclictest0-21swapper/111:35:021
113485599548,26cyclictest131rcu_preempt11:23:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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