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2026-01-15 - 19:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Thu Jan 15, 2026 12:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10805359911477,8cyclictest37-21ksoftirqd/311:20:033
1080529998013,40cyclictest131rcu_preempt09:55:011
108052499794,43cyclictest131rcu_preempt10:50:370
108052999762,3cyclictest131rcu_preempt07:25:021
1080524997615,40cyclictest12-21ksoftirqd/012:13:340
1080524997311,42cyclictest12-21ksoftirqd/010:03:010
1080524996927,37cyclictest12-21ksoftirqd/011:02:450
108052499687,44cyclictest131rcu_preempt08:35:020
1080524996827,21cyclictest12-21ksoftirqd/011:19:270
1080524996719,40cyclictest12-21ksoftirqd/012:33:300
1080524996610,6cyclictest131rcu_preempt10:00:010
1080524996610,6cyclictest131rcu_preempt10:00:000
1080524996543,18cyclictest12-21ksoftirqd/009:54:020
1080524996517,44cyclictest12-21ksoftirqd/011:21:420
1080524996419,41cyclictest12-21ksoftirqd/011:42:190
1080524996415,44cyclictest131rcu_preempt11:15:010
1080524996329,15cyclictest1132167-21latency_hist10:50:030
1080524996324,6cyclictest131rcu_preempt09:15:000
1080524996218,23cyclictest16850irq/134-800000009:25:010
1080524996018,37cyclictest16850irq/134-800000010:17:250
1080524995927,28cyclictest12-21ksoftirqd/010:41:100
1080524995926,15cyclictest12-21ksoftirqd/010:30:230
1080524995926,15cyclictest12-21ksoftirqd/010:30:220
1080524995918,22cyclictest16850irq/134-800000012:29:290
1080524995917,38cyclictest16850irq/134-800000012:08:020
1080535995842,10cyclictest3467602-21systemd-journal12:20:003
1080524995819,35cyclictest16850irq/134-800000011:52:230
1080524995819,35cyclictest16850irq/134-800000010:25:020
1080524995819,35cyclictest16850irq/134-800000009:30:390
1080524995819,34cyclictest16850irq/134-800000011:58:500
1080524995819,34cyclictest16850irq/134-800000011:31:070
1080524995817,37cyclictest12-21ksoftirqd/012:37:030
1080524995810,5cyclictest12-21ksoftirqd/009:15:580
1080531995712,6cyclictest131rcu_preempt10:05:012
1080531995710,6cyclictest131rcu_preempt12:25:002
1080524995727,4cyclictest12-21ksoftirqd/008:22:580
1080524995720,33cyclictest16850irq/134-800000012:18:260
1080524995719,34cyclictest16850irq/134-800000012:01:290
1080524995719,34cyclictest16850irq/134-800000012:01:290
1080524995719,34cyclictest16850irq/134-800000010:13:540
1080524995719,34cyclictest16850irq/134-800000009:48:260
1080524995719,34cyclictest16850irq/134-800000009:48:250
1080524995719,34cyclictest16850irq/134-800000009:25:580
1080524995719,33cyclictest16850irq/134-800000011:07:580
1080524995717,35cyclictest16850irq/134-800000011:25:510
1080524995717,35cyclictest16850irq/134-800000011:25:500
1080524995716,20cyclictest16850irq/134-800000010:29:170
108053199567,6cyclictest131rcu_preempt09:30:002
1080524995618,34cyclictest16850irq/134-800000011:37:270
1080524995618,34cyclictest16850irq/134-800000009:40:480
1080524995617,35cyclictest16850irq/134-800000010:35:100
1080524995617,34cyclictest16850irq/134-800000011:00:030
1080524995615,33cyclictest16850irq/134-800000009:10:010
1080524995615,31cyclictest16850irq/134-800000009:35:300
1080524995546,5cyclictest16950irq/224-800000009:00:000
1080524995540,11cyclictest3467602-21systemd-journal08:40:000
1080524995517,34cyclictest16850irq/134-800000012:22:070
1080524995516,21cyclictest16850irq/134-800000011:48:160
1080524995515,35cyclictest16850irq/134-800000010:06:380
108053199549,5cyclictest131rcu_preempt10:35:012
108053199549,5cyclictest131rcu_preempt10:35:012
1080531995418,9cyclictest30-21ksoftirqd/211:24:372
108052999541,5cyclictest131rcu_preempt11:40:011
1080531995323,11cyclictest30-21ksoftirqd/209:43:102
1080535995219,25cyclictest37-21ksoftirqd/311:45:023
108053199529,7cyclictest131rcu_preempt10:20:012
108053199529,6cyclictest131rcu_preempt09:09:592
108053199519,5cyclictest131rcu_preempt08:56:572
108053199518,5cyclictest131rcu_preempt12:09:592
1080531995111,6cyclictest131rcu_preempt10:00:012
1080531995111,6cyclictest131rcu_preempt10:00:002
1080524995141,7cyclictest12-21ksoftirqd/007:20:000
1080524995137,10cyclictest1083045-21run-parts08:00:000
1080535995031,15cyclictest275-21dbus-daemon09:20:023
108053199505,7cyclictest30-21ksoftirqd/212:31:272
108053199504,5cyclictest131rcu_preempt11:09:042
108053199504,5cyclictest131rcu_preempt09:39:242
1080531995035,12cyclictest275-21dbus-daemon11:00:012
108053199502,5cyclictest131rcu_preempt10:55:022
1080531995012,6cyclictest131rcu_preempt12:27:282
1080531995011,6cyclictest131rcu_preempt11:59:582
108052999505,8cyclictest23-21ksoftirqd/109:18:561
1080529995035,11cyclictest1-21systemd10:25:011
108053599491,6cyclictest131rcu_preempt12:10:013
108053199499,5cyclictest131rcu_preempt08:17:592
108053199496,9cyclictest1145740-21diskmemload11:20:032
108053199493,6cyclictest131rcu_preempt09:25:012
1080531994911,5cyclictest131rcu_preempt09:20:012
1080531994910,6cyclictest131rcu_preempt10:05:142
1080529994918,4cyclictest23-21ksoftirqd/109:00:001
1080524994920,17cyclictest131rcu_preempt07:10:030
1080524994920,17cyclictest131rcu_preempt07:10:020
1080524994919,19cyclictest12-21ksoftirqd/008:25:010
108053599484,4cyclictest131rcu_preempt12:22:593
1080535994815,14cyclictest37-21ksoftirqd/309:10:253
108053199489,5cyclictest131rcu_preempt12:20:002
108053199488,5cyclictest131rcu_preempt10:20:142
108053199488,5cyclictest131rcu_preempt09:54:062
108053199486,9cyclictest30-21ksoftirqd/210:46:232
108053199485,5cyclictest131rcu_preempt07:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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