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2026-05-14 - 18:49

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Thu May 14, 2026 12:45:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
55061799728,33cyclictest131rcu_preempt10:40:021
550622996514,10cyclictest30-21ksoftirqd/209:45:022
550615996526,34cyclictest578434-21ssh09:55:000
550615996330,15cyclictest648367-21ssh12:20:000
550615996318,28cyclictest12-21ksoftirqd/010:53:350
55062299625,22cyclictest583679-21ssh10:05:342
550615996217,26cyclictest12-21ksoftirqd/011:05:010
550615996214,44cyclictest12-21ksoftirqd/010:13:020
55062299618,14cyclictest30-21ksoftirqd/209:53:572
55062299616,20cyclictest0-21swapper/209:39:592
550622996116,8cyclictest30-21ksoftirqd/208:25:032
550622996112,9cyclictest30-21ksoftirqd/212:40:002
550615996139,4cyclictest16850irq/134-800000010:05:020
550615996135,22cyclictest12-21ksoftirqd/010:58:030
550615996112,40cyclictest12-21ksoftirqd/007:32:430
550615996111,45cyclictest12-21ksoftirqd/008:31:430
550615996033,23cyclictest602572-21kworker/u8:310:45:000
550615996017,26cyclictest12-21ksoftirqd/009:34:240
550615996014,4cyclictest12-21ksoftirqd/010:31:480
550622995919,11cyclictest30-21ksoftirqd/210:35:452
550622995912,8cyclictest30-21ksoftirqd/211:10:012
550615995928,15cyclictest598989-21ssh10:37:280
550615995922,32cyclictest6299721ssh11:41:290
55062299588,10cyclictest30-21ksoftirqd/211:31:452
550622995815,10cyclictest30-21ksoftirqd/209:12:342
550615995826,12cyclictest12-21ksoftirqd/009:55:270
550615995826,12cyclictest12-21ksoftirqd/009:55:260
550615995825,30cyclictest12-21ksoftirqd/011:08:210
55062299579,12cyclictest30-21ksoftirqd/212:29:182
55062299573,11cyclictest30-21ksoftirqd/211:51:532
550622995723,12cyclictest131rcu_preempt11:35:352
550622995712,8cyclictest30-21ksoftirqd/212:11:202
55061599574,42cyclictest12-21ksoftirqd/009:44:260
550615995728,12cyclictest562247-21ssh09:20:590
550615995717,30cyclictest131rcu_preempt11:30:000
55062299569,8cyclictest30-21ksoftirqd/210:33:522
55062299568,10cyclictest30-21ksoftirqd/210:50:022
55062299565,9cyclictest30-21ksoftirqd/212:15:522
55062299565,11cyclictest30-21ksoftirqd/211:00:002
550622995628,9cyclictest30-21ksoftirqd/210:03:112
550622995618,9cyclictest30-21ksoftirqd/208:19:592
550622995614,7cyclictest30-21ksoftirqd/210:20:042
550615995628,13cyclictest655560-21ssh12:34:480
550615995626,14cyclictest564300-21ssh09:25:170
550615995626,14cyclictest564300-21ssh09:25:160
550615995625,13cyclictest638779-21ssh12:00:010
55062299558,7cyclictest568876-21date09:35:022
55062299557,10cyclictest30-21ksoftirqd/211:57:502
55062299556,8cyclictest575238-21ssh09:48:112
55062299556,11cyclictest30-21ksoftirqd/210:41:382
55062299555,7cyclictest30-21ksoftirqd/211:24:322
55062299555,7cyclictest30-21ksoftirqd/211:24:322
550622995519,9cyclictest30-21ksoftirqd/212:06:382
550615995545,7cyclictest16850irq/134-800000010:30:010
550615995526,14cyclictest625055-21ssh11:31:120
55062299548,7cyclictest630849-21ssh11:43:272
55062299548,15cyclictest594055-21ssh10:27:072
55062299545,12cyclictest30-21ksoftirqd/207:40:022
55062299544,11cyclictest30-21ksoftirqd/211:20:002
55062299544,11cyclictest30-21ksoftirqd/207:25:022
550622995424,21cyclictest275-21dbus-daemon09:05:012
550622995410,9cyclictest30-21ksoftirqd/209:26:572
550622995410,9cyclictest30-21ksoftirqd/209:26:572
550617995425,10cyclictest23-21ksoftirqd/110:20:011
550615995442,8cyclictest0-21swapper/009:40:000
550615995427,12cyclictest603158-21ssh10:45:560
550615995426,12cyclictest629006-21ssh11:39:470
55062299533,14cyclictest30-21ksoftirqd/210:17:322
550622995320,9cyclictest131rcu_preempt07:55:002
550622995315,9cyclictest0-21swapper/211:15:012
550622995311,5cyclictest0-21swapper/212:05:012
550617995342,8cyclictest23-21ksoftirqd/107:50:021
550617995342,8cyclictest23-21ksoftirqd/107:50:011
550617995315,22cyclictest638816-21ssh12:00:021
550615995324,13cyclictest575249-21ssh09:48:120
550615995323,13cyclictest633195-21ssh11:48:210
55062599525,4cyclictest131rcu_preempt09:15:123
55062599525,4cyclictest131rcu_preempt09:15:123
550625995212,5cyclictest131rcu_preempt12:39:433
55062299528,9cyclictest30-21ksoftirqd/211:05:012
55062299524,14cyclictest30-21ksoftirqd/211:48:082
55062299524,10cyclictest30-21ksoftirqd/209:18:152
55062299524,10cyclictest30-21ksoftirqd/209:18:142
55062299523,10cyclictest30-21ksoftirqd/208:35:002
550622995211,9cyclictest30-21ksoftirqd/209:59:052
550622995211,9cyclictest30-21ksoftirqd/209:59:052
550615995224,12cyclictest560689-21ssh09:18:090
550615995224,12cyclictest560689-21ssh09:18:090
55062299518,8cyclictest30-21ksoftirqd/207:10:022
55062299515,6cyclictest30-21ksoftirqd/210:55:022
55062299514,9cyclictest30-21ksoftirqd/211:27:432
55062299513,6cyclictest30-21ksoftirqd/209:09:592
55061599512,44cyclictest653254-21ssh12:30:000
550615995124,12cyclictest656056-21ssh12:35:210
55062299506,8cyclictest30-21ksoftirqd/209:22:112
55062299502,9cyclictest30-21ksoftirqd/212:32:522
55062299502,10cyclictest30-21ksoftirqd/212:22:402
550617995013,19cyclictest23-21ksoftirqd/112:20:031
550615995035,10cyclictest0-21swapper/008:15:010
550615995028,18cyclictest634391-21ssh11:50:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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