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2026-02-04 - 15:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Wed Feb 04, 2026 12:45:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3125882999489,3cyclictest0-21swapper/007:25:020
312588299943,3cyclictest131rcu_preempt08:05:010
3125882999086,2cyclictest0-21swapper/007:30:010
312588299871,82cyclictest0-21swapper/008:30:020
312588299851,6cyclictest150-21pr/ttyS209:00:010
3125882998113,31cyclictest12-21ksoftirqd/011:55:000
3125882997621,22cyclictest3174502-21ssh10:43:340
3125882997621,22cyclictest3174502-21ssh10:43:330
312588999728,46cyclictest30-21ksoftirqd/209:20:022
3125882996965,2cyclictest0-21swapper/007:35:030
312589699685,9cyclictest37-21ksoftirqd/312:40:013
312589699681,54cyclictest3200365-21ssh11:40:023
3125882996831,9cyclictest12-21ksoftirqd/010:10:000
312588299671,33cyclictest0-21swapper/008:10:010
3125882996624,12cyclictest3154877-21date10:00:020
3125885996424,12cyclictest275-21dbus-daemon11:30:001
3125885996420,14cyclictest3189868-21sh11:17:151
3125885996418,15cyclictest3170304-21sh10:34:191
3125882996425,3cyclictest0-21swapper/010:18:570
3125885996316,12cyclictest0-21swapper/112:17:331
3125885996316,12cyclictest0-21swapper/112:17:321
3125885996314,14cyclictest3136024-21ssh09:18:311
3125885996220,10cyclictest3200916-21rm11:41:211
3125885996216,14cyclictest3142596-21sh09:33:021
312588599617,19cyclictest3180175-21ssh10:55:501
3125885996116,9cyclictest23-21ksoftirqd/111:07:291
3125885996110,15cyclictest3223381-21ssh12:31:021
312588599607,18cyclictest3170903-21ssh10:35:111
3125885996016,9cyclictest23-21ksoftirqd/111:02:561
3125885996016,9cyclictest23-21ksoftirqd/111:02:551
3125885995916,14cyclictest3165815-21sh10:24:201
3125885995915,14cyclictest3215602-21sh12:14:071
3125882995914,10cyclictest12-21ksoftirqd/011:20:020
312589699585,10cyclictest37-21ksoftirqd/312:29:093
312589699585,10cyclictest37-21ksoftirqd/312:29:083
3125885995823,29cyclictest3128933-21cron08:10:001
3125885995810,14cyclictest3144635-21ssh09:37:311
3125882995820,33cyclictest16850irq/134-800000011:32:280
3125882995815,9cyclictest12-21ksoftirqd/009:34:040
3125896995718,13cyclictest37-21ksoftirqd/310:53:133
3125889995748,6cyclictest3119643-21kworker/2:112:04:342
312588599576,13cyclictest3222275-21ssh12:28:501
312588599576,13cyclictest3222275-21ssh12:28:491
312588599575,22cyclictest3212255-21sh12:06:271
312588599575,17cyclictest3166574-21ssh10:25:421
3125885995715,11cyclictest0-21swapper/110:07:591
3125885995713,13cyclictest0-21swapper/109:59:101
3125885995713,10cyclictest0-21swapper/111:11:321
3125882995720,4cyclictest3127670-21munin-run07:45:010
3125882995714,37cyclictest151rcuc/012:17:320
3125882995714,37cyclictest151rcuc/012:17:310
3125882995710,10cyclictest12-21ksoftirqd/009:16:350
3125896995613,12cyclictest37-21ksoftirqd/310:06:513
3125885995614,11cyclictest0-21swapper/112:00:411
3125885995612,13cyclictest3208714-21diskmemload11:58:531
3125885995612,13cyclictest3208714-21diskmemload11:58:521
3125885995611,14cyclictest0-21swapper/109:27:041
3125885995611,14cyclictest0-21swapper/109:27:031
3125882995629,11cyclictest3214925-21ssh12:12:300
3125882995627,14cyclictest3180957-21ssh10:57:540
3125882995621,32cyclictest16850irq/134-800000010:34:380
3125882995618,33cyclictest16850irq/134-800000012:00:200
3125882995618,14cyclictest12-21ksoftirqd/009:29:080
3125882995618,14cyclictest12-21ksoftirqd/009:29:070
3125882995614,8cyclictest12-21ksoftirqd/009:40:360
3125882995614,21cyclictest0-21swapper/011:57:340
3125882995614,21cyclictest0-21swapper/011:57:340
3125896995546,6cyclictest361rcuc/310:39:173
3125896995545,6cyclictest361rcuc/312:19:263
3125896995545,6cyclictest361rcuc/312:19:253
3125896995545,6cyclictest361rcuc/312:06:063
3125896995544,8cyclictest361rcuc/309:15:043
3125889995547,5cyclictest3138998-21kworker/2:309:54:492
3125889995545,5cyclictest3119643-21kworker/2:110:55:022
3125889995543,9cyclictest3159287-21kworker/2:210:50:012
3125889995532,7cyclictest3119643-21kworker/2:111:15:292
3125882995527,12cyclictest3177286-21ssh10:49:490
3125882995518,7cyclictest16850irq/134-800000010:53:490
312589699546,8cyclictest37-21ksoftirqd/312:21:573
312589699545,10cyclictest37-21ksoftirqd/310:30:333
3125896995444,7cyclictest361rcuc/310:02:243
3125889995446,5cyclictest3119643-21kworker/2:108:05:022
3125889995444,6cyclictest3159287-21kworker/2:212:11:022
3125889995443,5cyclictest3159287-21kworker/2:211:50:292
3125885995443,9cyclictest3177261-21ssh10:49:461
3125885995442,9cyclictest3178242-21ssh10:51:351
3125885995413,13cyclictest3147358-21diskmemload09:43:361
3125885995413,11cyclictest0-21swapper/111:30:301
3125882995419,6cyclictest16850irq/134-800000010:26:330
3125882995418,6cyclictest16850irq/134-800000010:23:550
3125882995418,32cyclictest16850irq/134-800000009:45:470
3125882995418,32cyclictest16850irq/134-800000009:45:460
3125882995416,33cyclictest16850irq/134-800000010:35:130
3125882995414,8cyclictest151rcuc/012:26:380
3125882995414,8cyclictest151rcuc/012:26:380
3125882995413,10cyclictest12-21ksoftirqd/011:43:040
312589699536,7cyclictest37-21ksoftirqd/311:08:323
312589699535,9cyclictest37-21ksoftirqd/310:17:363
312589699534,10cyclictest37-21ksoftirqd/311:49:063
312589699534,10cyclictest37-21ksoftirqd/311:49:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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