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2026-02-05 - 16:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Thu Feb 05, 2026 00:45:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32848849911317,51cyclictest131rcu_preempt22:55:000
32848979910313,61cyclictest3271115-21munin-node23:00:033
32848979910313,61cyclictest3271115-21munin-node23:00:023
32848939910113,83cyclictest3350283-21ssh23:20:022
328488499766,8cyclictest121ksoftirqd/022:10:010
328488499762,71cyclictest0-21swapper/022:05:020
3284884997232,36cyclictest12-21ksoftirqd/023:25:000
328488499683,9cyclictest121ksoftirqd/021:40:010
328488499683,9cyclictest121ksoftirqd/021:40:010
328488499681,9cyclictest121ksoftirqd/023:50:030
328488499681,42cyclictest131rcu_preempt00:04:030
3284889996748,9cyclictest23-21ksoftirqd/119:50:001
3284889996615,12cyclictest23-21ksoftirqd/120:00:001
328489399655,45cyclictest3318320-21ssh22:10:022
3284889996513,17cyclictest23-21ksoftirqd/121:50:021
3284884996511,5cyclictest131rcu_preempt22:15:000
3284884996511,5cyclictest131rcu_preempt22:15:000
328488499649,44cyclictest131rcu_preempt23:20:030
328488499643,43cyclictest131rcu_preempt00:06:450
3284884996430,12cyclictest12-21ksoftirqd/021:43:040
328488499642,9cyclictest121ksoftirqd/023:35:030
328488499642,9cyclictest121ksoftirqd/023:35:020
328488499641,4cyclictest131rcu_preempt23:49:130
3284889996310,5cyclictest131rcu_preempt21:45:001
328488499635,30cyclictest131rcu_preempt21:20:470
3284884996315,5cyclictest131rcu_preempt20:00:000
328489799622,21cyclictest37-21ksoftirqd/322:00:023
328489399614,11cyclictest30-21ksoftirqd/223:00:002
328489399614,11cyclictest30-21ksoftirqd/223:00:002
3284893996120,6cyclictest131rcu_preempt23:10:322
3284884996116,15cyclictest131rcu_preempt21:34:250
3284884996113,5cyclictest131rcu_preempt23:39:590
328488999606,9cyclictest23-21ksoftirqd/122:02:081
3284889996017,11cyclictest23-21ksoftirqd/123:56:061
3284884996055,3cyclictest0-21swapper/019:30:020
3284884996055,3cyclictest0-21swapper/019:30:020
3284884996049,6cyclictest12-21ksoftirqd/000:15:020
3284884996032,14cyclictest3331803-21ssh22:39:490
3284889995914,9cyclictest23-21ksoftirqd/123:25:011
3284889995913,5cyclictest131rcu_preempt23:47:401
328489399585,8cyclictest30-21ksoftirqd/200:40:032
328488999587,13cyclictest23-21ksoftirqd/100:40:021
328488999585,11cyclictest23-21ksoftirqd/122:43:271
3284889995816,6cyclictest131rcu_preempt21:19:581
3284889995814,6cyclictest131rcu_preempt21:15:001
3284889995812,6cyclictest131rcu_preempt19:55:001
3284884995848,8cyclictest151rcuc/020:50:020
3284893995711,6cyclictest131rcu_preempt23:35:022
3284893995711,6cyclictest131rcu_preempt23:35:022
328488999577,9cyclictest23-21ksoftirqd/122:15:001
328488999577,9cyclictest23-21ksoftirqd/122:15:001
328488999576,12cyclictest23-21ksoftirqd/120:20:011
328488999575,8cyclictest23-21ksoftirqd/122:50:011
328488999575,10cyclictest23-21ksoftirqd/121:35:021
328488999575,10cyclictest23-21ksoftirqd/121:35:021
328488999574,10cyclictest23-21ksoftirqd/123:44:341
328488999574,10cyclictest23-21ksoftirqd/100:30:091
3284889995718,9cyclictest23-21ksoftirqd/121:10:011
3284889995712,6cyclictest131rcu_preempt00:20:011
3284889995710,6cyclictest131rcu_preempt23:10:001
328488499574,37cyclictest12-21ksoftirqd/021:56:570
328488499573,5cyclictest131rcu_preempt23:10:010
3284884995710,6cyclictest131rcu_preempt23:00:010
3284884995710,6cyclictest131rcu_preempt23:00:010
3284884995710,6cyclictest131rcu_preempt20:25:020
3284893995633,18cyclictest275-21dbus-daemon20:45:002
328488999569,6cyclictest131rcu_preempt00:05:011
328488999568,10cyclictest23-21ksoftirqd/121:25:001
328488999567,12cyclictest23-21ksoftirqd/122:32:071
328488999567,12cyclictest23-21ksoftirqd/122:32:061
3284889995610,5cyclictest131rcu_preempt22:38:321
3284884995627,13cyclictest3378202-21ssh00:21:580
3284884995626,14cyclictest3325126-21ssh22:25:020
3284884995623,15cyclictest3309396-21ssh21:50:020
3284884995617,34cyclictest16850irq/134-800000021:15:570
328488999557,8cyclictest23-21ksoftirqd/121:30:011
328488999557,8cyclictest23-21ksoftirqd/121:30:001
328488999556,10cyclictest23-21ksoftirqd/100:21:481
328488999554,12cyclictest23-21ksoftirqd/123:20:001
3284889995514,5cyclictest131rcu_preempt20:15:021
3284889995511,6cyclictest131rcu_preempt22:58:121
3284889995511,6cyclictest131rcu_preempt22:58:121
3284889995511,6cyclictest131rcu_preempt22:18:561
3284889995510,5cyclictest131rcu_preempt23:03:321
3284884995543,10cyclictest151rcuc/022:35:030
3284884995543,10cyclictest151rcuc/022:35:020
3284884995512,5cyclictest131rcu_preempt00:38:470
3284897995435,13cyclictest3467602-21systemd-journal21:20:003
3284893995446,4cyclictest3285093-21kworker/2:022:30:002
328488999548,13cyclictest23-21ksoftirqd/119:40:001
328488999546,7cyclictest131rcu_preempt23:35:021
328488999546,7cyclictest131rcu_preempt23:35:021
328488999545,9cyclictest23-21ksoftirqd/120:25:001
328488999544,14cyclictest23-21ksoftirqd/120:30:001
3284889995415,5cyclictest131rcu_preempt21:32:261
3284889995414,6cyclictest131rcu_preempt00:15:011
3284889995411,6cyclictest131rcu_preempt19:15:021
3284889995411,6cyclictest131rcu_preempt19:15:021
3284889995410,5cyclictest131rcu_preempt23:13:321
3284884995415,6cyclictest131rcu_preempt23:30:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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