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2026-02-19 - 21:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Thu Feb 19, 2026 12:45:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
369680399896,18cyclictest131rcu_preempt07:35:023
3696792997975,2cyclictest0-21swapper/011:10:030
3696801997332,16cyclictest3467602-21systemd-journal10:25:002
3696792997369,2cyclictest0-21swapper/007:35:030
369680199728,57cyclictest3467602-21systemd-journal11:45:012
3696792997249,19cyclictest16850irq/134-800000009:40:000
3696801997139,10cyclictest3696753-21kworker/2:209:25:452
369679299709,17cyclictest3697241-21modprobe07:20:000
369679299709,17cyclictest3697241-21modprobe07:20:000
3696792996662,2cyclictest0-21swapper/008:50:020
3696803996523,9cyclictest37-21ksoftirqd/311:40:023
369679299651,41cyclictest131rcu_preempt11:31:010
369679299651,3cyclictest0-21swapper/007:15:020
3696792996512,31cyclictest131rcu_preempt12:35:030
3696801996125,21cyclictest30-21ksoftirqd/209:55:012
3696792996116,40cyclictest16850irq/134-800000009:30:010
3696792996115,42cyclictest12-21ksoftirqd/007:30:020
369680199603,4cyclictest131rcu_preempt12:00:022
369680399597,11cyclictest37-21ksoftirqd/310:10:293
369680399594,7cyclictest3734929-21latency_hist10:20:023
3696803995941,15cyclictest1-21systemd09:45:013
3696803995920,7cyclictest37-21ksoftirqd/312:35:013
3696803995914,5cyclictest131rcu_preempt10:10:023
3696801995941,8cyclictest3753167-21kworker/2:211:30:022
369679299599,34cyclictest19350irq/34-mmc110:05:020
3696792995918,37cyclictest16850irq/134-800000011:30:020
3696792995917,38cyclictest12-21ksoftirqd/010:20:020
3696803995819,7cyclictest37-21ksoftirqd/307:20:003
3696803995819,7cyclictest37-21ksoftirqd/307:20:003
3696801995849,5cyclictest3753167-21kworker/2:211:50:022
369679299585,34cyclictest131rcu_preempt10:55:180
3696792995829,13cyclictest3746570-21ssh10:45:080
3696803995718,8cyclictest37-21ksoftirqd/308:05:003
369679299579,10cyclictest12-21ksoftirqd/009:46:240
369679299577,5cyclictest131rcu_preempt11:37:050
3696792995724,15cyclictest131rcu_preempt11:52:240
3696792995715,8cyclictest12-21ksoftirqd/012:10:020
3696792995715,8cyclictest12-21ksoftirqd/012:10:020
369679299571,40cyclictest3796719-21ssh12:35:060
369679299571,40cyclictest3796719-21ssh12:35:060
3696792995620,31cyclictest16850irq/134-800000011:45:190
3696792995617,7cyclictest12-21ksoftirqd/011:15:000
3696792995611,6cyclictest131rcu_preempt10:45:010
3696792995611,6cyclictest131rcu_preempt10:45:010
369680399552,5cyclictest131rcu_preempt12:25:013
369680399551,14cyclictest37-21ksoftirqd/310:00:003
3696801995547,5cyclictest3696753-21kworker/2:209:24:142
3696792995527,13cyclictest3722247-21ssh09:52:050
3696792995520,31cyclictest16850irq/134-800000011:03:060
3696792995519,32cyclictest16850irq/134-800000012:27:230
369680399549,5cyclictest131rcu_preempt07:15:003
369680399545,6cyclictest131rcu_preempt11:00:043
369680399542,7cyclictest37-21ksoftirqd/309:25:023
3696803995417,6cyclictest131rcu_preempt10:25:003
369680399541,6cyclictest131rcu_preempt10:40:003
3696803995415,9cyclictest37-21ksoftirqd/309:35:013
3696803995413,7cyclictest131rcu_preempt11:35:023
3696803995413,6cyclictest131rcu_preempt09:52:163
3696803995412,7cyclictest131rcu_preempt11:15:023
3696803995411,5cyclictest131rcu_preempt08:20:003
3696803995410,5cyclictest131rcu_preempt09:20:013
3696801995446,5cyclictest3773681-21kworker/2:012:20:092
3696797995410,6cyclictest131rcu_preempt08:17:001
369679299549,9cyclictest131rcu_preempt09:00:000
369679299548,5cyclictest131rcu_preempt09:20:030
3696792995419,31cyclictest16850irq/134-800000012:04:310
3696792995419,31cyclictest16850irq/134-800000010:36:100
3696792995419,31cyclictest16850irq/134-800000009:10:420
3696792995419,30cyclictest16850irq/134-800000010:07:570
3696792995418,31cyclictest16850irq/134-800000012:20:550
3696792995418,31cyclictest16850irq/134-800000012:19:330
3696792995418,31cyclictest16850irq/134-800000012:19:330
3696792995418,31cyclictest16850irq/134-800000010:30:330
3696792995418,31cyclictest16850irq/134-800000010:24:110
3696792995417,33cyclictest16850irq/134-800000010:11:050
3696792995417,32cyclictest16850irq/134-800000011:55:260
369679299541,5cyclictest131rcu_preempt11:45:000
3696792995411,3cyclictest12-21ksoftirqd/009:44:490
369680399538,5cyclictest131rcu_preempt09:30:023
369680399538,4cyclictest131rcu_preempt10:04:273
369680399537,10cyclictest37-21ksoftirqd/311:30:013
3696803995310,5cyclictest131rcu_preempt10:50:003
3696801995345,5cyclictest3773681-21kworker/2:012:37:122
3696801995345,5cyclictest3773681-21kworker/2:012:37:122
3696801995343,6cyclictest3744063-21kworker/2:010:58:522
3696797995311,6cyclictest131rcu_preempt12:05:011
3696792995319,30cyclictest16850irq/134-800000011:22:070
3696792995317,32cyclictest16850irq/134-800000009:57:540
3696792995317,31cyclictest16850irq/134-800000009:30:090
369680399528,5cyclictest131rcu_preempt10:55:023
369680399527,6cyclictest131rcu_preempt11:22:283
369680399523,5cyclictest131rcu_preempt10:35:023
3696803995211,6cyclictest131rcu_preempt08:15:013
3696801995244,5cyclictest3773681-21kworker/2:012:19:202
3696801995244,5cyclictest3773681-21kworker/2:012:19:192
3696801995243,6cyclictest3773681-21kworker/2:012:13:282
3696801995243,5cyclictest3701162-21kworker/2:110:10:132
369680199523,3cyclictest131rcu_preempt09:40:032
3696792995234,13cyclictest3698828-21unin-run07:50:010
3696792995234,13cyclictest3698828-21unin-run07:50:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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