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2025-11-24 - 06:25

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Mon Nov 24, 2025 00:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
401196399961,3cyclictest0-21swapper/023:15:020
4011963999283,4cyclictest0-21swapper/021:15:010
4011968997122,10cyclictest23-21ksoftirqd/120:55:011
401196899677,22cyclictest4012846-21cut19:25:031
401197799642,10cyclictest37-21ksoftirqd/321:50:003
401197399634,6cyclictest131rcu_preempt22:15:002
4011973996216,12cyclictest30-21ksoftirqd/200:00:002
4011973996216,12cyclictest30-21ksoftirqd/200:00:002
401196899629,15cyclictest4026459-21cut23:45:021
4011968996216,8cyclictest23-21ksoftirqd/100:10:001
4011968996215,8cyclictest23-21ksoftirqd/123:50:011
4011968996116,9cyclictest23-21ksoftirqd/119:10:011
4011968996115,10cyclictest23-21ksoftirqd/120:25:021
401197799608,15cyclictest37-21ksoftirqd/300:00:003
401197799608,15cyclictest37-21ksoftirqd/300:00:003
4011968996017,9cyclictest23-21ksoftirqd/122:35:001
4011968996017,9cyclictest23-21ksoftirqd/122:35:001
4011968996010,17cyclictest4024832-21latency_hist23:15:021
4011977995911,5cyclictest131rcu_preempt20:55:013
4011968995917,9cyclictest23-21ksoftirqd/121:00:001
4011968995917,9cyclictest23-21ksoftirqd/121:00:001
4011968995915,9cyclictest23-21ksoftirqd/120:50:021
4011968995915,10cyclictest23-21ksoftirqd/119:55:021
401197399583,7cyclictest30-21ksoftirqd/200:25:002
401196899588,16cyclictest4027797-21latency_hist00:15:021
401196899588,16cyclictest4027797-21latency_hist00:15:021
401196899588,13cyclictest4013907-21date19:45:021
401196899588,13cyclictest4013907-21date19:45:011
4011968995818,7cyclictest23-21ksoftirqd/120:35:011
4011968995810,14cyclictest4020860-21wc22:00:011
4011977995711,6cyclictest131rcu_preempt21:10:013
4011968995739,14cyclictest4027280-21sshd00:04:371
4011968995716,9cyclictest23-21ksoftirqd/120:20:021
401197399569,5cyclictest131rcu_preempt22:05:012
4011968995638,13cyclictest1-21systemd20:45:011
4011968995638,13cyclictest1-21systemd20:45:011
4011968995615,9cyclictest23-21ksoftirqd/119:15:001
401197799556,7cyclictest37-21ksoftirqd/322:56:593
4011977995535,15cyclictest1-21systemd20:20:003
4011973995544,8cyclictest30-21ksoftirqd/221:15:012
4011973995510,5cyclictest131rcu_preempt22:45:002
4011968995511,14cyclictest4027063-21munin-run00:00:011
4011968995511,14cyclictest4027063-21munin-run00:00:011
4011963995549,3cyclictest0-21swapper/023:30:020
401197399542,5cyclictest131rcu_preempt23:25:022
401197399542,5cyclictest131rcu_preempt23:25:022
401196899547,14cyclictest4018841-21sed21:20:021
401196899546,14cyclictest4022802-21apt-helper22:39:231
4011977995320,12cyclictest37-21ksoftirqd/323:35:273
4011977995315,9cyclictest131rcu_preempt20:30:003
4011977995315,9cyclictest131rcu_preempt20:30:003
401197399538,5cyclictest131rcu_preempt20:40:012
4011973995312,5cyclictest131rcu_preempt23:30:012
401196899536,16cyclictest4028410-21sed00:25:011
401196899534,15cyclictest4026123-21latency_hist23:40:021
4011968995313,8cyclictest23-21ksoftirqd/100:20:011
401197799525,8cyclictest37-21ksoftirqd/300:05:003
4011977995224,19cyclictest37-21ksoftirqd/319:15:023
4011977995215,5cyclictest131rcu_preempt23:15:023
401197399524,5cyclictest30-21ksoftirqd/220:10:002
401196899523,17cyclictest0-21swapper/119:50:011
401196399525,34cyclictest4011966-21latency_hist19:10:000
401197799518,5cyclictest131rcu_preempt20:15:023
401197799516,9cyclictest37-21ksoftirqd/323:18:233
401197799513,9cyclictest37-21ksoftirqd/319:20:023
401197799513,6cyclictest131rcu_preempt21:25:023
4011977995111,5cyclictest131rcu_preempt19:30:003
4011973995141,8cyclictest291rcuc/219:15:012
4011973995112,5cyclictest131rcu_preempt22:40:002
401196899515,13cyclictest4020975-21modprobe22:00:021
4011963995143,4cyclictest16950irq/224-800000000:00:010
4011963995143,4cyclictest16950irq/224-800000000:00:010
4011977995015,6cyclictest131rcu_preempt19:45:013
4011977995015,6cyclictest131rcu_preempt19:45:003
4011977995010,5cyclictest131rcu_preempt20:10:003
401197399504,12cyclictest30-21ksoftirqd/221:00:012
401197399504,12cyclictest30-21ksoftirqd/221:00:012
401197399502,11cyclictest30-21ksoftirqd/219:30:002
4011973995011,6cyclictest131rcu_preempt22:55:002
4011973995011,5cyclictest131rcu_preempt00:15:372
4011973995010,6cyclictest131rcu_preempt23:15:002
401196899506,16cyclictest1-21systemd21:24:191
401197799499,5cyclictest131rcu_preempt00:15:003
401197799499,5cyclictest131rcu_preempt00:15:003
401197799498,5cyclictest131rcu_preempt19:25:023
401197799497,8cyclictest37-21ksoftirqd/320:50:023
4011977994914,6cyclictest37-21ksoftirqd/319:55:023
4011977994914,6cyclictest131rcu_preempt22:00:023
4011977994912,5cyclictest131rcu_preempt23:10:023
4011977994911,5cyclictest131rcu_preempt23:45:023
401197799491,11cyclictest37-21ksoftirqd/323:55:013
401197399499,6cyclictest131rcu_preempt00:15:022
401197399499,6cyclictest131rcu_preempt00:15:022
401197399498,7cyclictest131rcu_preempt21:05:022
401197399498,7cyclictest131rcu_preempt21:05:022
401197399494,6cyclictest131rcu_preempt23:50:012
401197399493,10cyclictest30-21ksoftirqd/223:05:002
401197399491,5cyclictest131rcu_preempt21:50:012
401197399491,5cyclictest131rcu_preempt00:40:012
4011973994915,6cyclictest131rcu_preempt00:05:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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