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2026-01-27 - 11:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackeslot3s.osadl.org (updated Tue Jan 27, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48768999702,49cyclictest12-21ksoftirqd/023:31:000
487696996923,12cyclictest1-21systemd23:20:012
48768999685,9cyclictest12-21ksoftirqd/023:45:020
48768999684,45cyclictest0-21swapper/021:45:140
487689996614,8cyclictest12-21ksoftirqd/021:44:590
487696996522,12cyclictest30-21ksoftirqd/222:58:302
487696996522,12cyclictest30-21ksoftirqd/222:58:302
487696996428,5cyclictest580578-21sh00:21:032
487689996416,8cyclictest12-21ksoftirqd/019:40:010
487689996411,16cyclictest561889-21sed23:40:020
487699996242,14cyclictest1-21systemd22:35:013
48769999622,41cyclictest493840-21diskmemload23:45:023
487689996222,11cyclictest12-21ksoftirqd/023:25:400
487689996212,7cyclictest12-21ksoftirqd/022:19:590
487696996024,11cyclictest30-21ksoftirqd/222:05:042
48769699601,12cyclictest525368-21sshd22:19:222
487689996016,8cyclictest12-21ksoftirqd/000:03:550
487689996016,7cyclictest12-21ksoftirqd/022:35:010
487689996014,8cyclictest12-21ksoftirqd/022:30:000
48769999597,6cyclictest131rcu_preempt21:40:013
48769999597,6cyclictest131rcu_preempt21:40:013
487696995924,9cyclictest30-21ksoftirqd/200:25:592
487689995941,14cyclictest1-21systemd21:20:000
487689995914,10cyclictest12-21ksoftirqd/021:52:550
48768999591,31cyclictest493840-21diskmemload21:21:500
487699995835,17cyclictest3467602-21systemd-journal19:55:013
487696995827,9cyclictest30-21ksoftirqd/222:45:012
48768999588,7cyclictest12-21ksoftirqd/021:12:080
48768999588,13cyclictest12-21ksoftirqd/021:35:010
487689995820,19cyclictest516592-21ssh22:00:020
487689995816,7cyclictest131rcu_preempt22:05:010
487689995813,9cyclictest12-21ksoftirqd/022:15:010
487689995745,8cyclictest16850irq/134-800000023:00:000
487689995745,8cyclictest16850irq/134-800000022:59:590
487689995726,4cyclictest0-21swapper/000:30:030
487689995715,9cyclictest0-21swapper/000:40:010
487689995715,10cyclictest0-21swapper/023:59:590
487689995715,10cyclictest0-21swapper/000:00:000
48768999571,27cyclictest12-21ksoftirqd/022:39:410
487689995712,6cyclictest12-21ksoftirqd/000:10:010
48769999566,47cyclictest493840-21diskmemload23:05:013
48769699562,9cyclictest568273-21modprobe23:54:212
48768999565,9cyclictest12-21ksoftirqd/000:11:490
48768999565,13cyclictest12-21ksoftirqd/022:41:100
48768999564,17cyclictest544970-21ssh23:02:440
487689995626,12cyclictest555095-21ssh23:25:030
487689995626,12cyclictest555095-21ssh23:25:030
48768999562,22cyclictest502625-21ssh21:29:120
487699995537,13cyclictest1-21systemd00:05:013
487699995510,6cyclictest131rcu_preempt23:38:583
487696995523,10cyclictest30-21ksoftirqd/222:47:202
48768999559,9cyclictest12-21ksoftirqd/023:50:380
48768999558,7cyclictest566218-21ssh23:50:010
487689995513,8cyclictest12-21ksoftirqd/023:10:010
487696995436,13cyclictest1-21systemd21:45:012
48768999549,9cyclictest12-21ksoftirqd/020:05:000
487689995446,5cyclictest151rcuc/019:29:210
487689995445,6cyclictest12-21ksoftirqd/020:58:220
48768999542,6cyclictest12-21ksoftirqd/000:16:550
487689995417,32cyclictest16850irq/134-800000022:54:130
487689995410,10cyclictest552718-21munin-run23:20:010
48769999539,6cyclictest131rcu_preempt22:05:013
48769499532,39cyclictest580025-21sh00:20:021
48769499531,4cyclictest131rcu_preempt23:25:021
48769499531,4cyclictest131rcu_preempt23:25:011
48768999536,11cyclictest12-21ksoftirqd/023:13:530
487689995321,3cyclictest0-21swapper/000:21:240
487689995317,32cyclictest492769-21sshd20:45:210
487699995211,5cyclictest131rcu_preempt00:18:323
487689995215,29cyclictest16850irq/134-800000022:49:180
487689995213,5cyclictest520439-21rm22:08:220
48769999519,6cyclictest131rcu_preempt21:50:263
48769999518,6cyclictest131rcu_preempt22:50:013
48769999513,11cyclictest37-21ksoftirqd/321:15:023
487694995135,12cyclictest1-21systemd22:20:011
487694995130,16cyclictest275-21dbus-daemon22:10:011
48768999516,10cyclictest12-21ksoftirqd/019:15:000
48768999515,8cyclictest12-21ksoftirqd/019:55:030
48768999515,10cyclictest12-21ksoftirqd/020:40:020
487689995125,3cyclictest0-21swapper/000:26:330
487699995022,11cyclictest37-21ksoftirqd/300:25:563
487699995013,6cyclictest131rcu_preempt23:35:023
487699995011,7cyclictest131rcu_preempt23:20:003
487699995011,6cyclictest131rcu_preempt00:09:483
487699995011,18cyclictest131rcu_preempt00:00:023
487699995011,18cyclictest131rcu_preempt00:00:013
48768999507,34cyclictest3467602-21systemd-journal21:40:010
48768999507,34cyclictest3467602-21systemd-journal21:40:010
48768999506,12cyclictest12-21ksoftirqd/022:24:340
48768999503,10cyclictest12-21ksoftirqd/019:20:020
48769999497,7cyclictest37-21ksoftirqd/319:20:013
48769999497,11cyclictest37-21ksoftirqd/322:45:013
48769999495,6cyclictest131rcu_preempt21:10:013
48769999495,5cyclictest131rcu_preempt22:59:503
48769999495,5cyclictest131rcu_preempt22:59:493
48769999494,5cyclictest131rcu_preempt22:39:143
487699994941,5cyclictest37-21ksoftirqd/323:51:323
48769999492,9cyclictest37-21ksoftirqd/321:40:573
48769999492,10cyclictest37-21ksoftirqd/320:45:003
487699994913,5cyclictest131rcu_preempt20:30:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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