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2026-03-06 - 08:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot3s.osadl.org (updated Fri Mar 06, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4069938991051,3cyclictest131rcu_preempt20:45:020
4069938997635,20cyclictest4155132-21ssh00:06:140
4069938997329,27cyclictest131rcu_preempt22:31:560
4069938997132,19cyclictest131rcu_preempt23:40:020
4069938997132,19cyclictest131rcu_preempt23:40:020
406993899712,39cyclictest131rcu_preempt22:49:340
406993899654,39cyclictest131rcu_preempt23:19:260
406993899654,39cyclictest131rcu_preempt23:19:250
406993899652,3cyclictest131rcu_preempt21:57:060
406993899641,39cyclictest131rcu_preempt22:39:480
406993899632,4cyclictest131rcu_preempt23:04:390
4069948996232,9cyclictest4069727-21kworker/2:221:50:012
4069938996225,7cyclictest12-21ksoftirqd/023:50:020
4069938996222,4cyclictest131rcu_preempt00:19:400
4069938996129,15cyclictest131rcu_preempt00:23:430
4069938996129,15cyclictest131rcu_preempt00:23:430
406993899603,4cyclictest131rcu_preempt22:58:110
4069938996020,3cyclictest131rcu_preempt21:25:390
4069938996013,42cyclictest12-21ksoftirqd/000:35:260
406994399598,12cyclictest23-21ksoftirqd/120:35:011
406993899599,5cyclictest12-21ksoftirqd/023:20:260
4069938995831,12cyclictest4081632-21ssh21:21:440
4069938995831,12cyclictest4081632-21ssh21:21:440
4069938995825,29cyclictest12-21ksoftirqd/021:14:580
4069938995825,29cyclictest12-21ksoftirqd/021:14:580
4069938995820,33cyclictest16850irq/134-800000023:10:000
4069938995819,34cyclictest16850irq/134-800000023:35:030
4069948995741,7cyclictest4141093-21kworker/2:200:29:282
4069948995728,21cyclictest4141093-21kworker/2:200:05:052
4069948995728,21cyclictest4141093-21kworker/2:200:05:042
4069938995728,11cyclictest131rcu_preempt22:06:230
4069948995639,7cyclictest4107480-21kworker/2:123:35:002
4069938995628,3cyclictest131rcu_preempt22:13:540
4069938995628,12cyclictest4108178-21ssh22:21:110
4069938995628,12cyclictest4108178-21ssh22:21:110
4069938995619,20cyclictest16850irq/134-800000000:30:230
406993899561,36cyclictest131rcu_preempt21:46:010
4069948995547,5cyclictest4069727-21kworker/2:221:26:062
4069948995538,8cyclictest4098553-21kworker/2:022:05:022
4069948995527,18cyclictest4062519-21kworker/2:121:16:172
406994399555,3cyclictest131rcu_preempt21:35:021
4069938995520,31cyclictest16850irq/134-800000023:25:230
4069938995520,31cyclictest16850irq/134-800000023:25:230
4069938995518,32cyclictest16850irq/134-800000022:15:470
4069938995518,32cyclictest16850irq/134-800000021:30:160
4069938995515,14cyclictest16850irq/134-800000000:00:020
4069948995445,5cyclictest4154505-21kworker/2:300:18:182
4069948995439,8cyclictest4062519-21kworker/2:121:11:182
4069948995439,8cyclictest4062519-21kworker/2:121:11:182
4069948995428,9cyclictest4069727-21kworker/2:221:42:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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