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2026-01-20 - 01:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Jan 19, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1312033994138,2cyclictest1378713-21kworker/3:0+pm09:10:343
1312026992926,2cyclictest0-21swapper/107:54:591
1312033992825,2cyclictest0-21swapper/309:05:013
1312031992814,1cyclictest191rcu_preempt07:45:002
131203399254,2cyclictest1593947-21irqcore11:45:173
131203399251,20cyclictest1634010-21apt-get12:25:153
1312031992521,2cyclictest1613769-21apt-get12:05:122
131203199251,22cyclictest1618844-21apt-get12:10:132
1312023992521,2cyclictest1470868-21apt-get09:45:140
131202399251,22cyclictest1543314-21tr10:55:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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