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2026-01-28 - 11:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Wed Jan 28, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
583350994037,2cyclictest608843-21fwupd19:32:550
58335099331,22cyclictest665698-21cron20:30:010
58335099321,22cyclictest919950-21/usr/sbin/munin00:35:130
583352993121,8cyclictest919948-21sshd00:35:131
58335299310,3cyclictest655161-21/usr/sbin/munin20:20:001
58335099311,2cyclictest718813-21apt-get21:20:110
58335299301,19cyclictest0-21swapper/100:15:181
58335299291,20cyclictest599132-21apt-get19:25:131
58335299290,3cyclictest698092-21apt-get21:00:021
583350992917,10cyclictest650038-21cron20:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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