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2026-02-20 - 18:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Feb 20, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
483495993836,1cyclictest2670913-21kworker/0:2+pm08:36:190
48349799322,3cyclictest768820-21apt-get11:50:121
48349799311,19cyclictest615778-21apt-get09:20:111
48349799291,20cyclictest753617-21apt-get11:35:111
48349799291,20cyclictest753617-21apt-get11:35:111
483501992825,1cyclictest434656-21kworker/2:2+pm08:36:192
48349799280,20cyclictest0-21swapper/111:55:131
48350499272,22cyclictest789997-21apt-get12:10:103
48350499272,22cyclictest519539-21apt-get07:45:113
48349799270,26cyclictest0-21swapper/110:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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