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2026-02-17 - 18:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Tue Feb 17, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3664183993816,16cyclictest3709762-21sh07:55:010
366418899321,3cyclictest3898635-21apt-get11:00:122
366418399321,2cyclictest0-21swapper/008:25:170
366418399320,21cyclictest3898638-21taskset11:00:100
366418399311,26cyclictest3807465-21apt-get09:30:120
366418399311,11cyclictest0-21swapper/012:30:160
366418899300,2cyclictest3705461-21sed07:50:172
366418899300,23cyclictest3710936-21ps07:55:162
366418399300,2cyclictest3944324-21cron11:45:000
366418399300,2cyclictest3787235-21ps09:10:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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