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2026-02-16 - 02:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Feb 15, 2026 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
164616799330,30cyclictest1973528-21cron12:30:012
1646167992921,6cyclictest0-21swapper/207:55:162
1646167992919,8cyclictest0-21swapper/210:20:002
164616799290,27cyclictest1892033-21cron11:10:012
164616799290,27cyclictest1892033-21cron11:10:012
164616799290,26cyclictest0-21swapper/210:15:002
1646167992819,7cyclictest0-21swapper/208:55:112
164616799281,26cyclictest1897127-21cron11:15:002
164616799280,26cyclictest1708031-21irqcore08:10:152
164616799280,25cyclictest1763039-21chrt09:05:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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