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2026-02-27 - 21:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Feb 27, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133939699331,21cyclictest1451689-21awk09:00:013
1339390993212,2cyclictest1544153-21ls10:29:591
1339396992724,2cyclictest491ktimers/308:35:003
133939699252,22cyclictest1462966-21apt-get09:10:133
133939699252,21cyclictest1431745-21apt-get08:40:113
1339396992520,3cyclictest1569763-21apt-get10:55:113
1339396992520,3cyclictest1559633-21apt-get10:45:123
133939699251,3cyclictest0-21swapper/309:15:103
133939699251,22cyclictest1375020-21apt-get07:45:123
133939699251,21cyclictest1600514-21apt-get11:25:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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