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2026-02-11 - 10:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Wed Feb 11, 2026 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236984799331,3cyclictest2573682-21cron22:30:002
236984799331,3cyclictest2527868-21cron21:45:002
236984799310,3cyclictest2696357-21sort00:30:152
236984799310,3cyclictest2644502-21cron23:40:002
2369847993019,10cyclictest2477204-21idleruntime-cro20:55:002
236984799301,3cyclictest2700944-21apt-get00:35:132
236984799301,2cyclictest0-21swapper/223:10:122
236984799300,2cyclictest2606316-21grep23:00:152
236984799291,3cyclictest0-21swapper/200:25:132
236984799291,2cyclictest0-21swapper/220:40:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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