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2026-01-23 - 01:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Thu Jan 22, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2898990993026,3cyclictest3009745-21seq20:55:213
2898981992917,1cyclictest2919393-21apt-get19:30:110
289898899271,22cyclictest3041417-21apt-get21:30:112
2898981992724,2cyclictest3035674-21fwupd21:20:550
289898899261,21cyclictest3015947-21apt-get21:05:122
289898899261,21cyclictest2904247-21apt-get19:15:112
2898988992520,3cyclictest261-21systemd-journal22:15:012
2898988992520,2cyclictest3231918-21apt-get00:35:142
289898899251,3cyclictest2914339-21apt-get19:25:122
289898899251,20cyclictest3103209-21apt-get22:30:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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