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2026-01-12 - 23:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Jan 12, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
45780799380,1cyclictest0-21swapper/108:40:001
457807993720,6cyclictest559951-21apt-get08:50:121
45780799301,22cyclictest707682-21cron11:15:001
45780799291,3cyclictest728192-21apt-get11:35:111
45780799291,21cyclictest463082-21apt-get07:15:121
45780799281,2cyclictest0-21swapper/107:45:131
45780799281,24cyclictest0-21swapper/108:15:111
45780799281,20cyclictest733671-21apt-get11:40:111
45780799281,1cyclictest0-21swapper/111:45:131
45780799280,26cyclictest0-21swapper/107:50:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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