You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-25 - 16:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Wed Feb 25, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3491176993936,2cyclictest3618197-21fwupd09:10:421
349118399319,2cyclictest0-21swapper/308:30:013
3491173992823,3cyclictest0-21swapper/010:35:010
349118199270,23cyclictest743-21ntpd07:50:122
349118399260,6cyclictest3659183-21idleruntime-cro09:55:003
349118399260,6cyclictest3659183-21idleruntime-cro09:55:003
349117699262,20cyclictest3726715-21apt-get11:00:141
3491183992520,3cyclictest3716084-21apt-get10:50:113
349118399251,21cyclictest3613747-21apt-get09:10:123
349118399251,21cyclictest0-21swapper/312:20:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional