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2026-02-14 - 14:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Feb 14, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3294423994138,2cyclictest3466843-21fwupd22:00:023
329441399270,25cyclictest0-21swapper/022:00:020
329442399261,22cyclictest3584678-21apt-get23:55:143
329442399261,22cyclictest3579628-21apt-get23:50:123
329442399261,22cyclictest3569513-21apt-get23:40:113
329441899261,5cyclictest3534001-21seq23:05:132
329441599261,21cyclictest3559378-21apt-get23:30:111
329441599261,21cyclictest3559378-21apt-get23:30:101
329441599260,24cyclictest3564450-21taskset23:35:121
3294413992623,2cyclictest3589515-21idleruntime-cro00:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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