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2026-01-30 - 09:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Jan 30, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2668767994038,1cyclictest2474282-21kworker/0:2+pm19:11:020
266876799350,5cyclictest2920401-21cron23:15:000
266876799350,33cyclictest2878922-21cron22:35:000
2668777993431,2cyclictest2673440-21fwupd19:11:013
266876799330,3cyclictest2843415-21cron22:00:000
266876799321,29cyclictest2853547-21cron22:09:590
266876799311,20cyclictest1-21systemd22:50:000
266876799311,11cyclictest1-21systemd21:40:010
266876799310,29cyclictest2766037-21sh20:45:000
266876799310,20cyclictest261-21systemd-journal20:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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