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2026-02-07 - 23:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Feb 07, 2026 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
197370899304,23cyclictest702-21runrttasks12:35:152
197371099287,1cyclictest2019698-21munin-run07:55:003
197371099285,3cyclictest1974413-21sort07:10:153
197371099284,21cyclictest0-21swapper/312:35:153
1973710992824,2cyclictest2157742-21latency_hist10:10:013
197371099272,21cyclictest2224448-21apt-get11:15:123
197370899275,2cyclictest2094628-21ntpq09:05:222
197370899274,21cyclictest2019678-21cron07:55:002
1973708992723,2cyclictest2157744-21latency_hist10:10:012
1973704992718,2cyclictest191rcu_preempt07:30:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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