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2026-02-13 - 19:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Feb 13, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
384830099310,20cyclictest3904141-21apt-get08:05:100
3848303992826,1cyclictest3919003-21idleruntime-cro08:20:001
3848310992724,2cyclictest4041034-21fwupd10:16:553
384830399261,21cyclictest4179133-21apt-get12:35:131
384830099261,5cyclictest4092511-21cron11:10:000
384830099261,2cyclictest0-21swapper/010:16:560
384830899251,4cyclictest4072095-21chrt10:50:122
384830899251,3cyclictest4006205-21apt-get09:45:112
3848308992511,13cyclictest0-21swapper/209:40:002
384830099252,3cyclictest3919277-21apt-get08:20:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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