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2026-01-15 - 20:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Thu Jan 15, 2026 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1440952994118,16cyclictest261-21systemd-journal09:20:003
1440952994118,16cyclictest261-21systemd-journal09:20:003
144093899331,3cyclictest1456869-21tr07:25:150
144093899321,29cyclictest1634424-21apt-get10:20:110
1440952993019,9cyclictest1456863-21ps07:25:153
144095299290,27cyclictest1686784-21cut11:10:173
144093899292,3cyclictest1706543-21apt-get11:30:110
1440938992917,11cyclictest1563505-21tr09:10:140
144093899291,3cyclictest1628966-21apt-get10:15:120
144093899291,3cyclictest1481657-21apt-get07:50:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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