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2026-02-27 - 13:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Feb 27, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186998899321,3cyclictest2069194-21cron22:25:002
186998899321,3cyclictest2069194-21cron22:25:002
186998899310,2cyclictest2141088-21sed23:35:162
186998899301,2cyclictest0-21swapper/219:45:222
186998899290,28cyclictest2085098-21cut22:40:152
186998899281,26cyclictest0-21swapper/219:50:182
186998899270,3cyclictest2116426-21cat23:10:162
186998899270,26cyclictest2083435-21ntpq22:35:202
186998899261,21cyclictest2019051-21apt-get21:35:102
186998899260,20cyclictest0-21swapper/221:15:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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