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2026-01-26 - 22:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Jan 26, 2026 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218411399271,23cyclictest2266725-21apt-get08:30:122
2184109992724,2cyclictest0-21swapper/108:10:011
2184115992619,5cyclictest261-21systemd-journal11:34:593
2184113992622,3cyclictest0-21swapper/208:50:012
218411399261,22cyclictest2220205-21apt-get07:45:132
218411399261,21cyclictest2481275-21apt-get12:00:112
218410999264,20cyclictest311ktimers/110:05:201
218410799262,21cyclictest2271826-21apt-get08:35:130
218411599252,3cyclictest2225716-21apt-get07:50:133
2184115992520,3cyclictest2194787-21apt-get07:20:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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