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2026-01-25 - 09:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Jan 25, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3804740994845,2cyclictest3983066-21fwupd22:01:561
3804743993019,9cyclictest3952552-21cron21:35:002
380474399301,26cyclictest4112230-21irqcore00:10:172
380474399300,25cyclictest3851662-21grep19:55:162
380474399281,26cyclictest0-21swapper/222:00:002
380474399281,25cyclictest4131352-21ntpq00:25:252
380474399280,27cyclictest4085645-21cron23:44:592
380474399280,25cyclictest0-21swapper/200:00:132
380474999272,21cyclictest3962936-21apt-get21:45:113
380474399271,25cyclictest4120687-21ntpq00:15:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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