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2026-01-18 - 11:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Jan 18, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2936196993218,5cyclictest3069651-21idleruntime-cro21:24:591
293619699311,23cyclictest3049375-21idleruntime-cro21:05:001
293619699301,19cyclictest0-21swapper/119:25:121
2936196992921,7cyclictest1-21systemd23:35:001
2936196992818,2cyclictest3207981-21cron23:40:011
2936196992818,2cyclictest3197881-21munin-run23:30:001
2936196992818,2cyclictest3177188-21cron23:10:011
293619699280,19cyclictest0-21swapper/119:10:121
293619699272,22cyclictest3115849-21apt-get22:10:111
2936196992717,2cyclictest3156620-21munin-run22:50:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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