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2026-02-19 - 10:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Thu Feb 19, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2064985994845,2cyclictest2232892-21fwupd21:51:011
206499199272,21cyclictest2345953-21apt-get23:45:133
206498599271,21cyclictest2243669-21apt-get22:05:111
206498899261,21cyclictest2361286-21apt-get00:00:112
206498899261,21cyclictest2065200-21apt-get19:10:112
206498899261,21cyclictest0-21swapper/200:30:102
2064991992520,3cyclictest2310434-21apt-get23:10:113
206498899251,4cyclictest2285072-21seq22:45:132
206498899251,22cyclictest2264115-21cron22:24:592
206498899250,21cyclictest0-21swapper/223:15:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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