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2026-02-09 - 00:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Feb 08, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
920258993227,3cyclictest1226487-21ls12:09:590
92026699300,2cyclictest1236623-21awk12:20:002
92026699261,5cyclictest261-21systemd-journal07:24:592
92025899261,5cyclictest1058597-21cron09:25:000
92025899261,21cyclictest1079184-21apt-get09:45:120
920268992518,5cyclictest1089786-21irqcore09:55:153
92026899251,20cyclictest0-21swapper/311:15:123
92026699252,3cyclictest1063973-21apt-get09:30:102
92026699251,21cyclictest987578-21apt-get08:15:122
92026699251,20cyclictest1094322-21apt-get10:00:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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