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2026-02-20 - 06:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Feb 20, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1009936995351,1cyclictest1172964-21fwupd21:48:021
1009933994442,1cyclictest1137634-21kworker/0:2+pm21:48:030
100993699301,5cyclictest1020471-21cron19:19:591
100993699271,23cyclictest1086913-21apt-get20:25:111
100994399262,21cyclictest1260706-21apt-get23:15:133
1009943992621,3cyclictest1209835-21apt-get22:25:123
1009936992621,3cyclictest1158240-21apt-get21:35:121
100994399251,22cyclictest1301033-21ls23:55:003
100993699252,3cyclictest1230249-21apt-get22:45:121
100993699251,22cyclictest1311233-21cron00:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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