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2026-02-19 - 23:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Thu Feb 19, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1534485993423,4cyclictest1838085-21sshd12:05:173
153448599272,21cyclictest1621828-21apt-get08:35:123
153448599271,21cyclictest1560453-21apt-get07:35:113
153448599261,21cyclictest1826519-21apt-get11:55:123
153448599261,21cyclictest1544821-21apt-get07:20:123
1534478992624,1cyclictest301rcuc/111:55:181
153448599251,22cyclictest1765327-21apt-get10:55:113
153448599251,21cyclictest1811332-21apt-get11:40:113
153448599251,21cyclictest1698571-21apt-get09:50:093
1534482992520,3cyclictest1846732-21apt-get12:15:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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