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2026-02-07 - 11:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Feb 07, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
252393299321,21cyclictest2610621-21apt-get20:35:133
252393299320,3cyclictest2549909-21seq19:35:113
2523932993118,5cyclictest2759392-21tr23:00:173
252393299301,2cyclictest2590334-21apt-get20:15:123
252393299281,3cyclictest0-21swapper/320:45:123
252393299281,23cyclictest2580248-21apt-get20:05:113
252393299281,20cyclictest0-21swapper/320:20:133
252393299271,20cyclictest0-21swapper/323:55:103
252393299270,2cyclictest2836298-21apt-get00:20:123
252393299270,1cyclictest0-21swapper/321:30:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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