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2026-01-28 - 17:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Wed Jan 28, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63655993230,1cyclictest257023-21kworker/0:2+pm12:00:240
6366599270,25cyclictest232231-21chrt09:55:123
6366299272,21cyclictest94274-21apt-get07:40:122
6366299272,21cyclictest89219-21apt-get07:35:102
6366599261,22cyclictest0-21swapper/309:55:003
6366599261,21cyclictest333836-21apt-get11:35:093
6366599261,21cyclictest206462-21apt-get09:30:113
6366099262,21cyclictest74058-21apt-get07:20:131
63655992622,3cyclictest61650irq/133-enp0s29f1:rx-011:00:120
6365599262,22cyclictest354007-21apt-get11:55:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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