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2026-02-03 - 09:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Tue Feb 03, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2567557992826,1cyclictest2633018-21kworker/0:1+pm20:53:360
256755999271,24cyclictest2613056-21cron19:55:001
2567567992620,2cyclictest2852377-21apt-get23:50:123
256756799261,22cyclictest2791609-21apt-get22:50:123
256756499262,21cyclictest2730315-21apt-get21:50:102
2567564992620,3cyclictest2720199-21apt-get21:40:112
2567564992619,3cyclictest2883230-21apt-get00:20:122
256755999262,4cyclictest2867993-21apt-get00:05:101
256755999262,4cyclictest2704904-21apt-get21:25:141
256755999262,22cyclictest2710016-21apt-get21:30:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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