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2026-02-09 - 13:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Feb 09, 2026 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36453799272,21cyclictest676693-21apt-get00:15:130
364537992715,3cyclictest554308-21cron22:14:590
36454999261,21cyclictest472256-21apt-get20:55:123
36454799261,21cyclictest610344-21apt-get23:10:122
36454299262,20cyclictest467203-21apt-get20:50:101
364537992621,3cyclictest405746-21idleruntime-cro19:50:000
36454999252,2cyclictest411521-21apt-get19:55:123
36454999251,21cyclictest457075-21apt-get20:40:133
36454999251,21cyclictest457075-21apt-get20:40:123
36454799251,22cyclictest676420-21ls00:15:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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