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2026-03-05 - 15:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Thu Mar 05, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3716197994844,2cyclictest3888949-21fwupd21:59:012
371619399341,24cyclictest702-21runrttasks00:30:101
371619399331,3cyclictest0-21swapper/121:10:001
371619399321,21cyclictest3966361-21grep23:15:161
371619399301,3cyclictest3976000-21apt-get23:25:091
371619399291,20cyclictest0-21swapper/120:55:121
371619799272,21cyclictest3782577-21apt-get20:15:132
3716193992717,8cyclictest3920242-21irqcore22:30:151
371619399270,24cyclictest0-21swapper/119:15:121
3716197992621,3cyclictest3940519-21apt-get22:50:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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