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2026-02-10 - 02:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Feb 09, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4011065992723,3cyclictest4159733-21sh09:40:002
401106199271,22cyclictest125489-21apt-get12:15:121
401106799261,22cyclictest53309-21apt-get11:05:143
401106599262,3cyclictest4160000-21apt-get09:40:122
4011065992620,4cyclictest68916-21apt-get11:20:112
401105899260,24cyclictest4098745-21sshd08:35:150
401106799252,2cyclictest4072962-21apt-get08:10:123
401106599257,9cyclictest12183-21basename10:25:002
401106599252,21cyclictest37721-21apt-get10:50:122
401106599251,22cyclictest4118949-21runrttasks08:55:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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