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2026-02-02 - 09:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Feb 02, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
366925399331,4cyclictest3982738-21irqcore00:25:173
366925399331,3cyclictest3684416-21cron19:24:593
366925399330,22cyclictest3804391-21sort21:20:163
366925399300,2cyclictest3992873-21irqcore00:35:163
3669253992921,6cyclictest3751463-21apt-get20:30:133
366925399281,2cyclictest3951863-21apt-get23:55:133
366925399280,2cyclictest64-21kcompactd021:50:133
366925399280,2cyclictest0-21swapper/321:45:123
366925399272,21cyclictest3839789-21apt-get22:05:123
366925399270,2cyclictest0-21swapper/320:45:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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