You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-24 - 02:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Jan 23, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130584899320,21cyclictest1407592-21idleruntime-cro08:49:591
130584899300,21cyclictest1494493-21awk10:15:011
130584899292,3cyclictest1428488-21apt-get09:10:111
130584899291,21cyclictest1484408-21awk10:05:001
130584899291,19cyclictest0-21swapper/107:50:121
1305848992820,6cyclictest1438645-21apt-get09:20:121
130584899281,2cyclictest1443724-21apt-get09:25:121
130584899272,21cyclictest1539605-21apt-get11:25:121
1305848992719,6cyclictest1418339-21apt-get09:00:021
130584899270,24cyclictest1378022-21sort08:20:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional