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2026-02-10 - 10:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Tue Feb 10, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3463906993111,19cyclictest3591475-21grep21:15:163
3463903992617,2cyclictest191rcu_preempt20:50:002
346389699261,22cyclictest3707749-21apt-get23:10:120
346390699251,21cyclictest3717837-21apt-get23:20:133
3463903992521,3cyclictest3702696-21apt-get23:05:132
346390399251,4cyclictest3742922-21cron23:45:002
346390399251,22cyclictest3697640-21apt-get23:00:132
346390399251,21cyclictest3529810-21apt-get20:15:122
3463901992521,3cyclictest18050irq/130-nvme0q219:45:001
346390199251,21cyclictest3666921-21apt-get22:30:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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