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2026-02-08 - 12:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Feb 08, 2026 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1442976993118,11cyclictest1611402-21apt-get21:55:111
144297699301,21cyclictest1672172-21apt-get22:55:131
144297699300,2cyclictest1627058-21tr22:10:151
1442976992926,2cyclictest1763834-21idleruntime-cro00:25:001
1442976992819,6cyclictest1651914-21apt-get22:35:131
1442976992818,8cyclictest0-21swapper/100:05:001
144297699280,26cyclictest1748643-21cron00:09:591
1442976992717,3cyclictest1621494-21apt-get22:05:121
144297699271,22cyclictest1580566-21apt-get21:25:101
144297699271,1cyclictest1667117-21apt-get22:50:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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