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2026-03-01 - 02:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Feb 28, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23832099341,23cyclictest406912-21/usr/sbin/munin09:50:190
238320993218,2cyclictest330641-21apt-get08:40:110
23832099311,21cyclictest545272-21apt-get12:10:090
238320992819,2cyclictest371740-21apt-get09:20:130
238323992724,2cyclictest0-21swapper/109:50:121
238320992717,2cyclictest458792-21apt-get10:45:100
23832099261,3cyclictest550283-21apt-get12:15:110
23833099251,21cyclictest248715-21apt-get07:20:133
23832699252,21cyclictest479424-21apt-get11:05:102
23832399252,21cyclictest530070-21apt-get11:55:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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