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2026-02-15 - 02:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Feb 14, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
274920099312,20cyclictest3041775-21apt-get11:55:113
274920099311,21cyclictest2800512-21apt-get08:00:133
2749200993019,2cyclictest2949022-21irqcore10:25:163
2749200993019,2cyclictest0-21swapper/308:10:123
274920099290,3cyclictest2983897-21apt-config11:00:013
274920099290,21cyclictest2754266-21dpkg07:15:013
274920099261,22cyclictest2973840-21apt-get10:50:123
274919699262,21cyclictest2765069-21apt-get07:25:122
274919699261,22cyclictest2805540-21apt-get08:05:122
274919299262,21cyclictest2775222-21apt-get07:35:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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