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2026-02-21 - 15:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Feb 21, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3603874993530,3cyclictest3754640-21kthreadcore09:35:183
3603872992924,3cyclictest3614375-21sh07:20:002
360386799297,2cyclictest0-21swapper/107:50:001
360386799282,21cyclictest3650133-21apt-get07:55:121
360386799272,21cyclictest3936810-21apt-get12:35:141
3603867992719,6cyclictest3670353-21taskset08:15:121
360387299262,20cyclictest3634870-21apt-get07:40:132
360386799262,3cyclictest3921575-21apt-get12:20:111
360386799262,3cyclictest3798238-21apt-get10:20:121
360386799262,3cyclictest3726473-21apt-get09:10:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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