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2026-01-27 - 22:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Tue Jan 27, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1110587993633,2cyclictest1273409-21fwupd09:47:012
111058999261,21cyclictest1197394-21apt-get08:35:143
1110582992623,2cyclictest1442589-21apt-config12:35:001
111058299262,21cyclictest1136139-21apt-get07:35:121
111058299261,22cyclictest1151349-21apt-get07:50:131
111058299261,22cyclictest1141218-21apt-get07:40:131
111058299261,21cyclictest1361008-21apt-get11:15:111
111058799252,3cyclictest1366056-21apt-get11:20:122
111058799252,2cyclictest1422554-21apt-get12:15:122
111058799250,23cyclictest1436581-21modprobe12:25:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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