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2026-01-25 - 15:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Jan 25, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3283912993735,1cyclictest74-1kworker/2:1H+kblockd10:24:272
3283909993431,2cyclictest0-21swapper/111:35:001
3283909993228,2cyclictest3482277-21fwupd10:24:261
328391299319,20cyclictest0-21swapper/209:10:162
3283917992612,4cyclictest3605053-21apt-key12:25:003
328391799261,21cyclictest3548657-21apt-get11:30:133
328391799261,21cyclictest3325047-21apt-get07:50:113
328391299261,21cyclictest3396244-21apt-get09:00:142
3283912992611,8cyclictest3299479-21basename07:24:592
3283909992621,3cyclictest3431621-21apt-get09:35:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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