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2026-03-01 - 14:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Mar 01, 2026 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
385668999291,2cyclictest3912825-21http21:15:000
385669599261,22cyclictest3870566-21apt-get19:45:102
385669599261,21cyclictest0-21swapper/221:30:112
3856692992612,2cyclictest3862650-21awk19:20:001
385669299261,21cyclictest4051483-21apt-get23:30:121
385670099251,21cyclictest3876907-21apt-get20:00:123
385669599252,21cyclictest3864214-21apt-get19:30:122
385669599251,22cyclictest4087781-21apt-get00:05:122
385669299252,20cyclictest4046429-21apt-get23:25:121
385669299251,21cyclictest4092812-21apt-get00:10:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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