You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-02 - 14:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Mar 02, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2709220993936,2cyclictest3015268-21fwupd00:08:563
2709209993329,2cyclictest2919457-21apt-get22:35:130
2709220992925,2cyclictest0-21swapper/322:45:153
2709209992926,2cyclictest2724342-21turbostat.cron19:25:000
270921299272,21cyclictest2842300-21apt-get21:20:111
270920999271,22cyclictest2724602-21apt-get19:25:130
270921899261,21cyclictest2765099-21apt-get20:05:142
270920999262,22cyclictest2837242-21apt-get21:15:100
270920999262,21cyclictest2914403-21apt-get22:30:120
270920999261,22cyclictest2760021-21apt-get20:00:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional