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2026-02-22 - 16:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Feb 22, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2495246993026,2cyclictest2668199-21idleruntime-cro09:59:591
249524899260,22cyclictest3871586-21snmpd09:35:132
249524699261,21cyclictest0-21swapper/111:45:111
2495252992521,3cyclictest2802224-21sshd12:10:173
249525299251,21cyclictest2495460-21apt-get07:10:123
249524899252,21cyclictest2775573-21apt-get11:45:112
2495248992521,3cyclictest0-21swapper/207:15:182
2495248992520,3cyclictest2755167-21munin-run11:25:002
2495248992520,3cyclictest2622541-21apt-get09:15:132
249524699252,20cyclictest2536063-21apt-get07:50:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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