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2026-01-24 - 15:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Jan 24, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
702540995145,4cyclictest758988-21fwupd20:03:453
702540993218,6cyclictest713004-21cron19:19:593
70254099310,3cyclictest1018941-21unin-run00:20:013
70254099301,2cyclictest978578-21apt-get23:40:113
70254099300,20cyclictest784507-21systemd-run20:30:013
70253699303,18cyclictest759124-21munin-run20:05:002
70254099290,21cyclictest973551-21runrttasks23:35:103
702540992817,2cyclictest0-21swapper/323:50:103
702540992815,2cyclictest768539-21seq20:10:223
70254099271,22cyclictest968519-21apt-get23:30:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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