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2026-01-17 - 10:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sat Jan 17, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
402354199319,21cyclictest0-21swapper/100:20:151
402354699282,22cyclictest4069738-21apt-get19:55:122
402354699272,21cyclictest99796-21apt-get23:35:132
402354699272,21cyclictest151337-21apt-get00:25:102
402353899272,21cyclictest4110672-21apt-get20:35:110
402354899261,21cyclictest84606-21apt-get23:20:133
402354699262,21cyclictest33640-21apt-get22:30:122
402354199262,21cyclictest4161353-21apt-get21:25:111
402354199260,20cyclictest4161092-21munin-run21:25:001
402354699252,3cyclictest79528-21apt-get23:15:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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