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2026-01-16 - 22:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Fri Jan 16, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
387581994542,2cyclictest423452-21fwupd07:44:252
38757499310,29cyclictest696497-21ps12:15:150
38757899301,21cyclictest525312-21ntpq09:20:201
38757899301,19cyclictest567467-21apt-get10:05:111
38757899300,21cyclictest552727-21cut09:50:151
38757899291,20cyclictest638365-21apt-get11:15:121
38757899290,3cyclictest402777-21basename07:24:591
387578992819,8cyclictest413010-21cat07:35:001
38757899281,20cyclictest572522-21apt-get10:10:101
38757899280,20cyclictest484874-21dpkg08:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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