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2026-02-16 - 22:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Feb 16, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
55294399272,21cyclictest844776-21apt-get11:55:112
552942992724,2cyclictest0-21swapper/112:15:151
55294299272,22cyclictest768105-21apt-get10:40:111
55294299272,22cyclictest670680-21apt-get09:05:121
55294299262,21cyclictest650444-21apt-get08:45:121
55294299262,21cyclictest594894-21apt-get07:50:131
55294599251,21cyclictest763050-21apt-get10:35:103
552943992521,3cyclictest514-21in:imuxsock10:04:592
552943992518,5cyclictest594898-21taskset07:50:132
55294399251,22cyclictest613973-21ntpq08:05:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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