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2026-01-26 - 10:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Mon Jan 26, 2026 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2720346993111,1cyclictest3025691-21apt-key00:10:001
2720346992623,2cyclictest514-21in:imuxsock20:35:011
272034699261,21cyclictest2898729-21apt-get22:05:121
272034699261,21cyclictest0-21swapper/119:20:141
272035599251,20cyclictest2990276-21apt-get23:35:133
2720351992519,3cyclictest3041683-21apt-get00:25:142
272035199251,21cyclictest2847722-21apt-get21:15:122
272035199251,21cyclictest2837639-21apt-get21:05:142
272035199251,21cyclictest2735820-21apt-get19:25:132
272034699251,21cyclictest2776439-21apt-get20:05:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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