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2026-01-19 - 01:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot4.osadl.org (updated Sun Jan 18, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238212799282,22cyclictest0-21swapper/007:25:010
238213499262,20cyclictest2470053-21apt-get08:45:112
238213199260,24cyclictest2465465-21grep08:40:161
2382127992620,4cyclictest2475747-21apt-get08:55:080
238213899251,20cyclictest2521793-21apt-get09:40:143
238213499251,22cyclictest2429584-21apt-get08:05:132
238213499250,23cyclictest2541992-21chrt10:00:112
238213199252,3cyclictest2663860-21apt-get12:00:121
238213199252,22cyclictest2501146-21apt-get09:20:121
238213199251,20cyclictest0-21swapper/110:05:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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