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2026-02-17 - 08:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot4.osadl.org (updated Tue Feb 17, 2026 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2173499311,1cyclictest183402-21ntpq21:45:213
21734992918,10cyclictest82819-21unin-run20:10:003
2173499290,26cyclictest153547-21unin-run21:20:013
2173499281,2cyclictest327645-21apt-get00:10:123
21734992724,2cyclictest516-21rs:main3
2173499272,22cyclictest174431-21apt-get21:40:123
21734992717,8cyclictest133575-21taskset21:00:113
2173499271,20cyclictest0-21swapper/300:00:123
21734992619,3cyclictest312431-21apt-get23:55:113
2173499260,2cyclictest0-21swapper/322:17:493
2173499260,23cyclictest0-21swapper/322:10:123
2173499260,20cyclictest0-21swapper/322:31:473
2173499260,1cyclictest0-21swapper/320:40:173
2172899261,22cyclictest347831-21latency_hist00:30:021
21734992519,4cyclictest57042-21cron19:45:003
21734992516,7cyclictest225263-21latency_hist22:30:003
2173499251,21cyclictest0-21swapper/322:35:093
2173499250,2cyclictest0-21swapper/300:30:023
2173499250,22cyclictest73465-21tr20:00:163
2173499250,19cyclictest0-21swapper/321:55:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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