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2026-02-07 - 00:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Fri Feb 06, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18040996565,0cyclictest25644-21lspci11:55:491
18044996262,0cyclictest25641-21lspci11:55:492
18047996124,0cyclictest0-21swapper/311:55:493
1804499353,4cyclictest9591-21apt-get08:00:112
1803999350,33cyclictest0-21swapper/010:35:140
18039993433,1cyclictest25804-21lspci11:55:490
18039993128,3cyclictest0-21swapper/009:50:110
1804799300,29cyclictest307-21systemd-journal09:35:003
1804799300,29cyclictest11855-21idleruntime-cro09:15:003
1804499301,28cyclictest24448-21cron10:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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