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2026-02-09 - 15:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Mon Feb 09, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2465993128,2cyclictest17550-21sendmail-msp12:20:020
247199300,1cyclictest307-21systemd-journal12:40:001
2465993026,4cyclictest0-21swapper/009:55:120
2477992927,1cyclictest28720-21perf11:35:013
2477992927,1cyclictest17528-21cron12:20:013
247799290,1cyclictest0-21swapper/308:40:143
247699290,28cyclictest19964-21munin-run12:25:012
247699290,1cyclictest28683-21cron11:35:012
2465992928,1cyclictest2485-21apt-get09:30:120
246599290,28cyclictest0-21swapper/009:45:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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