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2026-05-01 - 02:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Thu Apr 30, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10112993433,1cyclictest779-21lspci10:16:290
1012599300,29cyclictest625-21avahi-daemon08:00:023
1012599300,29cyclictest621-21dbus-daemon10:05:013
1012599300,29cyclictest12732-21sh08:25:003
10121993028,1cyclictest625-21avahi-daemon12:40:002
1012199300,2cyclictest1471-21sh10:20:002
1012599290,1cyclictest2097-21cron11:30:013
10121992927,1cyclictest30072-21cron09:05:012
1012199290,28cyclictest28561-21apt-get10:10:132
1012199290,28cyclictest0-21swapper/212:25:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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