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2026-02-14 - 13:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sat Feb 14, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
104699300,29cyclictest621-21dbus-daemon00:40:003
1042993028,2cyclictest4753-21turbostat.cron21:35:002
104299300,2cyclictest12641-21cron19:35:022
1046992927,1cyclictest1822-21cron20:20:023
1046992927,1cyclictest12033-21cron21:50:003
104699290,28cyclictest5924-21apt-get22:45:013
1042992927,1cyclictest621-21dbus-daemon19:15:002
1042992927,1cyclictest13209-21perf23:00:012
1042992927,1cyclictest0-21swapper/221:10:012
104299290,28cyclictest330-21apt-get21:25:102
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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