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2026-01-26 - 11:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Mon Jan 26, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2337993128,2cyclictest307-21systemd-journal23:15:003
233799310,30cyclictest307-21systemd-journal22:00:003
233799300,1cyclictest621-21dbus-daemon23:35:023
232799300,1cyclictest27521-21sh00:40:010
233799290,28cyclictest31099-21idleruntime-cro21:20:013
233799290,28cyclictest0-21swapper/319:30:023
233499290,28cyclictest5690-21perf21:35:002
233499290,28cyclictest27234-21munin-run23:30:022
233499290,28cyclictest27234-21munin-run23:30:012
233499290,28cyclictest20828-21apt-get00:25:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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