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2026-02-02 - 21:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Mon Feb 02, 2026 12:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
361299306,11cyclictest0-21swapper/210:53:392
3612993028,1cyclictest24841-21apt-get11:25:132
361299300,29cyclictest621-21dbus-daemon07:35:012
361199300,29cyclictest621-21dbus-daemon08:40:001
361099300,29cyclictest25373-21apt-get12:35:130
361799290,28cyclictest9150-21apt-get08:30:133
361799290,28cyclictest29861-21apt-get08:05:123
361799290,28cyclictest0-21swapper/311:45:143
361299290,28cyclictest10837-21apt-get07:25:122
361199290,28cyclictest28358-21munin-run10:20:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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