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2026-02-27 - 15:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Fri Feb 27, 2026 00:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2204599339,11cyclictest0-21swapper/220:59:272
2204599327,25cyclictest0-21swapper/221:10:392
2204599310,2cyclictest28664-21cron21:40:002
2203899310,30cyclictest17860-21idleruntime-cro22:25:011
2204899300,29cyclictest2714-21idleruntime-cro00:10:003
2204899290,28cyclictest0-21swapper/321:45:123
2204899290,28cyclictest0-21swapper/300:20:113
2204899290,1cyclictest627-21apt-get20:40:103
2204899290,1cyclictest0-21swapper/322:10:123
2204599290,1cyclictest30492-21munin-run00:00:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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