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2026-02-21 - 18:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sat Feb 21, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1937899300,29cyclictest990-21cron07:40:013
1936599300,1cyclictest307-21systemd-journal11:00:010
1937899290,28cyclictest12522-21apt-get11:30:103
1937899290,28cyclictest0-21swapper/312:15:013
19373992928,1cyclictest30679-21apt-get11:00:132
1937399290,28cyclictest0-21swapper/210:15:012
1936899290,28cyclictest24939-21apt-get08:30:121
1936899290,28cyclictest0-21swapper/110:50:121
19365992927,1cyclictest646-21polkitd11:55:010
19365992927,1cyclictest0-21swapper/011:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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