You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-14 - 00:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Fri Feb 13, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1887099300,1cyclictest307-21systemd-journal08:45:013
18866993028,1cyclictest8056-21awk07:55:022
1886399300,29cyclictest649-21gdbus07:15:011
1886399300,29cyclictest621-21dbus-daemon10:00:001
18860993028,1cyclictest29896-21apt-get09:50:100
1886099300,29cyclictest16663-21cron11:40:010
1887099290,1cyclictest0-21swapper/308:00:013
18866992927,1cyclictest3212-21cron12:20:012
1886699290,28cyclictest17352-21cron08:15:002
1886399290,28cyclictest6538-21munin-run10:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional