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2026-02-22 - 13:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sun Feb 22, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5866993328,4cyclictest0-21swapper/222:05:012
586699310,30cyclictest0-21swapper/222:45:122
586699310,1cyclictest0-21swapper/200:10:012
5869993028,1cyclictest0-21swapper/321:20:123
586999300,29cyclictest9825-21awk21:35:003
586999300,29cyclictest24137-21apt-get22:05:123
5864993028,1cyclictest27019-21sh23:20:011
586999290,1cyclictest8990-21awk20:25:023
586999290,1cyclictest20642-21cron00:15:013
5866992927,1cyclictest621-21dbus-daemon20:00:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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