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2026-02-10 - 03:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Tue Feb 10, 2026 00:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1483199330,30cyclictest0-21swapper/100:00:011
1483199310,20cyclictest18324-21irqstats23:50:161
1483499300,1cyclictest7908-21sh23:30:002
1483499300,1cyclictest307-21systemd-journal20:05:012
1482799300,29cyclictest342-21cron22:05:010
1482799300,29cyclictest24972-21cron20:40:000
14837992927,1cyclictest307-21systemd-journal19:45:013
14834992928,1cyclictest3959-21apt-get19:55:132
1483499290,28cyclictest7677-21apt-get22:20:132
1483499290,28cyclictest7677-21apt-get22:20:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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