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2026-02-08 - 02:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sat Feb 07, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1376699380,0cyclictest0-21swapper/208:48:402
1376699322,29cyclictest9873-21sh11:35:012
13770993027,2cyclictest621-21dbus-daemon12:00:023
1377099300,29cyclictest27972-21cron11:05:013
1376699300,29cyclictest21625-21cron08:35:002
13764993028,1cyclictest31792-21sh10:05:001
13759993028,1cyclictest7617-21sh08:05:020
1375999300,29cyclictest3994-21perf12:30:010
1377099290,1cyclictest7849-21cron09:15:003
13764992928,1cyclictest2008-21apt-get10:10:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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