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2026-02-08 - 15:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sun Feb 08, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190799328,11cyclictest3273-21taskset22:37:521
1914993128,2cyclictest32362-21sh23:40:013
1912993028,1cyclictest15150-21cron23:04:592
1912993027,3cyclictest7329-21apt-get20:30:122
1906993028,1cyclictest0-21swapper/023:40:010
191499290,28cyclictest0-21swapper/321:35:093
191499290,1cyclictest20393-21apt-get23:15:123
191499290,1cyclictest10508-21perf22:55:013
1912992927,1cyclictest621-21dbus-daemon19:55:012
190799290,28cyclictest31501-21apt-get22:30:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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