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2026-01-27 - 12:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Tue Jan 27, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21526993028,1cyclictest307-21systemd-journal19:15:023
2152299300,29cyclictest19344-21cron20:15:012
21520993028,1cyclictest621-21dbus-daemon22:55:001
21526992928,1cyclictest0-21swapper/321:00:123
21526992928,1cyclictest0-21swapper/320:40:103
2152699290,28cyclictest0-21swapper/321:25:123
2152699290,1cyclictest12389-21cron20:00:023
2152299290,2cyclictest21997-21chrt20:20:112
2152299290,28cyclictest2033-21munin-run23:05:002
2152299290,28cyclictest0-21swapper/221:40:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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