You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-19 - 10:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Thu Feb 19, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
769599311,29cyclictest621-21dbus-daemon20:50:001
7695993028,1cyclictest621-21dbus-daemon23:35:021
7704992927,1cyclictest6668-21cron21:24:593
769899290,28cyclictest0-21swapper/219:35:132
769899290,1cyclictest4038-21apt-get21:20:002
7695992927,1cyclictest0-21swapper/121:15:001
769599290,28cyclictest21287-21apt-get21:55:101
769599290,28cyclictest0-21swapper/120:25:121
769299290,28cyclictest28270-21apt-get22:10:120
7704992828,0cyclictest0-21swapper/323:40:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional