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2026-02-15 - 09:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sun Feb 15, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2565299310,30cyclictest10343-21sh00:20:012
2565199310,30cyclictest2171-21idleruntime-cro21:45:011
2565399300,1cyclictest307-21systemd-journal20:20:023
2565199300,29cyclictest635-21rs:main1
2565099300,29cyclictest15100-21apt-get19:55:150
25653992928,1cyclictest16463-21apt-get22:15:123
25653992927,1cyclictest0-21swapper/300:40:013
25652992927,1cyclictest29683-21apt-get20:25:142
2565299290,28cyclictest25000-21apt-get20:15:122
2565299290,28cyclictest0-21swapper/219:55:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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