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2026-03-02 - 15:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Mon Mar 02, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1743993431,2cyclictest307-21systemd-journal07:40:010
1743993231,1cyclictest19779-21turbostat.cron11:15:010
174599316,0cyclictest9675-21apt-get08:35:102
174399312,29cyclictest0-21swapper/009:35:110
174999300,29cyclictest9393-21awk08:35:013
174999300,29cyclictest27788-21idleruntime-cro08:05:013
174999300,1cyclictest28872-21cron10:25:003
174599290,28cyclictest32715-21apt-get08:15:142
174599290,28cyclictest16143-21apt-get07:40:132
174599290,1cyclictest27894-21cron12:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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