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2026-05-09 - 20:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sat May 09, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2879399310,30cyclictest18043-21awk07:55:013
28793992927,1cyclictest0-21swapper/310:50:113
2879399290,28cyclictest0-21swapper/308:15:133
28792992928,1cyclictest621-21dbus-daemon09:24:592
2879299290,28cyclictest0-21swapper/212:00:132
28791992927,1cyclictest32334-21dump-pmu-power08:24:591
2879199290,28cyclictest27271-21perf11:40:011
2879199290,28cyclictest22885-21apt-get11:30:131
2879199290,28cyclictest0-21swapper/109:45:011
2879199290,28cyclictest0-21swapper/107:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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