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2026-02-11 - 05:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Wed Feb 11, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18685992927,1cyclictest473-21cron00:15:012
1868299290,28cyclictest0-21swapper/100:25:141
1867799290,28cyclictest20843-21perf23:50:010
1867799290,1cyclictest621-21dbus-daemon19:20:010
1869099280,28cyclictest7153-21apt-get23:20:103
1869099280,28cyclictest0-21swapper/319:20:133
1869099280,0cyclictest3932-21apt-get22:05:113
1869099280,0cyclictest17108-21apt-get20:15:133
18682992828,0cyclictest0-21swapper/122:15:111
18682992826,1cyclictest20975-21munin-run19:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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