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2026-02-23 - 14:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Mon Feb 23, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3251899310,30cyclictest307-21systemd-journal22:45:012
3251799300,29cyclictest621-21dbus-daemon00:30:011
3251399300,29cyclictest621-21dbus-daemon19:20:020
32519992927,1cyclictest1-21systemd21:40:013
32519992927,1cyclictest11889-21apt-get23:00:123
3251999290,1cyclictest4306-21cron22:45:013
3251899290,28cyclictest0-21swapper/219:35:132
3251899290,0cyclictest0-21swapper/223:30:122
3251799290,1cyclictest5724-21apt-get23:55:111
3251399290,1cyclictest19608-21munin-run21:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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