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2026-02-03 - 23:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Tue Feb 03, 2026 12:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249499320,0cyclictest0-21swapper/108:45:121
2494993026,1cyclictest15957-21apt-get08:50:121
249999290,28cyclictest0-21swapper/312:15:113
2494992927,1cyclictest621-21dbus-daemon11:10:011
249499290,28cyclictest8273-21apt-get12:00:121
249499290,28cyclictest0-21swapper/111:30:111
249199290,1cyclictest0-21swapper/007:40:010
2499992828,0cyclictest0-21swapper/309:45:113
2499992826,1cyclictest621-21dbus-daemon12:05:003
249999280,27cyclictest0-21swapper/307:55:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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