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2026-01-28 - 00:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Tue Jan 27, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14867993522,0cyclictest28-21ksoftirqd/207:40:142
1486499310,30cyclictest29058-21cron12:15:011
1487199290,28cyclictest17437-21apt-get10:40:133
14867992926,2cyclictest19471-21awk10:45:002
1486799290,28cyclictest0-21swapper/211:15:122
1486799290,28cyclictest0-21swapper/209:30:102
14864992927,1cyclictest17377-21basename11:50:001
1486499290,28cyclictest0-21swapper/111:00:121
1486499290,1cyclictest31150-21ls11:10:001
1486199290,28cyclictest0-21swapper/011:25:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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