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2026-01-22 - 07:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Thu Jan 22, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1510199330,32cyclictest267-21jbd2/nvme0n1p2-00:00:023
1510099310,30cyclictest20021-21cron19:20:022
1510199290,28cyclictest22854-21apt-get20:35:113
1510099290,28cyclictest12277-21munin-run23:40:012
1510099290,28cyclictest0-21swapper/221:55:012
1510099290,28cyclictest0-21swapper/220:55:102
15097992928,1cyclictest621-21dbus-daemon20:15:021
15095992928,1cyclictest621-21dbus-daemon23:15:010
15095992927,1cyclictest7648-21apt-get22:20:110
1509599290,28cyclictest873-21apt-get23:15:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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