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2026-02-01 - 06:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sun Feb 01, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
603099300,29cyclictest6809-21cron20:20:011
603099300,1cyclictest26638-21sh22:10:011
6028993028,1cyclictest649-21gdbus20:55:010
602899300,2cyclictest20796-21cron20:50:010
602899300,1cyclictest1703-21apache200:00:020
6034992927,1cyclictest621-21dbus-daemon22:00:002
603499290,28cyclictest0-21swapper/222:05:112
603099290,28cyclictest23700-21apt-get20:55:121
603099290,28cyclictest23446-21munin-run20:55:011
603099290,28cyclictest0-21swapper/123:55:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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