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2026-02-20 - 23:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Fri Feb 20, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3581993226,6cyclictest1104-21cron11:40:002
358599300,1cyclictest307-21systemd-journal09:50:013
3580993029,1cyclictest22-21ksoftirqd/108:35:111
357599301,28cyclictest17484-21apt-get11:05:140
357599300,29cyclictest3463-21awk11:45:000
3585992927,1cyclictest5853-21apt-get10:40:123
358599290,1cyclictest621-21dbus-daemon08:10:013
3581992928,1cyclictest9666-21apt-get09:40:122
358199290,28cyclictest15386-21apt-get12:10:112
358199290,28cyclictest0-21swapper/208:05:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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