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2026-01-29 - 00:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Wed Jan 28, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2269599300,29cyclictest0-21swapper/010:15:110
2269899290,1cyclictest28212-21cron09:40:013
2269899290,1cyclictest0-21swapper/312:20:123
2269799290,28cyclictest8849-21apt-get12:25:112
2269799290,28cyclictest22580-21apt-get11:45:102
2269799290,28cyclictest16309-21apt-get08:05:112
2269799290,28cyclictest0-21swapper/207:50:142
2269799290,28cyclictest0-21swapper/207:50:132
2269799290,1cyclictest0-21swapper/209:30:012
2269699290,28cyclictest19185-21apt-get09:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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