You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-21 - 06:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sat Feb 21, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1508799310,30cyclictest22532-21munin-run00:00:010
15100993028,1cyclictest17346-21cron19:15:023
1509199300,29cyclictest621-21dbus-daemon20:15:001
15087993028,1cyclictest9664-21cron22:25:000
15100992928,1cyclictest24264-21apt-get22:55:123
1510099290,28cyclictest17245-21apt-get22:40:113
1510099290,1cyclictest0-21swapper/319:20:023
1509699290,28cyclictest9944-21apt-get22:25:122
1509699290,1cyclictest24956-21cron00:05:022
15091992927,1cyclictest25274-21munin-run20:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional