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2026-05-02 - 03:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Fri May 01, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12377993128,2cyclictest649-21gdbus07:55:022
1238299300,29cyclictest23717-21cron11:00:013
1237299300,29cyclictest5577-21cron11:30:010
1237299300,29cyclictest31429-21cron07:50:010
1237299300,1cyclictest8164-21/usr/sbin/munin11:35:140
12382992928,1cyclictest621-21dbus-daemon10:35:003
12382992927,1cyclictest0-21swapper/311:10:013
12382992926,2cyclictest19551-21cron12:00:013
1238299290,28cyclictest0-21swapper/308:50:123
12377992928,1cyclictest649-21gdbus09:05:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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