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2026-02-11 - 20:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Wed Feb 11, 2026 12:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1845999320,7cyclictest0-21swapper/207:59:132
1846299310,30cyclictest18111-21cron10:35:003
1846299300,29cyclictest621-21dbus-daemon11:30:003
18459993028,1cyclictest0-21swapper/211:25:002
1845599300,29cyclictest0-21swapper/108:20:001
1845399300,29cyclictest646-21polkitd08:40:000
1845399300,29cyclictest646-21polkitd08:40:000
1845399300,29cyclictest30049-21cron12:10:000
18462992927,1cyclictest19339-21munin-run09:30:013
1846299290,28cyclictest29007-21munin-run09:50:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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