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2026-04-06 - 00:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Sun Apr 05, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
622699404,36cyclictest0-21swapper/108:04:321
622999316,25cyclictest0-21swapper/207:53:202
622699310,2cyclictest307-21systemd-journal12:00:001
623499300,29cyclictest307-21systemd-journal09:00:003
623499300,29cyclictest22461-21basename11:10:013
622999300,29cyclictest20132-21idleruntime-cro11:05:012
622699300,29cyclictest621-21dbus-daemon10:15:001
622699300,29cyclictest12554-21turbostat.cron10:50:021
6234992927,1cyclictest0-21swapper/311:30:013
6234992926,2cyclictest30390-21sh12:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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