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2026-02-20 - 11:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Fri Feb 20, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1142299300,1cyclictest20074-21awk21:45:003
1141799300,29cyclictest625-21avahi-daemon21:45:001
1141299300,1cyclictest20588-21cron22:55:000
11422992927,1cyclictest16628-21munin-run20:30:003
1142299290,28cyclictest2304-21munin-run20:00:013
11419992927,1cyclictest0-21swapper/221:00:012
1141999290,28cyclictest12070-21apt-get23:45:132
1141999290,28cyclictest0-21swapper/221:35:122
1141999290,28cyclictest0-21swapper/221:10:122
11417992927,1cyclictest0-21swapper/120:30:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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