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2026-03-03 - 14:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Tue Mar 03, 2026 00:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2105399300,2cyclictest649-21gdbus00:35:013
2104699300,29cyclictest24687-21apt-get21:35:102
21053992925,4cyclictest0-21swapper/300:35:113
2105399290,28cyclictest22364-21apt-get21:30:123
21046992928,1cyclictest7733-21apt-get23:15:122
2104499290,28cyclictest5275-21munin-run19:45:011
2104499290,28cyclictest1354-21apt-get20:45:141
2104499290,1cyclictest0-21swapper/121:10:001
21043992928,1cyclictest3384-21apt-get00:15:110
21043992927,1cyclictest5730-21apt-get00:20:120
2104399290,28cyclictest10464-21perf21:05:010
2104399290,28cyclictest0-21swapper/019:40:130
2104399290,28cyclictest0-21swapper/019:15:120
21053992828,0cyclictest0-21swapper/320:50:113
21053992828,0cyclictest0-21swapper/300:20:123
21053992827,1cyclictest5458-21munin-run00:20:003
21053992826,1cyclictest307-21systemd-journal22:40:013
21046992828,0cyclictest0-21swapper/200:20:122
2104699280,27cyclictest0-21swapper/223:20:132
21044992828,0cyclictest0-21swapper/100:40:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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