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2026-01-24 - 05:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Sat Jan 24, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
760993327,5cyclictest31013-21cron20:15:023
755993327,5cyclictest31012-21cron20:15:012
76099310,30cyclictest12346-21sh19:35:003
75599317,11cyclictest0-21swapper/223:26:042
75199310,28cyclictest0-21swapper/000:20:110
75599300,29cyclictest12347-21sh19:35:002
754993028,1cyclictest0-21swapper/100:00:021
760992927,1cyclictest5624-21munin-run20:29:593
76099290,28cyclictest31906-21munin-run21:25:003
755992927,1cyclictest30314-21cron23:40:002
75599290,1cyclictest29496-21sh21:20:002
754992927,1cyclictest8777-21cron21:45:011
75499290,28cyclictest8216-21apt-get20:35:121
75499290,28cyclictest19636-21apt-get00:25:131
75499290,28cyclictest14915-21awk20:50:001
75499290,28cyclictest0-21swapper/122:05:101
75499290,28cyclictest0-21swapper/119:35:011
75499290,1cyclictest18085-21cron22:05:001
75499290,1cyclictest16323-21perf23:10:011
75199290,28cyclictest12882-21apt-get20:45:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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