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2026-01-24 - 03:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Fri Jan 23, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2759299300,29cyclictest307-21systemd-journal07:30:021
2759099300,29cyclictest32575-21cron08:30:000
2760099290,28cyclictest0-21swapper/307:40:013
2759799290,28cyclictest7211-21sh12:35:012
2759799290,28cyclictest6036-21apt-get11:20:112
2759299290,28cyclictest15566-21apt-get10:10:131
2759299290,28cyclictest0-21swapper/108:10:121
27590992927,1cyclictest0-21swapper/011:50:000
2759099290,28cyclictest0-21swapper/010:20:110
2759099290,28cyclictest0-21swapper/008:20:130
27600992828,0cyclictest0-21swapper/309:25:113
2760099280,0cyclictest1359-21apt-get11:10:083
27597992826,1cyclictest0-21swapper/211:15:002
2759799280,0cyclictest0-21swapper/208:20:122
27592992827,1cyclictest23233-21perf08:10:021
2759299280,0cyclictest0-21swapper/111:40:121
2759299280,0cyclictest0-21swapper/108:40:111
2759299280,0cyclictest0-21swapper/107:55:121
27590992827,1cyclictest1-21systemd07:20:020
2759099280,28cyclictest0-21swapper/010:05:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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