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2026-02-07 - 09:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Sat Feb 07, 2026 00:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
222799300,29cyclictest4515-21awk19:15:010
222999290,28cyclictest5883-21apt-get21:35:122
222999290,28cyclictest22614-21apt-get00:30:122
222999290,28cyclictest22614-21apt-get00:30:122
222999290,28cyclictest16819-21apt-get19:40:122
222899290,28cyclictest15192-21apt-get21:55:111
222899290,28cyclictest0-21swapper/123:20:071
222799290,28cyclictest0-21swapper/019:35:120
222799290,28cyclictest0-21swapper/000:35:130
222799290,1cyclictest0-21swapper/023:05:010
223099287,14cyclictest811-21snmpd20:55:203
223099280,0cyclictest22006-21apt-get21:00:113
223099280,0cyclictest0-21swapper/322:15:113
2229992825,2cyclictest653-21apt-get20:15:122
222999280,27cyclictest10674-21apt-get00:05:142
2228992828,0cyclictest0-21swapper/121:45:101
2228992827,1cyclictest0-21swapper/100:10:001
2228992825,2cyclictest307-21systemd-journal23:15:021
222899280,28cyclictest0-21swapper/100:00:121
222899280,0cyclictest0-21swapper/123:50:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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