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2026-02-16 - 09:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Mon Feb 16, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31186993128,3cyclictest6331-21apt-get00:00:120
31192993024,5cyclictest621-21dbus-daemon21:15:012
31189993028,1cyclictest649-21gdbus20:15:021
3118999300,29cyclictest621-21dbus-daemon20:25:001
3118999300,29cyclictest6098-21latency_hist00:00:021
3118999300,29cyclictest13338-21cron00:15:011
31186993027,3cyclictest29976-21apt-get20:15:110
31186993025,4cyclictest0-21swapper/021:55:130
3118999290,28cyclictest0-21swapper/121:35:111
31186992927,1cyclictest19706-21perf23:20:010
3118699290,28cyclictest0-21swapper/023:25:120
3118699290,28cyclictest0-21swapper/023:05:000
31196992828,0cyclictest0-21swapper/323:15:113
3119699280,27cyclictest0-21swapper/300:20:013
3119699280,0cyclictest0-21swapper/319:55:123
3119699280,0cyclictest0-21swapper/300:25:133
31192992827,1cyclictest0-21swapper/221:05:122
3119299280,0cyclictest13925-21apt-get20:50:092
3119299280,0cyclictest0-21swapper/222:10:122
31189992828,0cyclictest0-21swapper/119:35:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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