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2026-01-21 - 13:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Wed Jan 21, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1952999317,11cyclictest0-21swapper/119:40:361
1952999310,30cyclictest5161-21cron20:55:001
1953199300,29cyclictest18589-21cron20:15:013
1952999306,11cyclictest0-21swapper/122:28:311
1952899300,2cyclictest9481-21cron00:30:010
19531992927,1cyclictest31466-21munin-run21:50:003
19531992927,1cyclictest0-21swapper/319:20:013
1953199290,28cyclictest6821-21apt-get23:15:103
1953199290,28cyclictest26176-21apt-get20:30:103
1953199290,28cyclictest22910-21apt-get22:40:123
1953199290,28cyclictest0-21swapper/321:05:123
1953199290,28cyclictest0-21swapper/320:40:123
1953099290,28cyclictest20564-21apt-get22:35:102
1953099290,28cyclictest1629-21apt-get21:55:122
1953099290,28cyclictest0-21swapper/221:50:132
1952999290,28cyclictest0-21swapper/121:15:121
19531992827,1cyclictest23575-21cron20:25:013
1953099280,27cyclictest8102-21apt-get21:00:132
1953099280,0cyclictest23135-21apt-get23:50:122
1953099280,0cyclictest0-21swapper/222:25:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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