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2026-01-30 - 08:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Fri Jan 30, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1592199322,29cyclictest0-21swapper/319:10:103
1592199300,29cyclictest14055-21idleruntime-cro20:15:013
1591399301,28cyclictest0-21swapper/123:20:121
1591399301,28cyclictest0-21swapper/123:20:121
1591399300,29cyclictest14909-21cron21:25:001
15921992929,0cyclictest17297-21apt-get20:20:133
1591799290,28cyclictest4984-21apt-get19:55:122
1591799290,28cyclictest0-21swapper/220:10:142
1591799290,1cyclictest0-21swapper/219:15:012
1591399290,28cyclictest0-21swapper/119:45:121
1591399290,1cyclictest19340-21idleruntime-cro20:25:021
1590899290,28cyclictest0-21swapper/022:25:120
1590899290,28cyclictest0-21swapper/021:40:120
1590899290,28cyclictest0-21swapper/020:15:020
15921992827,0cyclictest0-21swapper/322:45:133
1592199280,28cyclictest0-21swapper/322:00:123
1592199280,28cyclictest0-21swapper/300:25:123
1592199280,27cyclictest0-21swapper/321:40:123
1592199280,0cyclictest0-21swapper/321:15:123
1591799280,28cyclictest0-21swapper/222:45:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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