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2026-01-20 - 03:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Mon Jan 19, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2116499300,29cyclictest26307-21cron11:55:013
2116499300,29cyclictest26307-21cron11:55:003
2116199300,29cyclictest26901-21apt-get11:55:110
21164992927,1cyclictest621-21dbus-daemon07:55:023
2116499290,28cyclictest0-21swapper/308:05:113
21163992927,1cyclictest10497-21sh12:30:012
2116399290,28cyclictest5711-21apt-get07:45:122
2116299290,28cyclictest0-21swapper/111:50:121
2116299290,28cyclictest0-21swapper/111:50:111
2116299290,28cyclictest0-21swapper/110:15:121
2116199290,28cyclictest1468-21apt-get12:10:130
21164992828,0cyclictest0-21swapper/311:40:123
21164992828,0cyclictest0-21swapper/307:30:013
21164992826,1cyclictest23455-21sendmail-msp10:40:013
2116499280,28cyclictest0-21swapper/309:40:113
2116499280,0cyclictest0-21swapper/308:50:113
21163992826,1cyclictest1-21systemd11:45:002
21163992826,1cyclictest0-21swapper/211:10:012
2116399280,28cyclictest0-21swapper/208:15:122
2116399280,27cyclictest3392-21apt-get07:40:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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