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2026-02-02 - 08:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Mon Feb 02, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2782499300,29cyclictest0-21swapper/221:15:202
2782499290,28cyclictest8490-21apt-get23:10:112
2782499290,28cyclictest24298-21apt-get22:35:142
27823992928,1cyclictest28630-21apt-get20:20:141
2782399290,28cyclictest0-21swapper/120:30:121
2782299290,28cyclictest0-21swapper/020:10:130
27824992826,1cyclictest0-21swapper/219:35:012
2782499280,27cyclictest0-21swapper/220:25:142
2782499280,27cyclictest0-21swapper/200:20:122
2782499280,0cyclictest31595-21apt-get22:50:122
27823992827,0cyclictest0-21swapper/119:10:141
27823992826,1cyclictest307-21systemd-journal00:20:011
2782399280,28cyclictest0-21swapper/122:50:121
2782299280,28cyclictest0-21swapper/021:40:070
2782299280,28cyclictest0-21swapper/019:40:130
2782299280,0cyclictest0-21swapper/023:50:120
27825992727,0cyclictest0-21swapper/321:25:143
27825992727,0cyclictest0-21swapper/320:25:143
2782599270,0cyclictest0-21swapper/322:50:133
2782599270,0cyclictest0-21swapper/320:20:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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