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2026-06-14 - 17:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5.osadl.org (updated Sun Jun 14, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
882499328,11cyclictest0-21swapper/207:26:082
8828993028,1cyclictest821-21cron12:35:013
882899300,29cyclictest9659-21cron11:45:013
882899300,29cyclictest5877-21cron09:20:003
881999300,29cyclictest17924-21perf09:45:001
882899290,28cyclictest24629-21apt-get08:50:123
8824992927,1cyclictest31201-21apt-get12:30:102
882499290,28cyclictest5007-21apt-get10:25:132
882499290,28cyclictest30130-21apt-get10:10:122
882499290,28cyclictest0-21swapper/211:50:122
882499290,28cyclictest0-21swapper/211:25:122
882499290,28cyclictest0-21swapper/210:15:122
881999290,28cyclictest16700-21apt-get10:50:121
881599290,28cyclictest22305-21apt-get08:45:110
881599290,1cyclictest266522sleep008:55:010
8828992826,1cyclictest9752-21munin-run08:20:013
882899280,28cyclictest0-21swapper/307:40:123
882899280,0cyclictest0-21swapper/312:10:113
8824992828,0cyclictest0-21swapper/208:35:112
8824992827,0cyclictest0-21swapper/208:30:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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