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2026-06-22 - 20:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5s.osadl.org (updated Mon Jun 22, 2026 12:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
448299280,0cyclictest0-21swapper/010:55:200
448299273,21cyclictest62550irq/127-eno111:23:100
4482992722,4cyclictest0-21swapper/009:55:010
448299270,23cyclictest30677-21diskmemload11:17:550
449499260,25cyclictest5263-21head09:15:283
449199260,25cyclictest12331-21rm09:52:442
4484992623,2cyclictest3255-21head11:45:291
448299260,25cyclictest0-21swapper/010:34:380
448299260,25cyclictest0-21swapper/009:12:190
448299260,23cyclictest0-21swapper/009:55:120
448299260,1cyclictest27188-21sh10:05:490
448299260,1cyclictest0-21swapper/012:02:010
4494992523,1cyclictest0-21swapper/311:47:253
449499250,24cyclictest30677-21diskmemload12:28:423
449499250,1cyclictest0-21swapper/311:33:563
449199250,24cyclictest30677-21diskmemload10:39:392
449199250,24cyclictest23218-21ssh12:34:202
4484992523,1cyclictest0-21swapper/112:10:241
448499250,24cyclictest30677-21diskmemload10:46:291
448499250,24cyclictest0-21swapper/112:30:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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