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2026-02-02 - 15:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot5s.osadl.org (updated Mon Feb 02, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20418992623,3cyclictest14165-21diskmemload10:05:343
20417992623,2cyclictest8645-21sh09:35:282
2040799260,25cyclictest7921-21ssh12:09:180
2041799250,24cyclictest0-21swapper/209:49:292
2041299250,24cyclictest2829-21ssh09:30:011
2041299250,24cyclictest14165-21diskmemload10:43:311
2041299250,24cyclictest0-21swapper/112:18:501
2041299250,1cyclictest14165-21diskmemload11:06:241
2040799250,24cyclictest0-21swapper/010:23:300
2040799250,24cyclictest0-21swapper/008:28:360
20418992422,1cyclictest1097-21grep12:03:393
2041899240,2cyclictest2949-21sh12:36:013
2041899240,23cyclictest0-21swapper/310:45:173
2041899240,23cyclictest0-21swapper/309:13:043
2041899240,0cyclictest14165-21diskmemload11:17:233
20417992422,1cyclictest0-21swapper/209:11:582
20417992420,1cyclictest15390-21ssh12:17:162
20417992420,1cyclictest0-21swapper/211:44:402
2041799240,23cyclictest8589-21ssh10:06:392
2041799240,23cyclictest30967-21sh09:57:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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