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2026-07-07 - 03:46

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot5s.osadl.org (updated Tue Jul 07, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15054992623,2cyclictest6490-21ssh23:30:512
15054992622,4cyclictest0-21swapper/222:51:142
1505999250,24cyclictest0-21swapper/321:52:093
1505499250,24cyclictest0-21swapper/223:27:362
1505499250,24cyclictest0-21swapper/221:18:512
1505499250,22cyclictest31944-21apt-config22:00:012
1505099250,1cyclictest6669-21ssh00:27:151
15049992524,1cyclictest62550irq/127-eno122:44:100
15049992523,1cyclictest0-21swapper/023:01:450
1504999250,24cyclictest6965-21diskmemload23:22:020
1504999250,24cyclictest17122-21ssh21:18:150
15059992423,1cyclictest331rcuc/322:56:373
1505999240,2cyclictest22072-21ssh23:16:333
1505999240,23cyclictest7223-40mandb00:00:013
1505999240,23cyclictest10333-21sh21:11:433
1505999240,0cyclictest151rcu_preempt23:47:333
1505999240,0cyclictest0-21swapper/323:34:093
15054992424,0cyclictest0-21swapper/200:25:412
15054992422,1cyclictest6965-21diskmemload22:06:182
1505499240,0cyclictest0-21swapper/200:12:302
15050992423,1cyclictest0-21swapper/122:02:531
15050992422,1cyclictest0-21swapper/100:16:431
15050992421,2cyclictest29670-21ssh23:21:541
1505099240,23cyclictest0-21swapper/121:55:461
1505099240,23cyclictest0-21swapper/119:56:331
1505099240,22cyclictest0-21swapper/123:44:141
15049992424,0cyclictest6965-21diskmemload23:57:090
15049992423,1cyclictest9994-21chrt00:01:380
15049992423,1cyclictest62550irq/127-eno121:21:050
1504999240,24cyclictest6965-21diskmemload23:18:310
1504999240,24cyclictest0-21swapper/021:40:570
1504999240,24cyclictest0-21swapper/000:34:420
1504999240,23cyclictest6965-21diskmemload22:57:170
1504999240,23cyclictest22195-21cat22:20:000
1504999240,1cyclictest0-21swapper/022:06:310
1504999240,0cyclictest6965-21diskmemload22:11:470
1504999240,0cyclictest6965-21diskmemload00:09:200
15059992323,0cyclictest0-21swapper/323:54:333
15059992323,0cyclictest0-21swapper/323:27:173
15059992323,0cyclictest0-21swapper/323:07:013
15059992323,0cyclictest0-21swapper/323:02:223
15059992323,0cyclictest0-21swapper/322:36:513
15059992323,0cyclictest0-21swapper/322:30:233
15059992323,0cyclictest0-21swapper/321:46:153
15059992323,0cyclictest0-21swapper/321:43:083
15059992323,0cyclictest0-21swapper/300:31:173
15059992323,0cyclictest0-21swapper/300:01:563
15059992322,1cyclictest34-21ksoftirqd/323:35:163
1505999232,21cyclictest34-21ksoftirqd/322:00:013
15059992321,1cyclictest0-21swapper/322:05:483
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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