You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-12 - 08:04

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot5s.osadl.org (updated Thu Mar 12, 2026 00:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21087992623,3cyclictest0-21swapper/321:26:043
2108799260,22cyclictest32658-21ssh22:27:373
2108799260,0cyclictest14720-21diskmemload22:39:473
21077992617,8cyclictest0-21swapper/122:46:451
21082992523,1cyclictest23511-21sh00:22:002
21082992520,4cyclictest0-21swapper/222:08:012
21082992520,0cyclictest0-21swapper/223:05:172
2108299250,2cyclictest31321-21ssh23:59:302
2108299250,24cyclictest20637-21sh23:48:592
2107799250,1cyclictest0-21swapper/123:57:441
2107399250,24cyclictest0-21swapper/021:29:060
2108799240,24cyclictest14720-21diskmemload00:28:473
2108799240,23cyclictest14720-21diskmemload00:01:053
2108799240,23cyclictest0-21swapper/321:18:463
2108799240,0cyclictest0-21swapper/322:23:303
21082992422,1cyclictest0-21swapper/223:41:382
2108299240,2cyclictest18067-21sh22:14:222
2108299240,23cyclictest29203-21ssh00:27:472
2108299240,23cyclictest0-21swapper/222:27:012
2108299240,0cyclictest14720-21diskmemload21:42:362
21077992422,1cyclictest14720-21diskmemload21:36:451
21077992422,1cyclictest13372-21sh00:12:291
21077992422,1cyclictest0-21swapper/122:53:091
21077992421,2cyclictest538-21ssh00:01:261
2107799240,2cyclictest28518-21ssh21:53:521
2107799240,24cyclictest0-21swapper/122:33:551
2107799240,24cyclictest0-21swapper/121:59:541
2107799240,24cyclictest0-21swapper/121:59:541
2107799240,24cyclictest0-21swapper/100:15:031
2107799240,23cyclictest20575-21sh23:17:521
2107799240,23cyclictest19012-21ssh22:15:241
2107799240,23cyclictest14720-21diskmemload22:09:301
2107799240,23cyclictest0-21swapper/122:44:031
2107799240,1cyclictest14720-21diskmemload23:34:071
21073992423,1cyclictest728-21sh00:31:520
21073992421,2cyclictest24352-21ssh00:23:230
2107399240,24cyclictest14720-21diskmemload23:30:490
2107399240,24cyclictest0-21swapper/022:52:460
2107399240,24cyclictest0-21swapper/022:42:470
2107399240,23cyclictest25109-21perf20:25:010
2107399240,23cyclictest21345-21ssh23:18:590
2107399240,23cyclictest17052-21ssh21:42:140
2107399240,23cyclictest14720-21diskmemload21:53:180
2107399240,23cyclictest14720-21diskmemload21:36:450
2107399240,23cyclictest14720-21diskmemload21:23:070
2107399240,23cyclictest14720-21diskmemload00:26:480
2107399240,23cyclictest0-21swapper/000:13:060
21087992323,0cyclictest0-21swapper/323:30:453
21087992323,0cyclictest0-21swapper/323:12:103
21087992323,0cyclictest0-21swapper/322:51:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional