You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-31 - 16:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot5s.osadl.org (updated Sat Jan 31, 2026 12:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2067899280,22cyclictest17204-21mailstats09:43:342
2067899270,26cyclictest0-21swapper/211:11:342
20678992620,1cyclictest14025-21diskmemload10:52:482
2067899260,25cyclictest0-21swapper/210:23:262
2067899260,21cyclictest0-21swapper/210:38:262
2067899260,1cyclictest2626-21rm11:32:512
2067899260,0cyclictest0-21swapper/210:33:592
20685992523,1cyclictest30115-21ssh10:57:563
20678992520,4cyclictest0-21swapper/210:44:052
20678992520,4cyclictest0-21swapper/210:04:062
20678992519,1cyclictest24752-21ssh11:53:072
2067899250,25cyclictest0-21swapper/212:02:192
2067899250,21cyclictest14025-21diskmemload09:12:462
2067899250,21cyclictest0-21swapper/212:14:372
2067899250,0cyclictest3407-21apt-get11:03:282
2067599250,24cyclictest14025-21diskmemload11:43:351
2067199253,1cyclictest62550irq/127-eno110:17:110
20671992523,1cyclictest8123-21ssh10:36:340
20671992523,1cyclictest19373-21munin-run09:15:010
20671992523,1cyclictest0-21swapper/012:32:370
2067199251,23cyclictest0-21swapper/010:40:020
2067199250,24cyclictest0-21swapper/009:45:020
2068599240,23cyclictest14025-21diskmemload10:50:313
2068599240,23cyclictest0-21swapper/312:33:203
2068599240,23cyclictest0-21swapper/311:41:013
20678992420,0cyclictest0-21swapper/209:35:522
20678992419,1cyclictest9955-21rm10:08:052
20678992419,0cyclictest0-21swapper/210:56:212
2067899240,24cyclictest0-21swapper/212:16:092
2067899240,24cyclictest0-21swapper/211:45:062
2067899240,20cyclictest14025-21diskmemload09:51:012
2067899240,20cyclictest0-21swapper/211:59:032
2067899240,20cyclictest0-21swapper/211:05:012
2067899240,20cyclictest0-21swapper/210:19:032
2067899240,0cyclictest14025-21diskmemload09:57:272
2067899240,0cyclictest0-21swapper/212:30:112
2067899240,0cyclictest0-21swapper/210:29:402
20675992422,1cyclictest14025-21diskmemload10:01:121
2067599240,24cyclictest14025-21diskmemload09:43:551
2067599240,24cyclictest0-21swapper/112:29:011
2067599240,23cyclictest485-21ssh11:59:541
2067599240,23cyclictest32382-21ssh09:28:271
2067599240,0cyclictest14025-21diskmemload11:01:541
20671992423,1cyclictest0-21swapper/011:27:520
20671992423,1cyclictest0-21swapper/011:06:280
20671992423,1cyclictest0-21swapper/010:50:050
2067199241,2cyclictest19660-21acpi11:18:260
2067199240,24cyclictest0-21swapper/010:56:550
2067199240,23cyclictest28461-21ssh11:55:430
2067199240,23cyclictest1606-21rm10:29:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional