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2024-04-29 - 22:26

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot5s.osadl.org (updated Mon Apr 29, 2024 00:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31567992624,1cyclictest0-21swapper/021:43:240
3156899250,24cyclictest4661-21sh21:22:261
3156899250,24cyclictest24854-21diskmemload21:34:171
3156799250,24cyclictest0-21swapper/023:30:050
31570992424,0cyclictest0-21swapper/322:44:133
31570992423,1cyclictest0-21swapper/323:10:253
3157099240,23cyclictest24854-21diskmemload21:41:403
3157099240,23cyclictest24854-21diskmemload00:13:533
3157099240,23cyclictest0-21swapper/321:31:033
3156999240,0cyclictest24854-21diskmemload23:31:112
31568992423,1cyclictest24854-21diskmemload23:28:371
31568992423,1cyclictest24854-21diskmemload23:28:371
3156899240,2cyclictest4776-21sh00:09:221
3156899240,24cyclictest0-21swapper/123:21:381
3156899240,23cyclictest24854-21diskmemload21:36:391
3156899240,23cyclictest24854-21diskmemload21:27:031
3156899240,0cyclictest0-21swapper/122:13:091
3156899240,0cyclictest0-21swapper/100:12:471
31567992424,0cyclictest24854-21diskmemload22:52:530
31567992421,2cyclictest0-21swapper/000:00:060
3156799240,23cyclictest24854-21diskmemload23:20:100
3156799240,23cyclictest24854-21diskmemload22:36:100
3156799240,23cyclictest24854-21diskmemload22:02:370
3156799240,23cyclictest24854-21diskmemload21:28:030
3156799240,23cyclictest0-21swapper/021:36:400
3156799240,0cyclictest24854-21diskmemload23:55:540
3156799240,0cyclictest24854-21diskmemload23:06:120
31570992323,0cyclictest0-21swapper/323:52:533
31570992323,0cyclictest0-21swapper/322:51:343
31570992323,0cyclictest0-21swapper/322:25:543
31570992323,0cyclictest0-21swapper/322:10:083
31570992323,0cyclictest0-21swapper/300:23:323
3157099231,1cyclictest0-21swapper/323:18:043
3157099230,2cyclictest4599-21ssh00:09:023
3157099230,23cyclictest0-21swapper/323:08:343
3157099230,23cyclictest0-21swapper/322:17:443
3157099230,23cyclictest0-21swapper/321:50:063
3157099230,23cyclictest0-21swapper/300:18:133
3157099230,22cyclictest23716-21sh22:46:493
3157099230,22cyclictest0-21swapper/321:25:183
3157099230,22cyclictest0-21swapper/300:00:423
3157099230,0cyclictest0-21swapper/323:49:173
3157099230,0cyclictest0-21swapper/321:47:103
3157099230,0cyclictest0-21swapper/300:35:013
31569992323,0cyclictest24854-21diskmemload22:24:112
31569992323,0cyclictest24854-21diskmemload22:10:422
31569992323,0cyclictest24854-21diskmemload21:32:012
31569992323,0cyclictest0-21swapper/223:50:432
31569992323,0cyclictest0-21swapper/222:06:172
31569992323,0cyclictest0-21swapper/221:45:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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