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2026-02-17 - 18:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Tue Feb 17, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1727582430,2sleep20-21swapper/209:45:152
4163787993128,1cyclictest0-21swapper/308:40:003
4163787992924,2cyclictest0-21swapper/310:55:013
4163787992420,1cyclictest0-21swapper/307:25:013
4163787992218,1cyclictest0-21swapper/311:50:233
416378799211,16cyclictest183060-21sleep09:55:003
4163787992017,1cyclictest0-21swapper/312:20:183
4163787991915,1cyclictest0-21swapper/310:01:083
416378799191,14cyclictest336340-21taskset11:55:113
416378799191,14cyclictest265936-21turbostat11:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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