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2026-02-22 - 23:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sun Feb 22, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3709408993330,1cyclictest0-21swapper/309:30:013
3709408992218,1cyclictest0-21swapper/307:59:293
3709408992117,2cyclictest0-21swapper/310:45:003
39130052200,1sleep23913129-21gltestperf09:45:142
3709408992017,1cyclictest0-21swapper/311:45:153
3709408992017,1cyclictest0-21swapper/311:00:003
3709408992015,3cyclictest3737563-21turbostat07:30:013
3709408991917,1cyclictest0-21swapper/311:35:013
3709408991916,1cyclictest0-21swapper/308:19:593
370940899191,15cyclictest3976849-21sleep10:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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