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2026-01-26 - 09:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Mon Jan 26, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2010092710,1sleep20-21swapper/220:05:192
124876992421,1cyclictest0-21swapper/323:25:013
124876992116,4cyclictest178316-21turbostat19:50:003
307598190,4rtkit-daemon159099-21sed19:35:001
124876991916,1cyclictest0-21swapper/323:25:253
124876991916,1cyclictest0-21swapper/320:35:003
124876991916,1cyclictest0-21swapper/320:35:003
12487699191,13cyclictest538375-21sleep00:34:553
12487699191,13cyclictest538365-21turbostat00:30:003
12487699188,6cyclictest280994-21turbostat21:10:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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