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2026-02-20 - 19:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Fri Feb 20, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138418121850,181sleep11332439-21kworker/u16:1+efi_rts_wq07:12:011
1378054992319,1cyclictest0-21swapper/309:20:153
1378054992219,1cyclictest0-21swapper/311:05:003
1378054991916,1cyclictest0-21swapper/312:30:163
137805499191,14cyclictest1470912-21taskset08:20:123
137805499187,7cyclictest17470672sleep311:55:013
1378054991816,1cyclictest0-21swapper/311:40:013
1378054991815,1cyclictest0-21swapper/312:10:163
137805499181,13cyclictest1740660-21turbostat11:50:013
137805499181,13cyclictest1586504-21turbostat09:50:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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