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2026-02-24 - 20:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Tue Feb 24, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184167521070,1sleep2431ktimers/207:10:312
1835658993229,1cyclictest0-21swapper/311:10:003
183565899271,12cyclictest1908635-21turbostat08:05:003
1835658992320,1cyclictest0-21swapper/307:30:003
1835658992118,1cyclictest0-21swapper/311:35:013
1835658992017,1cyclictest0-21swapper/309:55:013
1835658991916,1cyclictest0-21swapper/311:55:003
183565899191,14cyclictest2025004-21chrt09:35:113
20505872182,4sleep02050609-21apt-get09:55:130
183565899188,7cyclictest1913694-21taskset08:05:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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