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2026-09-17 - 05:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Wed Sep 16, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1391485993027,1cyclictest0-21swapper/310:00:183
1391485992825,1cyclictest0-21swapper/312:35:013
1391485992724,1cyclictest0-21swapper/312:00:003
1391485992724,1cyclictest0-21swapper/309:40:153
1391485992724,1cyclictest0-21swapper/309:20:193
1391485992723,1cyclictest0-21swapper/310:40:183
139148599271,23cyclictest1874536-21turbostat12:40:003
1391485992522,1cyclictest0-21swapper/309:05:143
1391485992421,1cyclictest0-21swapper/312:20:163
1391485992421,1cyclictest0-21swapper/307:40:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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