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2026-01-29 - 22:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Thu Jan 29, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
954891993127,1cyclictest0-21swapper/309:50:003
954891992926,1cyclictest0-21swapper/310:45:013
954891992925,1cyclictest0-21swapper/310:40:003
954891992419,2cyclictest1085493-21turbostat08:50:013
954891992419,2cyclictest0-21swapper/311:10:013
954891992320,1cyclictest0-21swapper/308:30:153
95489199191,13cyclictest1374467-21turbostat12:35:003
95489199191,13cyclictest1008598-21chrt07:50:013
954891991815,1cyclictest0-21swapper/308:40:143
95489199181,13cyclictest1361926-21taskset12:25:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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