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2026-02-13 - 17:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Fri Feb 13, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3636549993431,1cyclictest0-21swapper/310:25:003
3636549992724,1cyclictest0-21swapper/309:15:013
3636549992320,1cyclictest0-21swapper/311:15:013
3636549992119,1cyclictest0-21swapper/308:35:163
3636549992017,1cyclictest0-21swapper/307:25:183
3636549991915,1cyclictest0-21swapper/308:50:013
363654999191,14cyclictest4018122-21taskset12:05:113
363654999181,12cyclictest4030836-21taskset12:15:003
363654999181,12cyclictest3921589-21taskset10:50:013
40568772170,6sleep14057367-21irqcore12:35:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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