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2026-02-05 - 22:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Thu Feb 05, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3149367992320,1cyclictest0-21swapper/323:20:003
3149367992320,1cyclictest0-21swapper/320:44:593
314936799221,16cyclictest3332356-21taskset21:30:023
3149367992118,1cyclictest0-21swapper/320:35:003
3149367992018,1cyclictest0-21swapper/323:35:013
3149367992016,2cyclictest3299603-21turbostat21:05:003
33522422190,1sleep10-21swapper/121:45:161
3149367991911,4cyclictest35129032chrt23:50:113
314936799191,13cyclictest3383853-21taskset22:10:013
314936799187,8cyclictest3575331-21chrt00:35:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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