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2026-06-17 - 18:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Wed Jun 17, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4132152330,1sleep10-21swapper/111:10:151
7069399291,23cyclictest428080-21turbostat11:20:003
70693992824,1cyclictest0-21swapper/309:30:193
70693992824,1cyclictest0-21swapper/309:30:193
70693992421,1cyclictest0-21swapper/310:40:123
70693992421,1cyclictest0-21swapper/310:25:013
70693992421,1cyclictest0-21swapper/309:20:263
70693992320,1cyclictest0-21swapper/311:10:003
70693992219,1cyclictest0-21swapper/311:00:113
70693992219,1cyclictest0-21swapper/310:00:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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