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2026-02-28 - 21:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sat Feb 28, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2328989992825,1cyclictest0-21swapper/310:20:003
2328989992420,1cyclictest0-21swapper/307:15:003
2328989992118,1cyclictest0-21swapper/307:35:043
232898999202,14cyclictest2585413-21taskset10:30:113
2328989991916,1cyclictest0-21swapper/311:59:593
2328989991915,1cyclictest0-21swapper/311:15:553
232898999182,12cyclictest2635775-21turbostat11:10:013
2328989991815,1cyclictest0-21swapper/312:40:003
232898999181,13cyclictest2554131-21taskset10:05:143
232898999181,12cyclictest2597947-21taskset10:40:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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