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2026-02-21 - 20:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sat Feb 21, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7448972240,4sleep1321rcuc/110:50:171
456433992421,1cyclictest0-21swapper/309:20:013
7214312230,1sleep20-21swapper/210:30:262
456433992320,1cyclictest0-21swapper/312:20:003
456433992319,1cyclictest0-21swapper/308:14:593
456433992118,1cyclictest0-21swapper/307:25:003
45643399206,7cyclictest7407612sleep310:46:313
456433992017,1cyclictest0-21swapper/308:50:233
456433992017,1cyclictest0-21swapper/308:40:003
45643399196,6cyclictest8437892sleep312:08:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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