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2026-09-10 - 02:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Wed Sep 09, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178681221220,117sleep21663269-21kworker/u16:0+efi_rts_wq10:20:142
1520478992825,1cyclictest0-21swapper/310:20:003
1520478992522,1cyclictest0-21swapper/311:55:003
1520478992522,1cyclictest0-21swapper/309:20:173
1520478992421,1cyclictest0-21swapper/307:20:543
1520478992320,1cyclictest0-21swapper/312:25:233
1520478992320,1cyclictest0-21swapper/308:00:393
1520478992219,1cyclictest0-21swapper/310:00:263
1520478992219,1cyclictest0-21swapper/307:45:163
1520478992118,1cyclictest0-21swapper/311:10:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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