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2026-02-15 - 22:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sun Feb 15, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1822010992118,1cyclictest0-21swapper/309:00:003
1822010992017,1cyclictest0-21swapper/311:10:003
182201099201,16cyclictest2184526-21sleep11:50:003
182201099201,13cyclictest1881939-21taskset07:55:003
1822010991916,1cyclictest0-21swapper/312:32:173
182201099191,15cyclictest1949661-21taskset08:45:183
182201099191,14cyclictest1939939-21chrt08:40:013
182201099191,13cyclictest2159121-21taskset11:30:003
182201099191,13cyclictest1991500-21taskset09:20:003
182201099191,13cyclictest1933440-21chrt08:34:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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