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2026-02-14 - 17:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sat Feb 14, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2734927992411,10cyclictest2995413-21turbostat10:30:003
2734927992118,1cyclictest0-21swapper/308:30:003
2734927992017,1cyclictest0-21swapper/312:15:003
2734927992017,1cyclictest0-21swapper/309:15:183
2734927991916,1cyclictest0-21swapper/312:20:003
2734927991916,1cyclictest0-21swapper/311:50:003
2734927991916,1cyclictest0-21swapper/311:10:163
2734927991916,1cyclictest0-21swapper/307:35:133
273492799187,7cyclictest29247902sleep309:35:123
273492799181,13cyclictest2937398-21turbostat09:45:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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