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2026-02-27 - 21:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Fri Feb 27, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3277327992724,1cyclictest0-21swapper/307:15:003
327732799202,14cyclictest3469638-21turbostat09:40:003
3277327992017,1cyclictest0-21swapper/310:45:003
327732799201,6cyclictest3323884-21turbostat07:45:013
3277327992016,1cyclictest0-21swapper/311:15:003
327732799201,15cyclictest3666502-21chrt12:15:133
327732799201,13cyclictest3583937-21chrt11:09:563
3277327991912,4cyclictest3488679-21turbostat09:59:563
3277327991912,4cyclictest3488679-21turbostat09:59:553
327732799191,13cyclictest3488672-21turbostat09:55:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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