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2026-03-09 - 07:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Mon Mar 09, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
268828321020,1sleep10-21swapper/120:50:171
27170502650,4sleep02717054-21cut21:15:160
26753232370,1sleep10-21swapper/120:40:191
255254699278,7cyclictest2826099-21turbostat22:40:003
2552546992320,1cyclictest0-21swapper/321:45:003
2552546992017,1cyclictest0-21swapper/319:10:153
2552546992017,1cyclictest0-21swapper/319:10:153
2552546991917,1cyclictest0-21swapper/320:00:013
255254699191,14cyclictest2664077-21taskset20:35:013
2552546991815,1cyclictest0-21swapper/321:45:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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