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2026-03-01 - 23:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sun Mar 01, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117508299274,20cyclictest1451869-21turbostat10:49:553
1175082992320,1cyclictest0-21swapper/310:45:013
307598200,9rtkit-daemon1247768-21/usr/sbin/munin08:05:142
307598200,9rtkit-daemon1247768-21/usr/sbin/munin08:05:132
117508299201,14cyclictest1573194-21taskset12:19:593
1175082991917,1cyclictest0-21swapper/312:00:153
1175082991916,1cyclictest0-21swapper/307:25:173
1175082991914,2cyclictest1356089-21sleep09:30:003
117508299185,9cyclictest14137152sleep310:15:093
1175082991815,1cyclictest0-21swapper/311:40:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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