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2026-01-19 - 08:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Mon Jan 19, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2487353994430,1cyclictest0-21swapper/320:20:003
2487353992724,1cyclictest0-21swapper/321:14:593
2487353992118,1cyclictest0-21swapper/323:55:163
248735399211,14cyclictest2812714-21taskset23:25:013
2487353991916,1cyclictest0-21swapper/323:00:143
2487353991916,1cyclictest0-21swapper/321:05:003
248735399191,13cyclictest2730386-21turbostat22:20:003
248735399191,13cyclictest2730386-21turbostat22:19:593
248735399191,13cyclictest2685896-21turbostat21:45:003
248735399188,7cyclictest25468062sleep319:55:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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