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2026-02-08 - 22:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot8.osadl.org (updated Sun Feb 08, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31261723801,375sleep0312160-21kworker/u16:3+efi_rts_wq12:20:120
411042799202,14cyclictest45826-21taskset08:50:133
411042799201,14cyclictest153794-21taskset10:14:593
411042799191,13cyclictest242726-21taskset11:25:013
411042799188,7cyclictest446122sleep308:45:213
4110427991815,1cyclictest0-21swapper/311:50:013
4110427991815,1cyclictest0-21swapper/311:20:013
4110427991815,1cyclictest0-21swapper/311:15:013
4110427991815,1cyclictest0-21swapper/309:30:003
411042799181,13cyclictest77740-21taskset09:15:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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