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2026-01-27 - 09:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Tue Jan 27, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35605862770,1sleep00-21swapper/021:31:210
35270252560,2sleep00-21swapper/021:05:160
3371215992825,1cyclictest0-21swapper/321:15:013
3371215992623,1cyclictest0-21swapper/321:50:003
3371215992320,1cyclictest0-21swapper/320:00:003
3371215992218,1cyclictest0-21swapper/319:35:003
3371215992115,3cyclictest3800332-21turbostat00:40:003
3371215992017,1cyclictest0-21swapper/320:15:003
337121599192,13cyclictest3451145-21turbostat20:10:003
3371215991916,1cyclictest0-21swapper/322:49:553
3371215991916,1cyclictest0-21swapper/321:50:133
3371215991916,1cyclictest0-21swapper/320:25:163
3371215991916,1cyclictest0-21swapper/320:00:153
337121599191,13cyclictest3386233-21taskset19:20:013
34589692181,14sleep03459832-21grep20:15:170
337121599182,12cyclictest3412517-21taskset19:40:123
337121599181,12cyclictest3377563-21turbostat19:15:003
3371215991714,1cyclictest0-21swapper/323:30:003
3371215991714,1cyclictest0-21swapper/319:55:013
3371215991714,1cyclictest0-21swapper/300:25:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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