You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-20 - 06:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Tue Jan 20, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1559527993119,8cyclictest1853633-21sleep23:00:013
1559527992926,1cyclictest0-21swapper/323:20:003
1559527992623,1cyclictest0-21swapper/300:20:003
1559527992623,1cyclictest0-21swapper/300:20:003
1559527992522,1cyclictest0-21swapper/322:45:163
1559527992421,1cyclictest0-21swapper/322:35:153
1559527992118,1cyclictest0-21swapper/320:05:013
1559527992118,1cyclictest0-21swapper/320:05:013
1559527992118,1cyclictest0-21swapper/320:00:013
155952799195,7cyclictest1726704-21taskset21:20:003
1559527991815,1cyclictest0-21swapper/323:35:223
1559527991815,1cyclictest0-21swapper/300:25:173
155952799181,13cyclictest1676356-21taskset20:40:133
155952799181,13cyclictest1612500-21turbostat19:50:003
155952799181,13cyclictest1599573-21turbostat19:39:593
155952799177,6cyclictest16864362sleep320:45:193
1559527991714,1cyclictest0-21swapper/323:55:143
1559527991714,1cyclictest0-21swapper/321:25:183
1559527991714,1cyclictest0-21swapper/300:35:003
1559527991714,1cyclictest0-21swapper/300:10:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional