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2026-11-06 - 00:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Thu Nov 05, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3412177992623,1cyclictest0-21swapper/311:50:003
3412177992422,1cyclictest0-21swapper/310:40:203
3412177992421,1cyclictest0-21swapper/307:20:013
3412177992321,0cyclictest0-21swapper/312:00:263
3412177992320,1cyclictest0-21swapper/312:20:553
3412177992320,1cyclictest0-21swapper/311:35:273
3412177992320,1cyclictest0-21swapper/309:50:193
3412177992320,1cyclictest0-21swapper/308:40:223
3412177992320,1cyclictest0-21swapper/307:40:193
3412177992319,1cyclictest0-21swapper/311:00:153
341217799223,15cyclictest3418542-21turbostat07:15:013
3412177992220,1cyclictest0-21swapper/307:20:133
3412177992219,1cyclictest0-21swapper/310:28:013
3412177992219,1cyclictest0-21swapper/310:00:163
341217799220,18cyclictest3549109-21turbostat08:55:003
3412177992119,1cyclictest0-21swapper/312:30:043
3412177992119,1cyclictest0-21swapper/311:20:013
3412177992118,1cyclictest0-21swapper/311:40:123
3412177992118,1cyclictest0-21swapper/310:20:233
3412177992118,1cyclictest0-21swapper/309:20:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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