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2025-12-02 - 07:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Tue Dec 02, 2025 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48510221040,1sleep20-21swapper/223:48:482
2991382300,1sleep20-21swapper/221:54:272
73938992826,1cyclictest0-21swapper/323:50:003
73938992825,1cyclictest0-21swapper/321:00:013
73938992522,1cyclictest0-21swapper/320:40:013
7393899229,1cyclictest0-21swapper/322:50:003
73938992219,1cyclictest0-21swapper/320:10:003
7393899219,9cyclictest0-21swapper/321:10:223
7393899211,9cyclictest477075-21taskset23:43:563
73938992119,1cyclictest0-21swapper/321:55:003
73938992118,2cyclictest0-21swapper/322:00:223
7393899211,15cyclictest170037-21turbostat20:25:003
7393899209,1cyclictest0-21swapper/323:20:173
7393899209,1cyclictest0-21swapper/323:05:213
7393899209,0cyclictest0-21swapper/300:33:403
73938992017,1cyclictest0-21swapper/300:00:143
7393899201,15cyclictest468527-21taskset23:37:513
7393899201,15cyclictest307427-21turbostat22:00:003
7393899201,14cyclictest267446-21chrt21:35:123
7393899201,13cyclictest207950-21taskset20:55:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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