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2026-09-06 - 21:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Sun Sep 06, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30901602630,3sleep1249-21jbd2/sda2-810:00:201
285243199271,22cyclictest3164939-21turbostat10:50:003
2852431992623,1cyclictest0-21swapper/312:20:003
285243199256,7cyclictest3180377-21turbostat11:00:013
2852431992320,1cyclictest0-21swapper/312:00:173
2852431992320,1cyclictest0-21swapper/309:35:163
2852431992320,1cyclictest0-21swapper/308:50:013
2852431992220,1cyclictest0-21swapper/311:00:193
2852431992219,1cyclictest0-21swapper/307:40:003
285243199221,16cyclictest3149066-21taskset10:39:503
2852431992118,1cyclictest0-21swapper/311:40:203
2852431992118,1cyclictest0-21swapper/310:20:123
2852431992118,1cyclictest0-21swapper/310:07:453
285243199211,14cyclictest2931762-21taskset08:10:013
285243199204,6cyclictest3070962-21turbostat09:50:003
2852431992017,1cyclictest0-21swapper/311:20:203
2852431992017,1cyclictest0-21swapper/307:20:073
2852431992016,1cyclictest0-21swapper/309:40:133
285243199201,14cyclictest3336028-21taskset12:37:273
2852431991916,1cyclictest0-21swapper/312:20:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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