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2026-02-24 - 13:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Tue Feb 24, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2292824992522,1cyclictest0-21swapper/319:45:003
2292824992219,1cyclictest0-21swapper/322:40:003
229282499217,11cyclictest0-21swapper/323:35:013
2292824992017,1cyclictest0-21swapper/323:10:013
2292824992017,1cyclictest0-21swapper/322:25:173
2292824992017,1cyclictest0-21swapper/321:00:013
2292824991916,1cyclictest0-21swapper/323:45:173
2292824991916,1cyclictest0-21swapper/323:35:213
2292824991916,1cyclictest0-21swapper/321:30:233
2292824991916,1cyclictest0-21swapper/320:21:403
2292824991915,2cyclictest2577334-21sleep22:49:593
2292824991914,3cyclictest25133442sleep322:00:003
229282499191,15cyclictest2545343-21turbostat22:24:593
229282499191,13cyclictest2494313-21taskset21:45:013
2292824991815,1cyclictest0-21swapper/323:45:013
2292824991815,1cyclictest0-21swapper/322:55:013
2292824991815,1cyclictest0-21swapper/321:55:003
2292824991815,1cyclictest0-21swapper/321:00:133
2292824991815,1cyclictest0-21swapper/320:20:013
2292824991815,1cyclictest0-21swapper/319:35:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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