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2026-01-17 - 16:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Sat Jan 17, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3871029993228,1cyclictest0-21swapper/310:00:003
387102999271,22cyclictest4102393-21sleep10:10:003
3871029992319,1cyclictest0-21swapper/312:20:003
3871029992118,1cyclictest0-21swapper/310:25:003
3871029992016,1cyclictest0-21swapper/312:10:003
387102999201,14cyclictest29145-21taskset11:45:013
307598200,15rtkit-daemon4050629-21ntp_states09:25:222
3871029991815,1cyclictest0-21swapper/311:15:003
3871029991714,1cyclictest0-21swapper/311:35:153
3871029991714,1cyclictest0-21swapper/311:00:123
3871029991714,1cyclictest0-21swapper/310:50:183
3871029991714,1cyclictest0-21swapper/308:35:203
3871029991714,1cyclictest0-21swapper/307:15:013
387102999171,13cyclictest3969114-21taskset08:25:223
387102999171,12cyclictest4159577-21chrt10:55:123
387102999171,12cyclictest4152701-21taskset10:46:223
387102999171,12cyclictest4127662-21turbostat10:30:003
387102999171,12cyclictest4108104-21taskset10:10:243
387102999171,12cyclictest4012963-21turbostat09:00:003
387102999171,12cyclictest3955808-21turbostat08:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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