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2026-02-03 - 10:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Tue Feb 03, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9938702350,1sleep00-21swapper/020:20:010
901874992320,1cyclictest0-21swapper/323:00:173
901874992320,1cyclictest0-21swapper/322:35:013
90187499219,1cyclictest0-21swapper/322:39:593
901874992017,1cyclictest0-21swapper/321:30:193
90187499201,14cyclictest1328344-21sleep00:40:003
90187499199,1cyclictest0-21swapper/323:33:383
90187499199,1cyclictest0-21swapper/321:01:263
90187499196,8cyclictest11352532sleep322:08:013
901874991916,1cyclictest0-21swapper/319:54:593
90187499191,14cyclictest968118-21turbostat20:00:003
90187499191,14cyclictest1321708-21turbostat00:35:003
90187499191,14cyclictest1283521-21taskset00:05:093
90187499191,14cyclictest1251246-21turbostat23:40:003
90187499191,14cyclictest1225620-21taskset23:20:003
90187499191,14cyclictest1070801-21taskset21:19:343
90187499191,14cyclictest1006553-21turbostat20:29:593
90187499187,1cyclictest0-21swapper/321:55:183
90187499186,6cyclictest12960412sleep300:14:553
90187499186,6cyclictest10769792sleep321:21:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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