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2026-01-24 - 08:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Sat Jan 24, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2050426992118,1cyclictest0-21swapper/323:15:003
2050426992018,1cyclictest0-21swapper/320:50:003
2050426992015,2cyclictest2160687-21turbostat20:35:013
205042699201,14cyclictest2262273-21taskset21:55:013
205042699192,13cyclictest2466268-21turbostat00:35:003
205042699191,13cyclictest2294424-21taskset22:20:013
205042699188,7cyclictest24722542sleep300:35:233
2050426991816,1cyclictest0-21swapper/322:00:013
2050426991815,1cyclictest0-21swapper/323:40:003
2050426991815,1cyclictest0-21swapper/319:55:163
205042699181,13cyclictest2453599-21turbostat00:25:003
205042699181,13cyclictest2326303-21taskset22:45:143
205042699180,13cyclictest2402757-21chrt23:45:013
23892732171,9sleep0714-21snmpd23:30:290
2050426991715,1cyclictest0-21swapper/321:15:173
2050426991714,1cyclictest0-21swapper/322:30:173
2050426991714,1cyclictest0-21swapper/319:40:223
2050426991713,1cyclictest0-21swapper/321:10:013
205042699171,12cyclictest2453862-21chrt00:25:123
205042699171,12cyclictest2317629-21taskset22:35:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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