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2025-12-15 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Mon Dec 15, 2025 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1556076993330,1cyclictest0-21swapper/300:20:173
1556076992926,1cyclictest0-21swapper/323:15:003
1556076992724,1cyclictest0-21swapper/320:50:013
1556076992319,1cyclictest0-21swapper/319:15:003
155607699211,15cyclictest1789782-21taskset22:10:133
155607699209,8cyclictest1853464-21sleep23:00:003
1556076992017,1cyclictest0-21swapper/323:19:593
1556076992017,1cyclictest0-21swapper/322:10:013
1556076991916,1cyclictest0-21swapper/323:55:223
155607699191,13cyclictest1808714-21taskset22:25:003
307598180,5rtkit-daemon1597316-21diskstats19:40:122
155607699187,8cyclictest1667403-21sleep20:35:013
155607699181,13cyclictest1911852-21chrt23:45:153
155607699181,13cyclictest1866281-21taskset23:09:563
155607699181,13cyclictest1840965-21chrt22:50:133
1556076991715,1cyclictest0-21swapper/321:44:523
1556076991714,1cyclictest0-21swapper/319:30:133
1556076991714,1cyclictest0-21swapper/300:09:093
155607699171,13cyclictest1944430-21chrt00:10:163
155607699171,13cyclictest1944430-21chrt00:10:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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