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2025-09-19 - 14:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Fri Sep 19, 2025 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79229121200,1sleep10-21swapper/122:20:181
530947992825,2cyclictest724528-21sh21:40:012
530942992723,2cyclictest0-21swapper/123:40:001
530948992522,1cyclictest0-21swapper/319:45:013
530948992522,1cyclictest0-21swapper/300:20:013
530947992420,3cyclictest522-21in:imuxsock00:05:002
530942992420,2cyclictest0-21swapper/100:00:011
530939992420,3cyclictest522-21in:imuxsock22:30:000
530948992320,1cyclictest0-21swapper/322:40:013
530942992319,3cyclictest522-21in:imuxsock23:15:001
530948992219,1cyclictest0-21swapper/321:20:003
530942992219,2cyclictest0-21swapper/122:20:011
530939992219,2cyclictest894084-21sh23:24:590
530948992119,1cyclictest0-21swapper/320:40:003
530948992118,1cyclictest0-21swapper/321:25:003
530947992118,2cyclictest0-21swapper/219:19:592
530942992118,2cyclictest675897-21diskmemload22:05:271
530942992117,2cyclictest0-21swapper/123:50:001
53094299211,6cyclictest748713-21awk21:55:011
53094299211,6cyclictest748713-21awk21:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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