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2026-01-18 - 17:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Sun Jan 18, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312845021070,3sleep0221rcuc/009:30:180
2958666992623,1cyclictest0-21swapper/312:39:593
2958666992522,1cyclictest0-21swapper/310:45:003
2958666992521,1cyclictest0-21swapper/307:15:003
2958666992421,1cyclictest0-21swapper/311:50:133
2958666992320,1cyclictest0-21swapper/312:35:003
2958666992018,1cyclictest0-21swapper/308:55:013
2958666992017,1cyclictest0-21swapper/308:30:143
295866699201,14cyclictest3175254-21turbostat10:10:013
2958666991916,1cyclictest0-21swapper/311:35:193
2958666991916,1cyclictest0-21swapper/307:20:013
295866699191,4cyclictest3233048-21sleep10:55:013
295866699191,14cyclictest3162481-21taskset10:00:113
295866699191,13cyclictest3258804-21taskset11:15:003
2958666991910,5cyclictest3020328-21turbostat08:05:003
295866699181,13cyclictest3294167-21taskset11:40:173
295866699180,15cyclictest3155795-21turbostat09:59:553
2958666991714,1cyclictest0-21swapper/311:20:183
2958666991714,1cyclictest0-21swapper/310:45:173
2958666991714,1cyclictest0-21swapper/308:05:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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