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2026-01-14 - 14:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Wed Jan 14, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31554482360,7sleep2431ktimers/222:20:162
2910045993027,1cyclictest0-21swapper/319:45:003
2910045992521,1cyclictest0-21swapper/320:55:003
2910045992017,1cyclictest0-21swapper/323:40:233
2910045992017,1cyclictest0-21swapper/323:20:003
291004599192,13cyclictest3090951-21taskset21:30:123
2910045991916,1cyclictest0-21swapper/321:50:013
2910045991916,1cyclictest0-21swapper/321:30:013
2910045991916,1cyclictest0-21swapper/321:00:153
291004599191,14cyclictest3148091-21taskset22:15:123
2910045991815,1cyclictest0-21swapper/319:10:133
2910045991813,3cyclictest32436402sleep323:30:113
291004599181,13cyclictest3162173-21taskset22:25:193
291004599181,13cyclictest2985325-21taskset20:05:163
291004599181,13cyclictest2974833-21taskset19:55:223
291004599181,12cyclictest3191910-21chrt22:45:213
31804602170,9sleep23180785-21sed22:40:162
30220462171,13sleep23020692-21/usr/sbin/munin20:35:172
291004599178,6cyclictest29437892sleep319:33:283
291004599171,12cyclictest3269387-21chrt23:50:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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