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2026-02-17 - 10:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8.osadl.org (updated Tue Feb 17, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
431881992926,1cyclictest0-21swapper/320:40:013
431881992421,1cyclictest0-21swapper/320:30:003
431881992014,4cyclictest673366-21turbostat22:15:003
431881991916,1cyclictest0-21swapper/322:00:233
431881991913,3cyclictest841335-21turbostat00:25:003
43188199191,13cyclictest860659-21turbostat00:40:003
43188199191,13cyclictest621848-21taskset21:35:003
43188199191,13cyclictest569920-21taskset20:55:003
43188199191,13cyclictest431991-21taskset19:10:013
431881991815,1cyclictest0-21swapper/321:20:243
431881991815,1cyclictest0-21swapper/319:40:003
43188199181,13cyclictest841598-21taskset00:25:123
43188199181,13cyclictest783624-21taskset23:40:123
43188199181,13cyclictest782630-21taskset23:35:233
8598172171,12sleep2859941-21python300:35:222
43188199176,8cyclictest699082-21turbostat22:34:593
431881991714,1cyclictest0-21swapper/323:27:443
431881991714,1cyclictest0-21swapper/322:40:003
431881991714,1cyclictest0-21swapper/320:30:193
431881991714,1cyclictest0-21swapper/319:30:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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