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2025-10-16 - 09:09

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #e, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot8s.osadl.org (updated Thu Oct 16, 2025 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149389899748739,3cyclictest1455333-21kworker/3:3+events00:20:213
149389899744740,3cyclictest1455333-21kworker/3:3+events00:00:313
149389899743738,4cyclictest1455333-21kworker/3:3+events23:15:203
149389399743739,3cyclictest1626905-21kworker/1:0+events20:55:521
149389899742737,4cyclictest1758388-21turbostat22:49:553
149389899742737,4cyclictest1455333-21kworker/3:3+events00:30:223
149389599742738,3cyclictest1708423-21kworker/2:2+events23:29:202
149389399742735,6cyclictest1626905-21kworker/1:0+events21:30:231
149389899741738,2cyclictest1455333-21kworker/3:3+events21:15:223
149389599741737,3cyclictest1708423-21kworker/2:2+events23:23:592
149389899739735,3cyclictest1455333-21kworker/3:3+events20:48:223
149389899739731,6cyclictest1455333-21kworker/3:3+events21:20:203
149389899738730,3cyclictest1455333-21kworker/3:3+events23:10:233
149389899736732,3cyclictest1455333-21kworker/3:3+events20:00:423
149389899734730,3cyclictest1455333-21kworker/3:3+events23:33:443
149389899734730,3cyclictest1455333-21kworker/3:3+events20:17:153
149389899734730,3cyclictest1455333-21kworker/3:3+events00:10:203
149389899733730,2cyclictest1455333-21kworker/3:3+events00:28:003
149389899733729,3cyclictest1889439-21kworker/3:1+events00:39:053
149389899733727,5cyclictest1455333-21kworker/3:3+events19:24:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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