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2026-02-25 - 18:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Wed Feb 25, 2026 00:54:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283325299203164,11cyclictest0-21swapper/2820:12:3321
283325299203164,11cyclictest0-21swapper/2820:12:3221
283323799202157,13cyclictest0-21swapper/1320:12:325
283323799202157,13cyclictest0-21swapper/1320:12:325
2833255991941,164cyclictest4145565-21kworker/u64:0+efi_rts_wq20:12:3325
2833255991941,164cyclictest4145565-21kworker/u64:0+efi_rts_wq20:12:3325
283322699193155,7cyclictest0-21swapper/1020:12:332
283322699193155,7cyclictest0-21swapper/1020:12:332
2833254991890,156cyclictest0-21swapper/3020:12:3324
2833254991890,156cyclictest0-21swapper/3020:12:3324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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