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2026-02-18 - 14:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Wed Feb 18, 2026 00:54:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11351699204166,11cyclictest0-21swapper/2021:53:5313
113474992011,168cyclictest0-21swapper/421:53:5326
11352599199161,10cyclictest0-21swapper/2921:53:5322
11346199198152,15cyclictest0-21swapper/021:53:540
11348099197166,2cyclictest0-21swapper/621:53:5328
113512991921,162cyclictest123019-21kworker/u64:0+efi_rts_wq21:53:538
113486991920,170cyclictest0-21swapper/821:53:5330
11350599187149,11cyclictest0-21swapper/1321:53:535
11350799183153,13cyclictest411529-21gdbus21:53:536
11349599182153,10cyclictest0-21swapper/1121:53:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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