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2026-01-30 - 05:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Fri Jan 30, 2026 00:54:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44124299225143,60cyclictest0-21swapper/2821:08:5221
44124299225143,60cyclictest0-21swapper/2821:08:5221
44124599220134,64cyclictest0-21swapper/3121:08:5225
44124599220134,64cyclictest0-21swapper/3121:08:5225
4412369922033,158cyclictest0-21swapper/2221:08:5315
4412369922033,158cyclictest0-21swapper/2221:08:5315
44118899213157,2cyclictest0-21swapper/321:08:5323
44118899213157,2cyclictest0-21swapper/321:08:5323
44123299196157,14cyclictest0-21swapper/1821:08:5310
44123299196157,14cyclictest0-21swapper/1821:08:5310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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