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2026-03-05 - 01:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Wed Mar 04, 2026 00:54:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131206799225149,47cyclictest0-21swapper/1120:41:343
1312039991990,166cyclictest0-21swapper/220:41:3412
131209399195163,10cyclictest0-21swapper/2320:41:3516
131205899195163,9cyclictest0-21swapper/820:41:3530
131207399192160,8cyclictest0-21swapper/1320:41:345
131207099192162,2cyclictest0-21swapper/1220:41:344
131209799189148,18cyclictest3342777-21kworker/u64:1+efi_rts_wq20:41:3420
131204599188150,13cyclictest0-21swapper/420:41:3426
131208799187149,16cyclictest1223-21dbus-daemon20:41:349
1312055991860,98cyclictest3342777-21kworker/u64:1+efi_rts_wq21:00:1729
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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