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2026-02-03 - 07:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Tue Feb 03, 2026 00:54:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81052199217160,41cyclictest0-21swapper/2321:42:1416
81048099203162,16cyclictest1080001-21gdbus21:42:1428
81050899201160,16cyclictest0-21swapper/1421:42:136
81051999194165,12cyclictest2121rcuc/2121:42:1414
81051599189158,13cyclictest0-21swapper/1721:42:149
81048999189161,10cyclictest0-21swapper/921:42:1431
81051399187158,12cyclictest1571rcuc/1521:42:147
81048499185153,12cyclictest0-21swapper/721:42:1329
81047799183149,2cyclictest0-21swapper/521:42:1427
81052399181153,8cyclictest0-21swapper/2521:42:1418
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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