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2026-02-22 - 18:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sun Feb 22, 2026 00:54:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4748389918789,65cyclictest0-21swapper/2121:28:0314
4748389918789,65cyclictest0-21swapper/2121:28:0314
47483299172105,38cyclictest0-21swapper/1522:30:167
47483299172105,38cyclictest0-21swapper/1522:30:167
47483599171100,39cyclictest0-21swapper/1822:30:1710
47483599171100,39cyclictest0-21swapper/1822:30:1710
4748489916873,64cyclictest0-21swapper/3121:28:0425
4748489916873,64cyclictest0-21swapper/3121:28:0425
4748409916674,59cyclictest0-21swapper/2321:28:0416
4748409916674,59cyclictest0-21swapper/2321:28:0416
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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