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2026-02-17 - 14:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Tue Feb 17, 2026 00:54:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212162299219133,62cyclictest0-21swapper/2119:28:3314
212162599211129,59cyclictest0-21swapper/2319:28:3316
212162899206121,61cyclictest0-21swapper/2619:28:3319
212162499203164,9cyclictest0-21swapper/2219:28:3315
2121630991970,168cyclictest0-21swapper/2819:28:3321
212162099196155,12cyclictest1865194-21kworker/u64:2+efi_rts_wq19:28:3311
212161499196160,7cyclictest0-21swapper/1419:28:336
212160899195125,49cyclictest0-21swapper/819:28:3330
212162199189114,53cyclictest0-21swapper/2019:28:3313
212161199187153,2cyclictest0-21swapper/1119:28:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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