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2026-01-26 - 05:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Mon Jan 26, 2026 00:55:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
547709917790,62cyclictest0-21swapper/522:04:3727
547709917790,62cyclictest0-21swapper/522:04:3727
548219917113,87cyclictest0-21swapper/2100:05:1714
548219917086,57cyclictest379063-21sshd22:04:3714
548219917086,57cyclictest379063-21sshd22:04:3714
547529916980,57cyclictest0-21swapper/022:04:370
547529916980,57cyclictest0-21swapper/022:04:370
547889916883,56cyclictest0-21swapper/920:14:1231
547729916884,57cyclictest0-21swapper/600:05:1728
548279916787,55cyclictest0-21swapper/2621:44:3219
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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