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2026-03-06 - 08:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Fri Mar 06, 2026 00:55:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15135779917479,69cyclictest0-21swapper/1921:45:1611
15135779917479,69cyclictest0-21swapper/1921:45:1611
15135799917386,60cyclictest0-21swapper/2021:45:1613
15135799917386,60cyclictest0-21swapper/2021:45:1613
15135749917082,65cyclictest0-21swapper/1623:45:488
15135449916784,2cyclictest0-21swapper/421:45:1626
15135449916784,2cyclictest0-21swapper/421:45:1626
151358899166158,5cyclictest0-21swapper/2922:59:4722
151358899166158,5cyclictest0-21swapper/2922:59:4722
151358599165161,2cyclictest0-21swapper/2621:56:1119
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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