You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-04 - 11:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Wed Feb 04, 2026 00:54:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
298948699244147,71cyclictest1631-21nfsd22:20:3613
298948699244147,71cyclictest1631-21nfsd22:20:3613
298947299233153,52cyclictest0-21swapper/622:20:3628
298947299233153,52cyclictest0-21swapper/622:20:3628
298949899223141,49cyclictest0-21swapper/3022:20:3624
298949899223141,49cyclictest0-21swapper/3022:20:3624
298948899220152,37cyclictest2653173-21kworker/u64:1+efi_rts_wq22:20:3615
298948899220152,37cyclictest2653173-21kworker/u64:1+efi_rts_wq22:20:3615
298949199213152,28cyclictest0-21swapper/2522:20:3618
298949199213152,28cyclictest0-21swapper/2522:20:3618
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional