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2026-02-07 - 12:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sat Feb 07, 2026 00:55:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11698639916888,61cyclictest0-21swapper/2300:00:1516
11698649916282,62cyclictest0-21swapper/2421:25:1517
11698619916285,4cyclictest0-21swapper/2123:05:1514
11698619916285,4cyclictest0-21swapper/2123:05:1514
11698509916185,53cyclictest0-21swapper/1321:25:145
116985999159130,2cyclictest0-21swapper/1923:45:1511
11698709915888,7cyclictest0-21swapper/3019:45:1724
11698709915888,7cyclictest0-21swapper/3019:45:1724
116986999156151,4cyclictest0-21swapper/2921:02:4122
116986999155139,10cyclictest0-21swapper/2923:25:3122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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