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2026-01-31 - 06:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sat Jan 31, 2026 00:55:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263233499220133,66cyclictest1667679-21kworker/u64:0+efi_rts_wq00:35:2214
263233499220133,66cyclictest1667679-21kworker/u64:0+efi_rts_wq00:35:2114
263233599202121,58cyclictest0-21swapper/2200:35:2215
263233599202121,58cyclictest0-21swapper/2200:35:2215
263233999200149,25cyclictest0-21swapper/2600:35:2219
263233999200149,25cyclictest0-21swapper/2600:35:2219
263233299199121,56cyclictest0-21swapper/1900:35:2211
263233299199121,56cyclictest0-21swapper/1900:35:2211
2632302991990,165cyclictest0-21swapper/700:35:2229
2632302991990,165cyclictest0-21swapper/700:35:2229
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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