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2026-01-23 - 04:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Thu Jan 22, 2026 00:54:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
388881899176165,10cyclictest0-21swapper/1221:25:174
388881899176165,10cyclictest0-21swapper/1221:25:174
38887819916882,8cyclictest0-21swapper/120:00:171
38887819916882,8cyclictest0-21swapper/120:00:161
388880799167139,17cyclictest0-21swapper/900:10:1731
38888359916679,11cyclictest0-21swapper/2320:00:1716
38888359916679,11cyclictest0-21swapper/2320:00:1716
3888839991640,1cyclictest0-21swapper/2723:00:2220
38888319916474,13cyclictest0-21swapper/1920:00:1711
38888319916474,13cyclictest0-21swapper/1920:00:1711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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