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2026-01-27 - 05:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Tue Jan 27, 2026 00:54:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
224919599176153,2cyclictest0-21swapper/2719:50:1720
224919599176153,2cyclictest0-21swapper/2719:50:1620
22491969917489,62cyclictest0-21swapper/2823:50:1621
22491869916766,83cyclictest0-21swapper/1819:25:1510
22491869916766,83cyclictest0-21swapper/1819:25:1510
2249191991650,90cyclictest0-21swapper/2319:37:1416
2249191991650,90cyclictest0-21swapper/2319:37:1416
22491339916482,9cyclictest0-21swapper/120:20:161
22491819916387,55cyclictest0-21swapper/1619:25:168
22491819916387,55cyclictest0-21swapper/1619:25:168
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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