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2026-02-21 - 15:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sat Feb 21, 2026 00:54:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247818799190182,6cyclictest0-21swapper/1621:35:168
24781999918582,68cyclictest0-21swapper/2819:50:1521
24781999918582,68cyclictest0-21swapper/2819:50:1521
24781539918490,63cyclictest0-21swapper/300:15:1523
24781999916991,55cyclictest0-21swapper/2800:15:1521
2478189991680,93cyclictest0-21swapper/1800:15:1510
24781609916683,53cyclictest0-21swapper/521:13:4927
24781609916683,53cyclictest0-21swapper/521:13:4827
24782029916583,45cyclictest0-21swapper/3122:25:1625
24782029916583,45cyclictest0-21swapper/3122:25:1625
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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