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2026-03-02 - 01:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sun Mar 01, 2026 00:54:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31413769918784,28cyclictest0-21swapper/1820:45:1810
314132399169147,10cyclictest0-21swapper/423:40:1626
314132399169147,10cyclictest0-21swapper/423:40:1626
31413749916587,51cyclictest0-21swapper/1723:15:309
31413319916477,13cyclictest0-21swapper/622:00:1628
31413699916288,8cyclictest0-21swapper/1522:00:167
31413779916079,50cyclictest0-21swapper/1922:00:1611
31413539916074,11cyclictest0-21swapper/1222:00:164
31413899915981,8cyclictest0-21swapper/3022:00:1724
31413879915988,43cyclictest0-21swapper/2823:15:3021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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