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2026-01-16 - 04:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Fri Jan 16, 2026 00:55:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
326336299218154,36cyclictest0-21swapper/1222:08:314
326336299218154,36cyclictest0-21swapper/1222:08:314
326337999215140,48cyclictest0-21swapper/2522:08:3118
326337999215140,48cyclictest0-21swapper/2522:08:3118
326338099211142,7cyclictest0-21swapper/2622:08:3119
326338099211142,7cyclictest0-21swapper/2622:08:3119
326337599199162,7cyclictest0-21swapper/2122:08:3114
326337599199162,7cyclictest0-21swapper/2122:08:3114
326338499194162,2cyclictest0-21swapper/3022:08:3124
326338499194162,2cyclictest0-21swapper/3022:08:3124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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