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2026-02-14 - 12:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sat Feb 14, 2026 00:54:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
395114999174167,5cyclictest0-21swapper/2720:40:1620
395115399166154,10cyclictest0-21swapper/3119:14:0125
395114499166114,42cyclictest0-21swapper/2220:05:1815
395114499166114,42cyclictest0-21swapper/2220:05:1815
395114599159139,10cyclictest0-21swapper/2320:40:1616
39511409915978,74cyclictest0-21swapper/1820:15:1710
39511259915986,46cyclictest0-21swapper/1120:20:183
39511109915969,60cyclictest0-21swapper/722:55:1729
395114899157138,11cyclictest0-21swapper/2621:55:1619
39511519915689,3cyclictest0-21swapper/2919:10:1522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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