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2026-02-28 - 22:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackfslot0.osadl.org (updated Sat Feb 28, 2026 00:54:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9660559917289,55cyclictest0-21swapper/119:44:221
96607799171139,19cyclictest0-21swapper/700:11:1629
96607799171139,19cyclictest0-21swapper/700:11:1629
9661269916787,7cyclictest0-21swapper/2522:35:1518
9661269916787,7cyclictest0-21swapper/2522:35:1518
9660659916573,74cyclictest0-21swapper/319:29:1923
9661239916478,57cyclictest0-21swapper/2219:44:2215
96612799162136,21cyclictest0-21swapper/2622:50:1619
96612799162136,21cyclictest0-21swapper/2622:50:1619
9660559916177,63cyclictest0-21swapper/100:30:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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