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2026-02-14 - 14:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackfslot0.osadl.org (updated Sat Feb 14, 2026 00:54:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
395114999174167,5cyclictest0-21swapper/2720:40:1620
395115399166154,10cyclictest0-21swapper/3119:14:0125
395114499166114,42cyclictest0-21swapper/2220:05:1815
395114499166114,42cyclictest0-21swapper/2220:05:1815
395114599159139,10cyclictest0-21swapper/2320:40:1616
39511409915978,74cyclictest0-21swapper/1820:15:1710
39511259915986,46cyclictest0-21swapper/1120:20:183
39511109915969,60cyclictest0-21swapper/722:55:1729
395114899157138,11cyclictest0-21swapper/2621:55:1619
39511519915689,3cyclictest0-21swapper/2919:10:1522
39511519915685,7cyclictest2218168-21kworker/u64:1+efi_rts_wq00:05:1722
39511479915587,38cyclictest0-21swapper/2521:59:3718
39511179915573,55cyclictest2218168-21kworker/u64:1+efi_rts_wq22:55:1731
395111599154145,5cyclictest0-21swapper/821:10:1430
395111599154145,5cyclictest0-21swapper/821:10:1430
395111599154138,4cyclictest0-21swapper/800:15:1830
39511479915375,48cyclictest0-21swapper/2520:25:1618
3951147991520,139cyclictest0-21swapper/2523:19:5618
3951147991520,139cyclictest0-21swapper/2523:19:5618
395115399150146,1cyclictest0-21swapper/3123:57:1325
3951147991500,148cyclictest0-21swapper/2520:40:1618
39511449915019,128cyclictest0-21swapper/2220:40:1615
395111599150121,16cyclictest0-21swapper/823:19:5630
395111599150121,16cyclictest0-21swapper/823:19:5630
395114699148128,13cyclictest0-21swapper/2420:30:1617
3951125991480,130cyclictest2218168-21kworker/u64:1+efi_rts_wq20:05:183
3951125991480,130cyclictest2218168-21kworker/u64:1+efi_rts_wq20:05:183
39511159914815,130cyclictest0-21swapper/820:40:1630
39511479914782,38cyclictest0-21swapper/2520:20:1818
39511529914663,54cyclictest0-21swapper/3022:55:1724
395114199146103,38cyclictest0-21swapper/1920:05:1811
395114199146103,38cyclictest0-21swapper/1920:05:1811
39511259914678,40cyclictest0-21swapper/1120:25:163
395115399145126,11cyclictest0-21swapper/3120:30:1625
39511479914569,46cyclictest0-21swapper/2520:50:1618
39511479914569,46cyclictest0-21swapper/2520:50:1618
395109799145121,15cyclictest0-21swapper/319:14:0123
39511409914475,64cyclictest0-21swapper/1823:40:1610
39511409914475,64cyclictest0-21swapper/1823:40:1610
39511389914460,55cyclictest0-21swapper/1622:55:178
39511379914486,3cyclictest0-21swapper/1519:10:157
39511369914372,49cyclictest0-21swapper/1400:05:176
39511309914380,37cyclictest0-21swapper/1220:25:164
395113399142126,11cyclictest0-21swapper/1320:30:165
395111599142115,19cyclictest0-21swapper/820:30:1630
39511109914061,70cyclictest2218168-21kworker/u64:1+efi_rts_wq21:35:1729
395114899139122,7cyclictest0-21swapper/2621:25:1519
395114199138132,4cyclictest0-21swapper/1922:00:5011
395114199138132,4cyclictest0-21swapper/1922:00:5011
39511259913865,44cyclictest0-21swapper/1122:45:173
39511009913886,10cyclictest2218168-21kworker/u64:1+efi_rts_wq23:15:1626
39511009913886,10cyclictest2218168-21kworker/u64:1+efi_rts_wq23:15:1626
395115399137135,1cyclictest0-21swapper/3120:48:0425
395115399137133,2cyclictest0-21swapper/3122:05:3425
395115399137133,2cyclictest0-21swapper/3122:05:3425
39511479913778,46cyclictest0-21swapper/2521:30:1618
395114199137135,1cyclictest0-21swapper/1922:09:0811
395114199137135,1cyclictest0-21swapper/1922:09:0811
395114199137132,3cyclictest0-21swapper/1923:18:4311
395114199137132,3cyclictest0-21swapper/1923:18:4311
395110499137127,8cyclictest0-21swapper/519:14:0127
395111599136133,1cyclictest0-21swapper/823:04:5130
39510909913682,20cyclictest0-21swapper/120:50:161
39510909913682,20cyclictest0-21swapper/120:50:161
395114699135133,1cyclictest0-21swapper/2419:10:0617
395114699135131,2cyclictest0-21swapper/2421:33:1917
395114199135131,3cyclictest0-21swapper/1922:46:3411
395111599135131,3cyclictest0-21swapper/821:40:1930
395115099134132,1cyclictest0-21swapper/2821:26:5121
39511409913477,55cyclictest0-21swapper/1820:20:1810
395111599134125,7cyclictest1295-21dbus-daemon23:29:2230
395111599134125,7cyclictest1295-21dbus-daemon23:29:2230
39510909913468,40cyclictest0-21swapper/123:20:151
39510909913468,40cyclictest0-21swapper/123:20:151
39511409913381,32cyclictest0-21swapper/1800:05:1710
39511399913379,44cyclictest0-21swapper/1723:19:569
39511399913379,44cyclictest0-21swapper/1723:19:569
39511369913380,35cyclictest0-21swapper/1400:25:166
39511369913380,35cyclictest0-21swapper/1400:25:166
39511159913391,36cyclictest0-21swapper/820:05:1830
39511159913391,36cyclictest0-21swapper/820:05:1830
395115399132129,1cyclictest0-21swapper/3122:55:2425
395114699132129,2cyclictest0-21swapper/2400:11:2317
395113399132129,2cyclictest0-21swapper/1320:16:545
39511259913269,50cyclictest0-21swapper/1121:15:163
39511259913269,50cyclictest0-21swapper/1121:15:163
39511179913260,56cyclictest0-21swapper/900:25:1631
39511179913260,56cyclictest0-21swapper/900:25:1631
395111599132128,3cyclictest0-21swapper/823:51:1330
395111599132128,3cyclictest0-21swapper/820:25:1330
395111599132127,4cyclictest0-21swapper/820:39:5230
395111599132126,4cyclictest0-21swapper/823:13:1830
395115399131128,2cyclictest0-21swapper/3120:56:3225
395115399131128,2cyclictest0-21swapper/3120:56:3225
395115099131126,1cyclictest0-21swapper/2823:49:0421
395115099131126,1cyclictest0-21swapper/2823:49:0421
39511409913173,46cyclictest0-21swapper/1821:25:1510
39511409913159,6cyclictest0-21swapper/1821:20:1710
39511409913159,6cyclictest0-21swapper/1821:20:1710
39511369913169,60cyclictest0-21swapper/1420:20:186
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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