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2026-01-21 - 14:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackfslot0.osadl.org (updated Wed Jan 21, 2026 00:54:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16912989917285,68cyclictest0-21swapper/3020:30:1524
16912869916780,70cyclictest0-21swapper/1819:30:1610
16912869916380,9cyclictest0-21swapper/1822:30:1610
16912869916380,9cyclictest0-21swapper/1822:30:1610
16912899916076,65cyclictest0-21swapper/2123:50:1614
16912899916076,65cyclictest0-21swapper/2123:50:1614
16912989915984,9cyclictest0-21swapper/3022:30:1624
16912989915984,9cyclictest0-21swapper/3022:30:1624
16912979915886,9cyclictest0-21swapper/2920:30:1422
16912909915879,6cyclictest0-21swapper/2200:25:1715
16912609915580,49cyclictest0-21swapper/819:30:1530
16912879915483,45cyclictest0-21swapper/1921:40:1711
16912699915377,5cyclictest0-21swapper/1119:30:153
16912569915382,47cyclictest0-21swapper/700:24:5729
16912959915179,58cyclictest0-21swapper/2720:30:1520
16912939915086,6cyclictest0-21swapper/2500:25:1618
16912839915076,52cyclictest0-21swapper/1522:45:167
16912839915076,52cyclictest0-21swapper/1522:45:167
16912989914978,8cyclictest0-21swapper/3022:50:1624
16912939914982,3cyclictest0-21swapper/2520:50:1518
16912929914970,61cyclictest0-21swapper/2423:50:1717
16912929914970,61cyclictest0-21swapper/2423:50:1717
16912909914974,9cyclictest0-21swapper/2220:50:1515
16912899914874,62cyclictest0-21swapper/2123:10:1614
16912999914778,50cyclictest0-21swapper/3122:45:1625
16912999914778,50cyclictest0-21swapper/3122:45:1625
16912959914773,54cyclictest0-21swapper/2722:45:1620
16912959914773,54cyclictest0-21swapper/2722:45:1620
16912989914672,6cyclictest0-21swapper/3000:25:1724
1691292991461,123cyclictest999786-21kworker/u64:0+efi_rts_wq22:45:1717
1691292991461,123cyclictest999786-21kworker/u64:0+efi_rts_wq22:45:1717
16912699914670,49cyclictest999786-21kworker/u64:0+efi_rts_wq22:50:163
16912609914681,8cyclictest0-21swapper/820:30:1430
16912999914584,51cyclictest0-21swapper/3120:30:1425
16912929914579,63cyclictest0-21swapper/2421:45:1617
16912869914583,31cyclictest0-21swapper/1819:25:1510
16912869914566,3cyclictest0-21swapper/1800:25:1710
169123499145141,2cyclictest0-21swapper/122:40:411
169123499145141,2cyclictest0-21swapper/122:40:411
16912869914481,7cyclictest0-21swapper/1820:30:1510
16912699914482,5cyclictest0-21swapper/1119:50:163
16912699914482,5cyclictest0-21swapper/1119:50:163
1691256991440,127cyclictest999786-21kworker/u64:0+efi_rts_wq22:25:1629
1691256991440,127cyclictest999786-21kworker/u64:0+efi_rts_wq22:25:1629
169129199142137,3cyclictest0-21swapper/2321:54:2516
16912789914270,53cyclictest0-21swapper/1322:45:165
16912789914270,53cyclictest0-21swapper/1322:45:165
16912789914176,51cyclictest0-21swapper/1320:30:155
16912529914187,44cyclictest0-21swapper/621:05:1728
16912529914187,44cyclictest0-21swapper/621:05:1728
16912839914082,49cyclictest0-21swapper/1520:30:147
169126399140121,11cyclictest0-21swapper/920:20:1531
16912909913986,9cyclictest0-21swapper/2222:25:1615
16912909913986,9cyclictest0-21swapper/2222:25:1615
16912899913964,64cyclictest999786-21kworker/u64:0+efi_rts_wq19:25:1614
16912899913960,6cyclictest0-21swapper/2119:30:1614
1691252991392,133cyclictest999786-21kworker/u64:0+efi_rts_wq21:30:1628
1691252991392,133cyclictest999786-21kworker/u64:0+efi_rts_wq21:30:1628
16912899913862,10cyclictest0-21swapper/2120:30:1514
16912569913873,58cyclictest0-21swapper/721:25:1629
16912569913873,58cyclictest0-21swapper/721:25:1629
16912529913856,62cyclictest0-21swapper/622:45:1728
16912529913856,62cyclictest0-21swapper/622:45:1628
169129399137115,12cyclictest0-21swapper/2520:20:1618
16912909913785,4cyclictest0-21swapper/2222:50:1615
16912979913685,10cyclictest0-21swapper/2922:30:1722
16912979913685,10cyclictest0-21swapper/2922:30:1722
1691297991361,96cyclictest999786-21kworker/u64:0+efi_rts_wq23:10:1622
16912969913664,51cyclictest0-21swapper/2822:45:1621
16912969913664,51cyclictest0-21swapper/2822:45:1621
16912879913678,46cyclictest999786-21kworker/u64:0+efi_rts_wq21:05:1611
16912879913678,46cyclictest999786-21kworker/u64:0+efi_rts_wq21:05:1611
16912869913662,10cyclictest0-21swapper/1820:50:1510
16912409913621,113cyclictest0-21swapper/319:30:1623
16912959913569,56cyclictest0-21swapper/2720:25:1620
169124799134128,4cyclictest0-21swapper/520:54:0227
16912919913377,32cyclictest0-21swapper/2322:25:1616
16912919913377,32cyclictest0-21swapper/2322:25:1616
16912869913373,8cyclictest0-21swapper/1822:50:1710
16912699913376,10cyclictest0-21swapper/1122:30:173
16912699913376,10cyclictest0-21swapper/1122:30:173
169123099133120,12cyclictest0-21swapper/022:25:200
169123099133120,12cyclictest0-21swapper/022:25:200
16912939913286,24cyclictest0-21swapper/2522:20:1618
16912939913286,24cyclictest0-21swapper/2522:20:1618
169129199132130,1cyclictest0-21swapper/2320:58:2116
169129199132130,1cyclictest0-21swapper/2320:58:2016
16912979913178,8cyclictest0-21swapper/2922:50:1622
16912929913154,51cyclictest999786-21kworker/u64:0+efi_rts_wq19:30:1517
16912869913182,19cyclictest0-21swapper/1821:15:1810
16912869913182,19cyclictest0-21swapper/1821:15:1710
169128599131124,6cyclictest0-21swapper/1719:30:169
169128499131123,6cyclictest0-21swapper/1623:35:448
169128499131123,6cyclictest0-21swapper/1623:35:448
16912839913172,49cyclictest0-21swapper/1520:25:157
169126699131122,2cyclictest0-21swapper/1023:18:002
16912569913164,52cyclictest0-21swapper/720:05:1529
16912569913164,52cyclictest0-21swapper/720:05:1529
169123099131124,4cyclictest0-21swapper/022:36:330
169123099131124,4cyclictest0-21swapper/022:36:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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