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2026-02-01 - 09:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackfslot0.osadl.org (updated Sun Feb 01, 2026 00:54:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63566099200161,13cyclictest0-21swapper/1019:46:172
63566099200161,13cyclictest0-21swapper/1019:46:172
635687991990,166cyclictest0-21swapper/1919:46:1711
635687991990,166cyclictest0-21swapper/1919:46:1711
63563699198150,2cyclictest0-21swapper/319:46:1723
63563699198150,2cyclictest0-21swapper/319:46:1723
63562999198161,11cyclictest0-21swapper/119:46:181
63562999198161,11cyclictest0-21swapper/119:46:181
635696991930,166cyclictest0-21swapper/2819:46:1721
635696991930,166cyclictest0-21swapper/2819:46:1721
63564899190153,9cyclictest670442-21gdbus19:46:1828
63564899190153,9cyclictest670442-21gdbus19:46:1728
635691991890,164cyclictest0-21swapper/2319:46:1716
635691991890,164cyclictest0-21swapper/2319:46:1716
63568699186148,13cyclictest0-21swapper/1819:46:1810
63568699186148,13cyclictest0-21swapper/1819:46:1810
63569499185136,8cyclictest0-21swapper/2619:46:1819
63569499185136,8cyclictest0-21swapper/2619:46:1819
63569099185150,9cyclictest0-21swapper/2219:46:1815
63569099185150,9cyclictest0-21swapper/2219:46:1715
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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