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2026-02-08 - 10:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackfslot0.osadl.org (updated Sun Feb 08, 2026 00:55:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
337049299211147,37cyclictest0-21swapper/2123:50:1114
337048499206141,3cyclictest0-21swapper/1323:50:115
337047599201141,2cyclictest0-21swapper/1023:50:112
337049399198162,17cyclictest0-21swapper/2223:50:1115
337045899196143,5cyclictest201rcu_preempt23:50:1128
3370444991960,174cyclictest0-21swapper/223:50:1212
3370483991920,171cyclictest0-21swapper/1223:50:114
3370468991883,157cyclictest0-21swapper/923:50:1231
3370487991870,2cyclictest3960827-21apt-get23:50:128
3370448991820,155cyclictest0-21swapper/323:50:1123
337046599181131,24cyclictest0-21swapper/823:50:1130
337050099179156,5cyclictest0-21swapper/2923:50:1122
33704889917982,64cyclictest0-21swapper/1722:03:079
33704889917982,64cyclictest0-21swapper/1722:03:079
337048599178145,5cyclictest0-21swapper/1423:50:116
33704909917788,59cyclictest0-21swapper/1900:35:1611
33704909917788,59cyclictest0-21swapper/1900:35:1611
337044099174138,12cyclictest0-21swapper/123:50:111
33704529917386,52cyclictest4046980-21uname00:35:1626
33704529917386,52cyclictest4046980-21uname00:35:1626
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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