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2026-01-18 - 08:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackfslot0.osadl.org (updated Sun Jan 18, 2026 00:54:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3488535992221,167cyclictest1295-21dbus-daemon00:36:3214
3488535992221,167cyclictest1295-21dbus-daemon00:36:3214
348850699222133,68cyclictest999786-21kworker/u64:0+efi_rts_wq00:36:3326
348850699222133,68cyclictest999786-21kworker/u64:0+efi_rts_wq00:36:3326
348854199219152,52cyclictest0-21swapper/2700:36:3320
348854199219152,52cyclictest0-21swapper/2700:36:3220
348851899213138,12cyclictest0-21swapper/700:36:3329
348851899213138,12cyclictest0-21swapper/700:36:3229
348852699209142,50cyclictest0-21swapper/1200:36:334
348852699209142,50cyclictest0-21swapper/1200:36:334
348849999208151,33cyclictest0-21swapper/200:36:3312
348849999208151,33cyclictest0-21swapper/200:36:3312
348852799204130,57cyclictest0-21swapper/1300:36:325
348852799204130,57cyclictest0-21swapper/1300:36:325
348854399202144,26cyclictest0-21swapper/2900:36:3322
348854399202144,26cyclictest0-21swapper/2900:36:3322
34885039919885,78cyclictest0-21swapper/322:33:2323
348853199192130,44cyclictest0-21swapper/1700:36:339
348853199192130,44cyclictest0-21swapper/1700:36:329
348849399190130,36cyclictest0-21swapper/000:36:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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