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2026-02-11 - 10:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackfslot0.osadl.org (updated Wed Feb 11, 2026 00:54:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157173799216146,59cyclictest0-21swapper/023:06:180
157173799216146,59cyclictest0-21swapper/023:06:170
157178899214130,70cyclictest787664-21kworker/u64:0+efi_rts_wq23:06:1825
157178899214130,70cyclictest787664-21kworker/u64:0+efi_rts_wq23:06:1825
157177299214168,16cyclictest0-21swapper/1523:06:187
157177299214168,16cyclictest0-21swapper/1523:06:187
157178599205160,17cyclictest0-21swapper/2823:06:1821
157178599205160,17cyclictest0-21swapper/2823:06:1821
157177999199132,53cyclictest0-21swapper/2223:06:1815
157177999199132,53cyclictest0-21swapper/2223:06:1815
157176999199128,57cyclictest0-21swapper/1223:06:184
157176999199128,57cyclictest0-21swapper/1223:06:184
1571778991970,172cyclictest0-21swapper/2123:06:1814
1571778991970,172cyclictest0-21swapper/2123:06:1814
157177799197154,14cyclictest0-21swapper/2023:06:1813
157177799197154,14cyclictest0-21swapper/2023:06:1813
157178399195167,5cyclictest0-21swapper/2623:06:1819
157178399195167,5cyclictest0-21swapper/2623:06:1819
157178299189121,38cyclictest0-21swapper/2523:06:1818
157178299189121,38cyclictest0-21swapper/2523:06:1818
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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