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2026-01-21 - 01:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackfslot0.osadl.org (updated Tue Jan 20, 2026 00:54:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
368716499167115,24cyclictest0-21swapper/122:03:301
368716499167115,24cyclictest0-21swapper/122:03:301
36872289916488,54cyclictest0-21swapper/2620:35:1719
36872249916283,50cyclictest0-21swapper/2223:40:1615
36872249916283,50cyclictest0-21swapper/2223:40:1615
36872299916083,14cyclictest0-21swapper/2720:05:1820
36872239915989,8cyclictest0-21swapper/2100:10:1714
36871869915983,5cyclictest0-21swapper/720:48:1129
36871869915983,5cyclictest0-21swapper/720:48:1129
36871739915989,7cyclictest0-21swapper/300:10:1723
36872289915869,57cyclictest999786-21kworker/u64:0+efi_rts_wq21:00:1819
36872289915869,57cyclictest999786-21kworker/u64:0+efi_rts_wq21:00:1819
36872229915881,53cyclictest0-21swapper/2020:35:1713
36871839915888,64cyclictest0-21swapper/623:55:1828
36871769915880,52cyclictest0-21swapper/422:13:3226
36871769915880,52cyclictest0-21swapper/422:13:3226
36871599915886,6cyclictest0-21swapper/020:48:110
36871599915886,6cyclictest0-21swapper/020:48:110
368723099157120,12cyclictest0-21swapper/2822:03:3021
368723099157120,12cyclictest0-21swapper/2822:03:3021
368722999157119,8cyclictest0-21swapper/2721:20:1620
3687225991550,140cyclictest0-21swapper/2322:10:1616
3687225991550,140cyclictest0-21swapper/2322:10:1616
3687224991550,1cyclictest0-21swapper/2221:50:1615
36872249915477,72cyclictest0-21swapper/2200:08:5915
36872209915482,4cyclictest0-21swapper/1800:10:1710
36871799915481,66cyclictest0-21swapper/500:08:5927
36871799915472,71cyclictest0-21swapper/519:32:5427
36871799915472,71cyclictest0-21swapper/519:32:5427
36871929915378,45cyclictest0-21swapper/921:00:1731
36871929915378,45cyclictest0-21swapper/921:00:1731
3687179991530,85cyclictest0-21swapper/523:40:1627
3687179991530,85cyclictest0-21swapper/523:40:1627
36871769915383,43cyclictest0-21swapper/423:45:1626
36872259915274,59cyclictest3977500-21sshd21:50:1616
36872229915282,56cyclictest999786-21kworker/u64:0+efi_rts_wq22:00:1713
36872229915282,56cyclictest999786-21kworker/u64:0+efi_rts_wq22:00:1713
36871769915277,50cyclictest0-21swapper/420:35:1826
36871599915269,11cyclictest999786-21kworker/u64:0+efi_rts_wq21:30:170
36871799915177,67cyclictest0-21swapper/500:35:1627
36871799915177,67cyclictest0-21swapper/500:35:1627
36871659915181,3cyclictest0-21swapper/220:48:1112
36871659915181,3cyclictest0-21swapper/220:48:1112
368715999151116,3cyclictest0-21swapper/021:20:160
36872119915073,58cyclictest0-21swapper/1400:00:186
368717399150118,2cyclictest0-21swapper/321:20:1623
36872049914983,11cyclictest0-21swapper/1320:20:175
36872209914885,4cyclictest0-21swapper/1820:48:1110
36872209914885,4cyclictest0-21swapper/1820:48:1110
36872339914778,57cyclictest0-21swapper/3100:35:1525
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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