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2026-08-04 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rackfslot5.osadl.org (updated Tue Aug 04, 2026 03:37:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31357991019510182,8cyclictest0-21swapper/102:59:181
31356991018910130,54cyclictest13572-21kworker/0:3+events02:59:180
31356991009410025,63cyclictest7953-21kworker/0:6+events03:34:520
31359991009210083,5cyclictest0-21swapper/302:59:193
3135899100099999,5cyclictest0-21swapper/202:59:182
313599999919978,8cyclictest0-21swapper/303:34:523
313579998889877,5cyclictest0-21swapper/103:34:521
313589997029694,3cyclictest0-21swapper/203:34:522
3135799756744,7cyclictest0-21swapper/102:38:121
3135799749737,7cyclictest0-21swapper/102:49:101
3135799744732,7cyclictest0-21swapper/103:11:061
3135799737725,7cyclictest0-21swapper/103:22:041
3135799737725,7cyclictest0-21swapper/103:22:041
3135799735723,7cyclictest0-21swapper/103:00:091
3135699718691,22cyclictest23690-21kworker/0:0+events_freezable_power_02:38:120
3135699712684,23cyclictest26870-21kworker/0:1+events_freezable_power_02:49:110
3135699712680,26cyclictest23690-21kworker/0:0+events_freezable_power_03:11:060
3135699701673,23cyclictest13572-21kworker/0:3+events_freezable_power_03:22:040
3135699701673,23cyclictest13572-21kworker/0:3+events_freezable_power_03:22:040
3135699701671,25cyclictest18829-21kworker/0:5+events_freezable_power_03:00:080
3135999654645,5cyclictest0-21swapper/302:38:123
3135999646637,5cyclictest0-21swapper/302:49:103
3135999642633,5cyclictest0-21swapper/303:11:063
3135999635626,5cyclictest0-21swapper/303:22:053
3135999635626,5cyclictest0-21swapper/303:22:043
3135999634624,5cyclictest0-21swapper/303:00:083
3135899575561,7cyclictest0-21swapper/202:38:122
3135899568554,7cyclictest0-21swapper/202:49:112
3135899560550,5cyclictest0-21swapper/203:11:072
3135899556542,7cyclictest0-21swapper/203:22:042
3135899556542,7cyclictest0-21swapper/203:22:042
3135899555540,8cyclictest0-21swapper/203:00:082
3135699602,54cyclictest8509-21ld03:06:280
31356995639,5cyclictest15350irq/419-imx_drm03:30:000
31356995538,5cyclictest15350irq/419-imx_drm03:15:330
31359994939,6cyclictest0-21swapper/303:15:373
31359994837,7cyclictest0-21swapper/303:05:543
31359994835,7cyclictest0-21swapper/303:25:363
31356994830,6cyclictest9450irq/76-5b050000.ethernet02:40:370
31357994739,5cyclictest0-21swapper/103:28:241
31357994638,5cyclictest0-21swapper/103:15:301
31357994638,5cyclictest0-21swapper/103:05:581
31358994335,5cyclictest0-21swapper/203:06:282
3135799431,5cyclictest0-21swapper/102:51:371
31358994133,5cyclictest0-21swapper/203:25:262
3135899402,34cyclictest0-21swapper/202:40:252
3135899401,5cyclictest0-21swapper/203:16:352
3135799402,5cyclictest0-21swapper/102:30:351
3135899383,6cyclictest0-21swapper/202:53:192
3135899372,12cyclictest0-21swapper/202:32:512
31359993625,7cyclictest0-21swapper/302:30:273
3135799361,5cyclictest0-21swapper/102:40:361
31359993525,7cyclictest0-21swapper/302:50:413
31356993526,6cyclictest9450irq/76-5b050000.ethernet02:50:420
31356993526,6cyclictest9450irq/76-5b050000.ethernet02:30:410
31359993223,5cyclictest0-21swapper/302:40:163
31359993015,10cyclictest0-21swapper/302:30:003
3135699272,21cyclictest31369-21sort02:30:010
3135899262,6cyclictest0-21swapper/202:30:012
3135799242,5cyclictest0-21swapper/102:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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