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2026-03-09 - 14:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rackfslot5.osadl.org (updated Mon Mar 09, 2026 03:37:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2880991025310241,7cyclictest0-21swapper/102:59:181
2879991023610184,47cyclictest2348-21kworker/0:3+events02:59:170
2882991023110220,6cyclictest0-21swapper/302:59:183
2881991004510035,5cyclictest0-21swapper/202:59:182
28809985168504,7cyclictest0-21swapper/103:34:521
28809985168504,7cyclictest0-21swapper/103:34:521
28799984958448,42cyclictest16495-21kworker/0:1+events03:34:520
28799984958448,42cyclictest16495-21kworker/0:1+events03:34:520
28829984948483,5cyclictest0-21swapper/303:34:523
28829984948483,5cyclictest0-21swapper/303:34:523
28819983098299,5cyclictest0-21swapper/203:34:522
28819983098299,5cyclictest0-21swapper/203:34:522
287999787749,33cyclictest27493-21kworker/0:0+events_freezable_power_02:43:240
287999782743,34cyclictest2348-21kworker/0:3+events_freezable_power_03:27:160
288099758746,7cyclictest0-21swapper/102:32:251
288099743731,7cyclictest0-21swapper/102:54:221
288299735725,5cyclictest0-21swapper/302:32:253
288099733720,7cyclictest0-21swapper/103:16:181
288299720710,5cyclictest0-21swapper/302:54:223
287999715690,20cyclictest27493-21kworker/0:0+events_freezable_power_02:32:260
288299708699,5cyclictest0-21swapper/303:16:183
287999697675,17cyclictest27493-21kworker/0:0+events_freezable_power_02:54:220
287999686664,17cyclictest656-21kworker/0:2+events_freezable_power_03:16:180
288099680670,5cyclictest0-21swapper/103:05:201
288299657650,3cyclictest0-21swapper/303:05:193
287999635614,15cyclictest16495-21kworker/0:1+events_freezable_power_03:05:200
288199610600,5cyclictest0-21swapper/202:43:242
288099610600,5cyclictest0-21swapper/103:27:161
288299592585,3cyclictest0-21swapper/302:43:243
288299586579,3cyclictest0-21swapper/303:27:163
288199555541,7cyclictest0-21swapper/202:32:262
288199541526,8cyclictest0-21swapper/202:54:222
288199530515,8cyclictest0-21swapper/203:16:182
288199475465,5cyclictest0-21swapper/203:05:202
288099420405,8cyclictest0-21swapper/102:43:241
288199408395,8cyclictest0-21swapper/203:27:162
2879994941,5cyclictest15350irq/419-imx_drm03:10:310
2882994839,5cyclictest0-21swapper/303:10:363
2879994739,5cyclictest15350irq/419-imx_drm03:20:370
2879994739,5cyclictest15350irq/419-imx_drm03:20:370
2882994637,5cyclictest0-21swapper/303:20:333
2882994637,5cyclictest0-21swapper/303:20:333
2882994637,5cyclictest0-21swapper/303:05:023
2882994536,5cyclictest0-21swapper/302:50:023
2880994537,5cyclictest0-21swapper/103:20:381
2880994537,5cyclictest0-21swapper/103:20:381
2880994537,5cyclictest0-21swapper/103:10:361
2879994537,5cyclictest15350irq/419-imx_drm02:50:030
2881994436,5cyclictest0-21swapper/203:10:362
2880994436,5cyclictest0-21swapper/102:50:001
2879994436,5cyclictest15350irq/419-imx_drm03:05:020
2880994335,5cyclictest0-21swapper/103:05:061
288099412,35cyclictest0-21swapper/102:35:471
288199402,5cyclictest0-21swapper/203:20:442
288199402,5cyclictest0-21swapper/203:20:442
288199402,5cyclictest0-21swapper/202:45:182
2880994025,11cyclictest0-21swapper/102:30:021
288199392,5cyclictest0-21swapper/202:37:002
288199372,31cyclictest0-21swapper/202:30:022
2882993627,5cyclictest0-21swapper/302:35:223
288199344,27cyclictest17592irq/55-edma2-chan7-tx03:00:472
2879993425,6cyclictest9450irq/76-5b050000.ethernet02:35:380
2882992819,5cyclictest0-21swapper/302:30:003
287999271,23cyclictest2944-21cat02:30:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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