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2026-08-25 - 09:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rackfslot5.osadl.org (updated Tue Aug 25, 2026 03:37:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
451199100559968,82cyclictest2256-21kworker/0:0+events02:59:190
45149998859875,5cyclictest0-21swapper/302:59:203
45129998359826,4cyclictest0-21swapper/102:59:201
45139998349824,5cyclictest0-21swapper/202:59:192
451299746734,7cyclictest0-21swapper/102:33:591
451399742732,5cyclictest0-21swapper/202:33:592
451299740728,7cyclictest0-21swapper/103:28:501
451299739727,7cyclictest0-21swapper/102:44:581
451299737725,7cyclictest0-21swapper/103:06:541
451399736726,5cyclictest0-21swapper/203:28:492
451399735725,5cyclictest0-21swapper/202:44:572
451299734722,7cyclictest0-21swapper/103:17:511
451399733723,5cyclictest0-21swapper/203:06:532
451399730720,5cyclictest0-21swapper/203:17:522
451199696676,15cyclictest18015-21kworker/0:5+events_freezable_power_02:33:590
451199691670,16cyclictest19788-21kworker/0:3+events_freezable_power_03:28:490
451199690669,16cyclictest2527-21kworker/0:2+events_freezable_power_02:44:570
451199688667,16cyclictest18015-21kworker/0:5+events_freezable_power_03:06:530
451199685664,16cyclictest2527-21kworker/0:2+events_freezable_power_03:17:520
451499595583,7cyclictest0-21swapper/302:34:003
451499588577,7cyclictest0-21swapper/303:28:503
451499587576,7cyclictest0-21swapper/302:44:573
451499586572,7cyclictest0-21swapper/303:17:513
451499585574,7cyclictest0-21swapper/303:06:533
4511996435,5cyclictest15350irq/419-imx_drm03:20:420
4511996435,5cyclictest15350irq/419-imx_drm03:20:410
451199642,10cyclictest15175-21irqstats03:10:290
4511996236,5cyclictest15350irq/419-imx_drm03:30:330
4511996010,29cyclictest13447-21wc03:05:060
4511995734,5cyclictest15350irq/419-imx_drm02:50:080
4511995734,5cyclictest15350irq/419-imx_drm02:50:070
4511995434,5cyclictest15350irq/419-imx_drm02:50:120
4511995434,5cyclictest15350irq/419-imx_drm02:50:110
4512995143,5cyclictest0-21swapper/103:10:341
4513994941,5cyclictest0-21swapper/203:10:352
4512994941,5cyclictest0-21swapper/103:30:561
4514994839,5cyclictest0-21swapper/303:30:293
4514994839,5cyclictest0-21swapper/303:11:033
4514994839,5cyclictest0-21swapper/303:05:033
4512994840,5cyclictest0-21swapper/103:23:351
4512994840,5cyclictest0-21swapper/103:23:341
4514994637,5cyclictest0-21swapper/303:20:403
4514994637,5cyclictest0-21swapper/303:20:403
451399466,34cyclictest17592irq/55-edma2-chan7-tx03:30:222
4512994638,5cyclictest0-21swapper/103:05:061
451399456,5cyclictest0-21swapper/203:00:532
4514994434,5cyclictest0-21swapper/302:50:083
4514994434,5cyclictest0-21swapper/302:50:083
4513994437,4cyclictest0-21swapper/203:23:342
4513994437,4cyclictest0-21swapper/203:23:342
4513994434,5cyclictest0-21swapper/202:50:102
4513994434,5cyclictest0-21swapper/202:50:102
4512994335,5cyclictest0-21swapper/102:50:111
4512994335,5cyclictest0-21swapper/102:50:101
4512994334,5cyclictest0-21swapper/102:50:021
4512994334,5cyclictest0-21swapper/102:50:021
4514994234,5cyclictest0-21swapper/302:50:113
4514994234,5cyclictest0-21swapper/302:50:103
4513994233,5cyclictest0-21swapper/202:50:112
4513994233,5cyclictest0-21swapper/202:50:102
451399376,5cyclictest0-21swapper/202:35:242
4514993425,5cyclictest0-21swapper/302:35:263
4511993424,7cyclictest9450irq/76-5b050000.ethernet02:35:100
4512993325,5cyclictest0-21swapper/102:35:191
4511993324,6cyclictest9450irq/76-5b050000.ethernet02:30:030
451399326,5cyclictest0-21swapper/202:30:022
4512992719,5cyclictest0-21swapper/102:30:001
4514992617,5cyclictest0-21swapper/302:30:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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