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2026-07-12 - 06:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rackfslot5.osadl.org (updated Sun Jul 12, 2026 03:37:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15244991428214269,8cyclictest0-21swapper/203:34:262
15244991428214269,8cyclictest0-21swapper/203:34:262
15243991427214260,6cyclictest0-21swapper/103:34:261
15243991427214260,6cyclictest0-21swapper/103:34:251
15245991426514258,2cyclictest0-21swapper/303:34:263
15245991426514258,2cyclictest0-21swapper/303:34:263
15242991425214202,45cyclictest10588-21kworker/0:5+events03:34:260
15242991425214202,45cyclictest10588-21kworker/0:5+events03:34:260
15242991038410318,61cyclictest14257-21kworker/0:3+events02:59:180
15243991019010177,8cyclictest0-21swapper/102:59:191
15245991018410175,5cyclictest0-21swapper/302:59:193
152449999969986,5cyclictest0-21swapper/202:59:192
1524299804764,34cyclictest25319-21kworker/0:4+events_freezable_power_03:21:510
1524299800763,32cyclictest14257-21kworker/0:3+events_freezable_power_02:37:590
1524299794755,34cyclictest6312-21kworker/0:1+events_freezable_power_02:48:570
1524299794755,34cyclictest6312-21kworker/0:1+events_freezable_power_02:48:560
1524399696686,5cyclictest0-21swapper/103:10:531
1524399696686,5cyclictest0-21swapper/103:10:531
1524599692685,3cyclictest0-21swapper/303:10:533
1524599692685,3cyclictest0-21swapper/303:10:533
1524299649628,15cyclictest6312-21kworker/0:1+events_freezable_power_03:10:530
1524299649628,15cyclictest6312-21kworker/0:1+events_freezable_power_03:10:520
1524499642632,5cyclictest0-21swapper/203:21:512
1524599633621,8cyclictest0-21swapper/303:21:503
1524499633623,5cyclictest0-21swapper/202:48:572
1524499633623,5cyclictest0-21swapper/202:48:562
1524399631621,5cyclictest0-21swapper/102:37:581
1524399630622,3cyclictest0-21swapper/103:21:511
1524599627620,3cyclictest0-21swapper/302:37:583
1524599627612,8cyclictest0-21swapper/302:48:573
1524599627612,8cyclictest0-21swapper/302:48:573
1524399622614,3cyclictest0-21swapper/102:48:571
1524399622614,3cyclictest0-21swapper/102:48:571
1524499505495,5cyclictest0-21swapper/203:10:532
1524499505495,5cyclictest0-21swapper/203:10:522
1524499446431,8cyclictest0-21swapper/202:37:592
15245996758,5cyclictest0-21swapper/303:15:373
15245996354,5cyclictest0-21swapper/303:05:543
15245995647,5cyclictest0-21swapper/302:30:123
15245995546,5cyclictest0-21swapper/303:25:273
15245995546,5cyclictest0-21swapper/303:00:593
15245995546,5cyclictest0-21swapper/302:50:493
15242995237,5cyclictest15350irq/419-imx_drm03:25:450
15242995136,5cyclictest15350irq/419-imx_drm03:15:070
15245994940,5cyclictest0-21swapper/302:40:173
15242994940,5cyclictest15350irq/419-imx_drm03:05:540
15244994838,5cyclictest0-21swapper/203:25:272
15244994737,5cyclictest0-21swapper/203:15:082
15243994739,5cyclictest0-21swapper/103:25:121
15243994739,5cyclictest0-21swapper/103:05:271
15243994739,5cyclictest0-21swapper/103:00:081
15245994637,5cyclictest0-21swapper/302:30:013
15245994637,5cyclictest0-21swapper/302:30:013
15243994638,5cyclictest0-21swapper/103:15:231
15244994536,5cyclictest0-21swapper/203:05:322
15242994537,5cyclictest15350irq/419-imx_drm03:05:050
15244994436,5cyclictest0-21swapper/203:05:022
15243994436,5cyclictest0-21swapper/102:30:391
15243994435,5cyclictest0-21swapper/102:45:011
15242994427,14cyclictest1621-21lldpd02:30:460
15243994133,5cyclictest0-21swapper/102:50:361
15244993830,5cyclictest0-21swapper/202:50:182
15242993627,6cyclictest9450irq/76-5b050000.ethernet02:40:170
1524299361,31cyclictest20467-21mousedance02:50:070
1524499352,30cyclictest0-21swapper/202:42:282
15244993426,5cyclictest0-21swapper/202:30:402
1524399322,5cyclictest0-21swapper/102:30:011
1524399322,5cyclictest0-21swapper/102:30:011
15244992712,1cyclictest17592irq/55-edma2-chan7-tx02:30:022
15244992712,1cyclictest17592irq/55-edma2-chan7-tx02:30:012
15242992617,5cyclictest15288-21latency_hist02:30:000
15242992617,5cyclictest15288-21latency_hist02:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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