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2026-01-12 - 17:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rackfslot5.osadl.org (updated Mon Jan 12, 2026 15:37:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27518991023310166,62cyclictest9591-21kworker/0:5+events15:34:180
27518991023310166,62cyclictest9591-21kworker/0:5+events15:34:170
27520991010110088,7cyclictest0-21swapper/215:34:182
27520991010110088,7cyclictest0-21swapper/215:34:182
27521991008810079,5cyclictest0-21swapper/315:34:183
27521991008810079,5cyclictest0-21swapper/315:34:183
27519991003010021,4cyclictest0-21swapper/115:34:181
27519991003010021,4cyclictest0-21swapper/115:34:181
2751899795752,36cyclictest23187-21kworker/0:1+events_freezable_power_15:20:190
2751899795752,36cyclictest23187-21kworker/0:1+events_freezable_power_15:20:190
2751899769730,33cyclictest23187-21kworker/0:1+events_freezable_power_15:09:210
2751899766732,29cyclictest30382-21kworker/0:4+events_freezable_power_14:47:250
2751899753712,35cyclictest27645-21kworker/0:2+events_freezable_power_14:36:260
2751899751712,33cyclictest23187-21kworker/0:1+events_freezable_power_14:58:230
2752099686674,7cyclictest0-21swapper/215:20:192
2752099686674,7cyclictest0-21swapper/215:20:192
2752199676665,5cyclictest0-21swapper/315:20:193
2752199676665,5cyclictest0-21swapper/315:20:193
2752099668655,7cyclictest0-21swapper/214:47:252
2752099664652,7cyclictest0-21swapper/215:09:202
2752199657646,5cyclictest0-21swapper/314:47:243
2752199653643,5cyclictest0-21swapper/315:09:213
2752099646634,7cyclictest0-21swapper/214:58:232
2752099646634,7cyclictest0-21swapper/214:36:262
2752199636626,5cyclictest0-21swapper/314:36:273
2752199635625,5cyclictest0-21swapper/314:58:223
2751999617607,5cyclictest0-21swapper/115:20:191
2751999617607,5cyclictest0-21swapper/115:20:181
2751999602588,7cyclictest0-21swapper/114:47:251
2751999594585,4cyclictest0-21swapper/115:09:211
2751999578568,5cyclictest0-21swapper/114:36:271
2751999576567,4cyclictest0-21swapper/114:58:231
2752099562,50cyclictest17592irq/55-edma2-chan7-tx15:20:002
27520995237,9cyclictest0-21swapper/215:10:442
27520995237,9cyclictest0-21swapper/215:10:442
2752099522,42cyclictest17592irq/55-edma2-chan7-tx14:40:202
27518995233,16cyclictest15350irq/419-imx_drm15:25:240
27520995038,9cyclictest0-21swapper/215:27:352
27519994941,5cyclictest0-21swapper/115:10:161
27519994941,5cyclictest0-21swapper/115:10:161
27521994837,7cyclictest0-21swapper/315:10:363
27521994837,7cyclictest0-21swapper/315:10:363
27518994840,5cyclictest15350irq/419-imx_drm15:10:410
27518994840,5cyclictest15350irq/419-imx_drm15:10:400
27521994736,7cyclictest0-21swapper/315:15:053
2752099472,2cyclictest17592irq/55-edma2-chan7-tx14:30:172
27519994739,5cyclictest0-21swapper/115:26:221
27519994739,5cyclictest0-21swapper/115:15:311
27521994634,7cyclictest0-21swapper/315:26:573
27519994638,5cyclictest0-21swapper/115:05:031
27518994638,5cyclictest15350irq/419-imx_drm15:16:030
2752099452,3cyclictest17592irq/55-edma2-chan7-tx14:51:102
2752099448,12cyclictest0-21swapper/215:00:562
2751899442,7cyclictest3918-21latency_hist15:05:030
2752099392,8cyclictest17592irq/55-edma2-chan7-tx14:30:022
27521993625,7cyclictest0-21swapper/314:40:183
2751999362,30cyclictest0-21swapper/114:30:411
27518993627,6cyclictest9450irq/76-5b050000.ethernet14:40:320
27518993627,6cyclictest9450irq/76-5b050000.ethernet14:30:230
27521993526,5cyclictest0-21swapper/314:50:073
27519993527,5cyclictest0-21swapper/114:40:211
27521993425,5cyclictest0-21swapper/314:34:083
27518993425,6cyclictest9450irq/76-5b050000.ethernet14:50:280
27519993325,5cyclictest0-21swapper/114:50:131
27521993224,4cyclictest0-21swapper/315:05:023
2751999292,24cyclictest0-21swapper/114:30:021
2751899282,7cyclictest27542-21sed14:30:020
27521992515,5cyclictest0-21swapper/314:30:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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