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2026-01-26 - 09:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot5.osadl.org (updated Mon Jan 26, 2026 00:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2085899989977,7cyclictest0-21swapper/222:39:282
2085799959949,5cyclictest0-21swapper/122:39:281
2085699934905,24cyclictest11967-21kworker/0:6+events_freezable_power_22:39:290
2085699797751,39cyclictest8123-21kworker/0:3+events_freezable_power_23:45:160
2085699778734,38cyclictest32599-21kworker/0:2+events_freezable_power_21:00:470
2085999776767,5cyclictest0-21swapper/322:39:283
2085899776764,7cyclictest0-21swapper/219:33:022
2085899775763,7cyclictest0-21swapper/223:12:222
2085899774762,7cyclictest0-21swapper/200:29:092
2085899773760,7cyclictest0-21swapper/200:07:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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