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2026-02-10 - 02:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot5.osadl.org (updated Mon Feb 09, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1626699925913,7cyclictest0-21swapper/308:39:523
1626699925913,7cyclictest0-21swapper/308:39:513
1626499913903,5cyclictest0-21swapper/108:39:511
1626499913903,5cyclictest0-21swapper/108:39:511
1626399873851,17cyclictest2237-21kworker/0:1+events_freezable_power_08:39:520
1626399873851,17cyclictest2237-21kworker/0:1+events_freezable_power_08:39:520
1626599858848,5cyclictest0-21swapper/208:39:522
1626599858848,5cyclictest0-21swapper/208:39:522
1626699754740,9cyclictest0-21swapper/309:45:403
1626699754740,9cyclictest0-21swapper/309:45:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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