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2026-01-30 - 19:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5.osadl.org (updated Fri Jan 30, 2026 12:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
367599769756,8cyclictest0-21swapper/307:45:263
367499764754,5cyclictest0-21swapper/207:45:272
367299764723,35cyclictest14740-21kworker/0:3+events_freezable_power_07:34:280
367299764723,35cyclictest14740-21kworker/0:3+events_freezable_power_07:34:280
367399753745,3cyclictest0-21swapper/107:45:261
367299753714,34cyclictest11668-21kworker/0:7+events_freezable_power_08:40:170
367599747735,7cyclictest0-21swapper/312:08:393
367599747735,7cyclictest0-21swapper/311:57:403
367599747735,7cyclictest0-21swapper/308:29:183
367599745734,7cyclictest0-21swapper/309:35:063
367599744732,7cyclictest0-21swapper/312:19:373
367599743731,7cyclictest0-21swapper/308:07:223
367499743733,5cyclictest0-21swapper/212:08:392
367499742732,5cyclictest0-21swapper/211:57:412
367499742732,5cyclictest0-21swapper/208:29:182
367599741729,7cyclictest0-21swapper/309:57:023
367599741729,7cyclictest0-21swapper/308:51:153
367599741727,8cyclictest0-21swapper/311:35:443
367499741731,5cyclictest0-21swapper/209:35:072
367599739727,7cyclictest0-21swapper/311:46:433
367499739729,5cyclictest0-21swapper/212:19:372
367599738726,7cyclictest0-21swapper/310:18:593
367499738728,5cyclictest0-21swapper/208:07:222
367599737727,5cyclictest0-21swapper/312:30:353
367599737725,7cyclictest0-21swapper/311:02:503
367499737727,5cyclictest0-21swapper/209:57:032
367599736724,7cyclictest0-21swapper/309:24:093
367599735723,7cyclictest0-21swapper/307:12:323
367599735723,7cyclictest0-21swapper/307:12:323
367499735725,5cyclictest0-21swapper/211:46:432
367499735724,5cyclictest0-21swapper/211:35:452
367499734726,3cyclictest0-21swapper/208:51:142
367499734724,5cyclictest0-21swapper/210:18:582
367499733725,3cyclictest0-21swapper/212:30:342
367599732720,7cyclictest0-21swapper/308:18:203
367499732722,5cyclictest0-21swapper/211:02:502
367499732722,5cyclictest0-21swapper/209:24:082
367399732724,3cyclictest0-21swapper/112:08:391
367599731719,7cyclictest0-21swapper/309:46:053
367599731719,7cyclictest0-21swapper/307:23:303
367499731721,5cyclictest0-21swapper/207:12:322
367499731721,5cyclictest0-21swapper/207:12:322
367399731723,3cyclictest0-21swapper/111:57:411
367399731723,3cyclictest0-21swapper/108:29:181
367599730718,7cyclictest0-21swapper/309:02:123
367399730722,3cyclictest0-21swapper/109:35:061
367599729717,7cyclictest0-21swapper/310:40:543
367599729717,7cyclictest0-21swapper/310:40:543
367499728718,5cyclictest0-21swapper/208:18:202
367399728720,3cyclictest0-21swapper/112:19:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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