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2026-01-15 - 21:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5.osadl.org (updated Thu Jan 15, 2026 12:46:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1766099983971,7cyclictest0-21swapper/210:03:152
1765999972962,5cyclictest0-21swapper/110:03:151
1766199955948,3cyclictest0-21swapper/310:03:153
1765899923908,10cyclictest9014-21kworker/0:0+events_freezable_power_10:03:150
1766099777765,7cyclictest0-21swapper/208:46:282
1766099773760,7cyclictest0-21swapper/210:47:062
1766099772760,7cyclictest0-21swapper/212:36:472
1766099770758,7cyclictest0-21swapper/212:14:502
1766099770758,7cyclictest0-21swapper/212:14:502
1766099766754,7cyclictest0-21swapper/208:57:272
1766099766754,7cyclictest0-21swapper/208:57:272
1765999766756,5cyclictest0-21swapper/108:46:291
1766199765752,8cyclictest0-21swapper/311:20:003
1766099764752,7cyclictest0-21swapper/209:41:192
1766099764752,7cyclictest0-21swapper/208:24:322
1766099763751,7cyclictest0-21swapper/210:36:092
1766099762750,7cyclictest0-21swapper/211:09:022
1766099762750,7cyclictest0-21swapper/210:58:042
1765999761751,5cyclictest0-21swapper/112:36:461
1765999761751,5cyclictest0-21swapper/110:47:061
1766099760748,7cyclictest0-21swapper/211:52:542
1766099759747,7cyclictest0-21swapper/212:03:532
1766099759747,7cyclictest0-21swapper/207:51:382
1765999758748,5cyclictest0-21swapper/112:14:511
1765999758748,5cyclictest0-21swapper/112:14:501
1766099756744,7cyclictest0-21swapper/210:14:132
1766099756743,7cyclictest0-21swapper/209:19:232
1766099755742,7cyclictest0-21swapper/208:02:362
1765999755745,5cyclictest0-21swapper/108:57:261
1765999755745,5cyclictest0-21swapper/108:57:261
1766099753741,7cyclictest0-21swapper/208:13:352
1766099753741,7cyclictest0-21swapper/208:13:352
1765999753743,5cyclictest0-21swapper/109:41:191
1766099752740,7cyclictest0-21swapper/207:29:422
1766099752740,7cyclictest0-21swapper/207:18:452
1766099752740,7cyclictest0-21swapper/207:18:452
1765999752742,5cyclictest0-21swapper/110:36:091
1765999752742,5cyclictest0-21swapper/108:24:331
1766099751739,7cyclictest0-21swapper/211:41:562
1765999751741,5cyclictest0-21swapper/111:09:021
1765899751712,32cyclictest9014-21kworker/0:0+events_freezable_power_11:20:000
1766199750739,7cyclictest0-21swapper/308:35:303
1765999750740,5cyclictest0-21swapper/110:58:041
1766199749738,7cyclictest0-21swapper/310:25:113
1766099749737,7cyclictest0-21swapper/209:08:252
1765999749739,5cyclictest0-21swapper/111:52:541
1766199748741,3cyclictest0-21swapper/308:46:293
1766099748736,7cyclictest0-21swapper/209:52:172
1766099748736,7cyclictest0-21swapper/209:52:162
1766099747735,7cyclictest0-21swapper/211:30:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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