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2026-03-01 - 19:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5.osadl.org (updated Sun Mar 01, 2026 12:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2656199991954,32cyclictest18738-21kworker/0:5+events_freezable_power_11:56:290
2656499903891,7cyclictest0-21swapper/311:56:293
2656399838823,8cyclictest0-21swapper/211:56:292
2656299834826,3cyclictest0-21swapper/111:56:291
2656199799759,34cyclictest18738-21kworker/0:5+events_freezable_power_12:18:250
2656199799759,34cyclictest18738-21kworker/0:5+events_freezable_power_12:18:250
2656199791749,37cyclictest15720-21kworker/0:0+events_freezable_power_09:12:000
2656199789750,33cyclictest15720-21kworker/0:0+events_freezable_power_10:28:460
2656199788748,34cyclictest29033-21kworker/0:2+events_freezable_power_09:44:540
2656199787747,34cyclictest12423-21kworker/0:5+events_freezable_power_07:44:150
2656199787744,37cyclictest15720-21kworker/0:0+events_freezable_power_09:55:510
2656199786746,34cyclictest12423-21kworker/0:5+events_freezable_power_08:28:080
2656199785749,31cyclictest23463-21kworker/0:4+events_freezable_power_10:06:500
2656199783747,31cyclictest19022-21kworker/0:1+events_freezable_power_09:01:010
2656199783743,34cyclictest29033-21kworker/0:2+events_freezable_power_09:33:560
2656199781745,31cyclictest5085-21kworker/0:3+events_freezable_power_08:17:100
2656199780740,34cyclictest15720-21kworker/0:0+events_freezable_power_10:17:480
2656199780740,34cyclictest15720-21kworker/0:0+events_freezable_power_10:17:470
2656199779739,34cyclictest25578-21kworker/0:0+events_freezable_power_07:33:180
2656199779739,34cyclictest25578-21kworker/0:0+events_freezable_power_07:33:180
2656199777737,34cyclictest5085-21kworker/0:3+events_freezable_power_08:06:110
2656199775735,34cyclictest19022-21kworker/0:1+events_freezable_power_11:01:400
2656199773735,32cyclictest23463-21kworker/0:4+events_freezable_power_10:39:440
2656199773735,32cyclictest23463-21kworker/0:4+events_freezable_power_10:39:440
2656199773733,34cyclictest29033-21kworker/0:2+events_freezable_power_07:22:190
2656199772735,32cyclictest15720-21kworker/0:0+events_freezable_power_11:23:360
2656499771759,7cyclictest0-21swapper/308:50:043
2656199771730,35cyclictest15245-21kworker/0:4+events_freezable_power_07:11:210
2656499770758,7cyclictest0-21swapper/312:07:273
2656199770729,35cyclictest12423-21kworker/0:5+events_freezable_power_08:39:050
2656199768728,34cyclictest19022-21kworker/0:1+events_freezable_power_11:12:370
2656199766728,32cyclictest23463-21kworker/0:4+events_freezable_power_09:22:580
2656199766728,32cyclictest23463-21kworker/0:4+events_freezable_power_09:22:580
2656199763723,34cyclictest18738-21kworker/0:5+events_freezable_power_11:34:330
2656199757720,32cyclictest23463-21kworker/0:4+events_freezable_power_12:29:230
2656499749736,8cyclictest0-21swapper/311:45:313
2656499748734,9cyclictest0-21swapper/307:55:133
2656499748734,9cyclictest0-21swapper/307:55:133
2656499742733,5cyclictest0-21swapper/310:50:423
2656499708696,7cyclictest0-21swapper/312:18:263
2656499708696,7cyclictest0-21swapper/312:18:253
2656299703694,4cyclictest0-21swapper/108:50:031
2656299702693,4cyclictest0-21swapper/112:07:271
2656399701691,5cyclictest0-21swapper/208:50:042
2656399700690,5cyclictest0-21swapper/212:07:272
2656499699687,7cyclictest0-21swapper/310:28:463
2656499699687,7cyclictest0-21swapper/309:11:593
2656499698687,7cyclictest0-21swapper/310:06:493
2656499697685,7cyclictest0-21swapper/309:44:543
2656499696684,7cyclictest0-21swapper/309:01:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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