You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-13 - 13:34
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of all highest latencies:
System rackfslot5.osadl.org (updated Mon Jul 13, 2026 03:37:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32092991033910267,67cyclictest3095-21kworker/0:4+events02:59:180
32095991032010307,8cyclictest0-21swapper/302:59:183
32094991014110131,5cyclictest0-21swapper/202:59:192
32093991013210122,5cyclictest0-21swapper/102:59:181
320949958995886,8cyclictest0-21swapper/203:34:582
320929958765822,49cyclictest3095-21kworker/0:4+events03:34:580
320959958735862,5cyclictest0-21swapper/303:34:593
320939956875677,5cyclictest0-21swapper/103:34:591
3209299765730,29cyclictest2375-21kworker/0:1+events_freezable_power_02:45:370
3209299765730,29cyclictest2375-21kworker/0:1+events_freezable_power_02:45:370
3209499737725,7cyclictest0-21swapper/202:34:392
3209499731719,7cyclictest0-21swapper/203:07:332
3209399723716,2cyclictest0-21swapper/102:34:391
3209399720710,5cyclictest0-21swapper/103:07:341
3209499713701,7cyclictest0-21swapper/203:29:302
3209499713701,7cyclictest0-21swapper/203:29:292
3209599710701,5cyclictest0-21swapper/302:34:393
3209499709697,7cyclictest0-21swapper/203:18:312
3209599701694,3cyclictest0-21swapper/303:07:343
3209599687677,5cyclictest0-21swapper/303:29:293
3209599687677,5cyclictest0-21swapper/303:29:293
3209599683673,5cyclictest0-21swapper/303:18:313
3209299680654,21cyclictest2375-21kworker/0:1+events_freezable_power_03:07:330
3209299676661,10cyclictest3095-21kworker/0:4+events_freezable_power_02:34:400
3209299663637,20cyclictest29720-21kworker/0:6+events_freezable_power_03:29:300
3209299663637,20cyclictest29720-21kworker/0:6+events_freezable_power_03:29:300
3209299655633,17cyclictest3095-21kworker/0:4+events_freezable_power_03:18:310
3209499604594,5cyclictest0-21swapper/202:45:372
3209499604594,5cyclictest0-21swapper/202:45:372
3209599577570,3cyclictest0-21swapper/302:45:383
3209599577570,3cyclictest0-21swapper/302:45:373
3209399503488,8cyclictest0-21swapper/103:18:311
3209399502492,5cyclictest0-21swapper/103:29:291
3209399502492,5cyclictest0-21swapper/103:29:291
3209399395385,5cyclictest0-21swapper/102:45:381
3209399395385,5cyclictest0-21swapper/102:45:371
3209299734,8cyclictest8332-20Xorg03:10:440
3209299612,5cyclictest12956-21ntpq03:20:390
32092995836,18cyclictest15350irq/419-imx_drm03:05:020
32092995525,26cyclictest9450irq/76-5b050000.ethernet02:35:330
32092995019,5cyclictest2899-21ntp_offset02:40:390
32094994838,5cyclictest0-21swapper/203:20:332
32092994820,25cyclictest9450irq/76-5b050000.ethernet02:50:440
32092994820,25cyclictest9450irq/76-5b050000.ethernet02:50:440
32095994738,5cyclictest0-21swapper/303:10:403
3209399472,5cyclictest0-21swapper/102:40:381
32095994637,5cyclictest0-21swapper/303:20:333
32094994638,5cyclictest0-21swapper/203:10:382
32095994435,5cyclictest0-21swapper/303:05:013
3209399432,37cyclictest0-21swapper/102:35:391
32094994234,5cyclictest0-21swapper/203:05:052
3209399422,36cyclictest0-21swapper/103:20:371
3209399422,36cyclictest0-21swapper/102:50:221
3209399422,36cyclictest0-21swapper/102:50:221
3209399412,35cyclictest0-21swapper/103:00:451
3209499402,5cyclictest0-21swapper/202:35:292
32093994032,5cyclictest0-21swapper/103:10:421
32092993917,5cyclictest32256-21latency_hist02:30:020
32094993628,5cyclictest0-21swapper/202:50:452
32094993628,5cyclictest0-21swapper/202:50:452
32094993628,5cyclictest0-21swapper/202:40:542
32095993526,5cyclictest0-21swapper/302:40:343
32095993223,5cyclictest0-21swapper/302:35:313
32095993123,5cyclictest0-21swapper/302:50:143
32095993123,5cyclictest0-21swapper/302:50:143
32095993122,5cyclictest0-21swapper/302:30:033
3209399262,5cyclictest0-21swapper/102:30:001
3209499232,17cyclictest0-21swapper/202:30:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional