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2026-02-25 - 10:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Feb 25, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
744888998810,19cyclictest0-21swapper/422:15:164
744891997333,39cyclictest0-21swapper/622:17:326
744891997232,39cyclictest0-21swapper/620:17:526
744891997134,18cyclictest871587-21kworker/u32:5+events_unbound23:20:006
744891997113,39cyclictest362-21jbd2/sda2-822:21:416
744891997031,39cyclictest0-21swapper/620:37:136
744891996950,19cyclictest79-21ksoftirqd/623:51:126
744891996930,19cyclictest0-21swapper/619:14:576
744891996910,20cyclictest1-21systemd00:35:006
744889996849,19cyclictest0-21swapper/523:15:165
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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