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2026-01-28 - 12:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Jan 28, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3894368997614,39cyclictest3947253-21idleruntime20:45:140
3894368997536,19cyclictest3960384-21aten2.4-expect21:10:130
3894368997214,39cyclictest4023141-21taskset23:03:050
3894368997031,0cyclictest0-21swapper/022:00:190
3894368996951,0cyclictest0-21swapper/023:50:010
3894368996930,19cyclictest0-21swapper/020:32:470
3894368996829,19cyclictest1750ktimers/021:02:550
3894368996828,19cyclictest0-21swapper/022:40:030
389436899678,20cyclictest3924780-21/usr/sbin/munin20:05:230
3894368996728,19cyclictest0-21swapper/022:11:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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