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2026-05-10 - 17:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun May 10, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181867099161159,1cyclictest0-21swapper/108:25:021
1818673999191,0cyclictest0-21swapper/412:25:154
1818673998324,19cyclictest191rcu_preempt07:20:134
181867399824,59cyclictest1858490-21ld08:20:204
1818673997736,20cyclictest1876857-21kworker/u32:5+events_unbound09:20:074
181867399770,58cyclictest1931750-21kworker/u32:4+events_unbound10:39:014
1818673997557,0cyclictest0-21swapper/410:27:264
1818673997556,19cyclictest601ktimers/409:39:044
1818673997517,39cyclictest1911821-21chrt09:58:544
1818673997335,38cyclictest601ktimers/408:39:344
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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