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2026-03-04 - 15:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Mar 04, 2026 12:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
367343199590,19cyclictest877-21mta-sts-daemon10:50:156
3673431995415,39cyclictest0-21swapper/612:10:156
3673425995314,39cyclictest0-21swapper/011:35:140
3673425995314,39cyclictest0-21swapper/009:15:160
3673428995214,19cyclictest0-21swapper/309:55:163
3673428995111,39cyclictest0-21swapper/307:50:163
3673432995031,19cyclictest0-21swapper/712:20:157
367342899489,39cyclictest0-21swapper/311:40:143
3673427994811,18cyclictest0-21swapper/210:40:162
367343299478,39cyclictest0-21swapper/710:50:157
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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