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2026-02-18 - 09:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Feb 18, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5360439911213,99cyclictest0-21swapper/123:25:151
536047999233,20cyclictest577729-21munin-plugin-st20:25:035
536047999232,39cyclictest708498-21ntpq00:20:205
536047998020,59cyclictest601174-21strings21:05:185
536043997415,19cyclictest0-21swapper/122:30:171
536047997336,18cyclictest877-21mta-sts-daemon23:35:185
536047997012,39cyclictest0-21swapper/521:10:065
536047996931,19cyclictest537023-21grep19:10:165
536047996911,39cyclictest618648-21perf21:40:005
536047996829,39cyclictest0-21swapper/522:47:195
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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