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2026-02-24 - 02:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Mon Feb 23, 2026 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1057998998911,19cyclictest0-21swapper/709:00:177
1057994998644,40cyclictest776-21dbus-daemon12:20:003
1057994997618,19cyclictest1086246-21aten2.4-expect08:00:133
1057994997537,19cyclictest873-21mta-sts-daemon11:42:233
1057994997214,39cyclictest1086-21runrttasks11:22:313
1057994997033,18cyclictest511ktimers/310:15:433
1057994996910,39cyclictest1142551-21ntpq09:40:213
105799899688,59cyclictest0-21swapper/710:20:187
1057994996729,38cyclictest0-21swapper/308:30:053
1057994996628,19cyclictest0-21swapper/308:25:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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