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2026-07-27 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Mon Jul 27, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
49466099148146,1cyclictest642923-21kworker/u32:3+writeback11:43:024
494660991450,144cyclictest324-21ice-ptp-0000:f4:00.211:02:134
494660991440,142cyclictest319-21ice-ptp-0000:f4:00.011:11:054
494660991410,140cyclictest629250-21kworker/u32:2+events_unbound11:26:064
4946609913598,18cyclictest538860-21sh08:30:024
49466099130130,0cyclictest520872-21lpstat07:55:174
494660999235,38cyclictest362-21jbd2/sda2-810:46:514
49466099680,67cyclictest319-21ice-ptp-0000:f4:00.011:05:464
494660996526,19cyclictest0-21swapper/412:07:564
494658996525,19cyclictest191rcu_preempt11:15:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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