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2026-02-18 - 22:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Feb 18, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3240678995214,19cyclictest0-21swapper/510:40:155
3240678995113,19cyclictest0-21swapper/508:10:165
3240678995010,39cyclictest0-21swapper/507:50:165
3240676994810,19cyclictest0-21swapper/311:00:143
324067899479,19cyclictest0-21swapper/508:00:165
324067899468,19cyclictest0-21swapper/510:20:145
324068099457,18cyclictest0-21swapper/708:45:187
324067699456,39cyclictest0-21swapper/309:40:153
324068099413,19cyclictest0-21swapper/709:10:177
324068099413,19cyclictest0-21swapper/708:50:157
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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