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2026-07-08 - 09:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Jul 08, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203988999111110,0cyclictest2196223-21sed23:55:012
20398899910769,19cyclictest2205968-21ntpq00:10:192
2039889999355,38cyclictest874-21mta-sts-daemon19:52:432
2039889998426,39cyclictest2127840-21aten2.4_rfpower21:50:122
2039889997856,19cyclictest421ktimers/219:55:182
2039889997636,39cyclictest2216928-21ldconfig00:30:202
2039889997556,19cyclictest411rcuc/220:55:312
2039889997537,20cyclictest2203964-21vmstat00:05:242
2039889997537,19cyclictest2144010-21munin-run22:19:592
2039890997474,0cyclictest776-21dbus-daemon00:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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