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2026-01-21 - 08:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Jan 21, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
338316099120118,1cyclictest0-21swapper/022:00:120
3383164997354,18cyclictest0-21swapper/423:00:114
3383164997113,39cyclictest1073-21sshd19:19:174
338316499658,38cyclictest3422737-21sh20:20:124
3383164996526,20cyclictest0-21swapper/421:34:224
3383164996324,20cyclictest0-21swapper/400:29:594
3383164996323,39cyclictest0-21swapper/423:46:544
338316499624,39cyclictest3449101-21chrt21:07:054
3383164996223,20cyclictest0-21swapper/400:31:024
3383164996223,19cyclictest0-21swapper/423:36:224
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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