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2026-02-13 - 18:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Fri Feb 13, 2026 12:46:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1245680991520,150cyclictest0-21swapper/410:45:114
12456809911050,39cyclictest1399217-21taskset11:47:554
1245680998730,38cyclictest1368577-21timerandwakeup10:50:234
1245680997314,39cyclictest3083133-21munin-node10:55:114
1245680997130,19cyclictest1385597-21latency_hist11:25:014
124568099656,19cyclictest12508162sleep407:17:214
124568099655,39cyclictest1351818-21collect210:20:214
1245681995941,0cyclictest0-21swapper/509:05:165
1245681995941,0cyclictest0-21swapper/509:05:165
1245680995918,19cyclictest1303371-21unin-run08:55:014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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