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2026-05-01 - 05:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Fri May 01, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74287299846,59cyclictest855341-21chrt22:30:334
742872997839,20cyclictest887962-21ntpq23:30:214
742872997618,39cyclictest776-21dbus-daemon22:10:014
742872997113,39cyclictest914931-21aten2.4_rfpower00:25:154
742872997032,38cyclictest0-21swapper/423:48:074
742872997012,39cyclictest878468-21kworker/u32:2+events_unbound23:18:434
742872996931,19cyclictest913411-21ntpq00:20:194
742872996829,19cyclictest0-21swapper/422:26:144
742872996728,19cyclictest0-21swapper/419:18:454
74287299669,38cyclictest792851-21kworker/u32:0+events_unbound22:49:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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