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2026-03-21 - 03:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Fri Mar 20, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2731079991550,35cyclictest0-21swapper/611:50:166
2731074996565,0cyclictest0-21swapper/110:15:151
2731077995616,19cyclictest0-21swapper/408:50:164
2731077995414,39cyclictest0-21swapper/411:50:164
2731077995314,39cyclictest0-21swapper/410:25:144
2731074995214,19cyclictest0-21swapper/111:35:161
2731078995133,18cyclictest0-21swapper/510:20:145
2731075995131,19cyclictest871-21mta-sts-daemon10:35:162
2731075994910,19cyclictest0-21swapper/208:15:162
2731078994810,19cyclictest0-21swapper/507:10:165
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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