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2026-02-02 - 13:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Mon Feb 02, 2026 00:46:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1683356998124,18cyclictest1839415-21unixbench_singl23:55:233
1683356997416,19cyclictest1849770-21meminfo00:15:173
1683356997214,19cyclictest0-21swapper/323:26:323
1683356997152,19cyclictest511ktimers/323:05:173
1683356997113,39cyclictest1689662-21df19:20:143
1683356996930,39cyclictest1780733-21sshd22:10:193
168335699656,39cyclictest1833849-21taskset23:46:403
1683360996445,19cyclictest0-21swapper/720:00:167
1683356996344,19cyclictest511ktimers/319:46:033
1683356996223,39cyclictest0-21swapper/319:29:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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