You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-30 - 12:39
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Nov 30, 2025 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4147027999032,19cyclictest191rcu_preempt19:40:186
4147025997922,38cyclictest98137-21cron23:25:014
4147025997618,39cyclictest2630-21if_eno520:35:174
4147028997213,19cyclictest0-21swapper/700:05:197
4147027997234,19cyclictest771rcuc/600:15:166
414702599699,59cyclictest0-21swapper/422:47:084
4147025996911,39cyclictest4182706-21lpstat20:10:214
4147025996911,20cyclictest0-21swapper/423:14:374
4147025996910,21cyclictest0-21swapper/419:57:214
4147025996828,19cyclictest121699-21aten2.4_rfpower00:05:154
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional