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2026-03-08 - 10:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Mar 08, 2026 00:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1720492997961,0cyclictest0-21swapper/420:42:164
1720492997857,21cyclictest1761351-21/usr/sbin/munin20:25:014
1720492997758,0cyclictest0-21swapper/420:30:434
172049299770,58cyclictest1786562-21kworker/u32:2+events_unbound21:12:434
1720492997557,0cyclictest0-21swapper/419:38:554
1720492997557,0cyclictest0-21swapper/400:10:464
1720492997536,20cyclictest1855342-21kworker/u32:1+events_unbound23:39:424
1720492997455,0cyclictest0-21swapper/419:16:354
1720492997436,19cyclictest191rcu_preempt00:24:504
1720492997436,19cyclictest1720363-21kworker/4:0-events22:17:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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