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2026-03-02 - 02:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Mar 01, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4128438997820,39cyclictest1086-21runrttasks12:13:294
4128438997233,20cyclictest4158206-21taskset08:02:584
4128438997232,39cyclictest0-21swapper/407:17:344
4128438997132,39cyclictest0-21swapper/409:21:224
4128438997031,39cyclictest0-21swapper/409:27:574
4128438997031,39cyclictest0-21swapper/409:02:184
4128438997031,39cyclictest0-21swapper/407:35:534
4128438996931,38cyclictest0-21swapper/411:45:384
4128438996930,39cyclictest0-21swapper/407:12:344
4128438996929,39cyclictest0-21swapper/412:07:104
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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