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2026-02-11 - 03:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Feb 11, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290985999314,59cyclictest358991-21users21:10:237
29098599846,59cyclictest471770-21tail00:35:197
290985997233,38cyclictest1926-21sendmail-mta19:39:317
290985997033,18cyclictest30750irq/60-ahci[0000:00:07.0]23:55:117
290985997011,19cyclictest0-21swapper/720:45:197
290985996911,39cyclictest411191-21ntpq22:45:197
290985996911,19cyclictest0-21swapper/719:15:017
290983996910,39cyclictest450915-21kworker/5:1+ice00:00:155
29098599679,21cyclictest0-21swapper/721:26:417
290985996729,19cyclictest101550irq/39-eno2-TxRx-022:57:117
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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