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2026-03-03 - 02:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Mon Mar 02, 2026 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1192153997736,19cyclictest1362870-21latency_hist12:19:594
1192153997416,39cyclictest1-21systemd11:10:014
1192153996931,38cyclictest0-21swapper/409:21:344
1192153996930,39cyclictest0-21swapper/412:26:034
1192153996829,39cyclictest0-21swapper/408:06:134
1192153996729,38cyclictest0-21swapper/408:02:064
119215099634,19cyclictest0-21swapper/107:20:151
119215399600,40cyclictest1319319-21grep11:00:014
1192153995839,0cyclictest0-21swapper/412:08:214
1192153995819,39cyclictest1357857-21/usr/sbin/munin12:10:244
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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