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2026-01-17 - 06:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sat Jan 17, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2590206991600,158cyclictest0-21swapper/223:20:122
259020799129129,0cyclictest2653428-21apt21:00:103
25902079910831,58cyclictest2594590-21strings19:15:183
2590207999054,17cyclictest511ktimers/323:10:023
259020799813,59cyclictest2749279-21unin-run23:50:013
2590207997920,39cyclictest2777682-21latency_hist00:40:023
2590207997634,19cyclictest2628909-21ntpq20:15:203
2590207997517,39cyclictest1086-21runrttasks23:04:323
2590207997517,39cyclictest1086-21runrttasks23:04:313
2590207997030,39cyclictest2757390-21chrt00:04:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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