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2026-05-22 - 23:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Fri May 22, 2026 12:46:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
340681099802,19cyclictest0-21swapper/709:45:157
340680799790,20cyclictest0-21swapper/409:45:154
3406805997613,40cyclictest3508114-21vmstat10:10:232
3406810997214,38cyclictest3406802-21cyclictest12:00:167
3406805997255,17cyclictest0-21swapper/210:35:022
3406805997235,19cyclictest871-21mta-sts-daemon09:29:052
3406805997235,18cyclictest411rcuc/208:45:132
3406805997235,18cyclictest411rcuc/208:45:132
3406805997232,39cyclictest0-21swapper/208:19:132
3406805997133,38cyclictest0-21swapper/212:24:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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