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2026-02-19 - 22:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Thu Feb 19, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26773499856,39cyclictest70-21ksoftirqd/507:50:145
267730997315,39cyclictest342659-21cut09:25:001
267730997111,59cyclictest326282-21sh08:55:011
26773099676,39cyclictest236199-21snmpd12:06:331
267730996643,19cyclictest413-21systemd-journal12:00:011
26773099633,22cyclictest383327-21taskset10:36:301
267730996223,19cyclictest393449-21ntpq10:55:191
267730996038,19cyclictest876-21mta-sts-daemon11:16:231
267730996021,20cyclictest236199-21snmpd09:55:291
26773099591,39cyclictest328442-21chrt08:56:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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