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2026-01-15 - 05:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Thu Jan 15, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53665999214,59cyclictest224919-21chrt00:10:162
53685996910,19cyclictest0-21swapper/623:26:406
5368599689,19cyclictest0-21swapper/619:33:416
5368599678,19cyclictest0-21swapper/623:55:496
5368599678,19cyclictest0-21swapper/623:50:486
5368599678,19cyclictest0-21swapper/600:21:176
5368599645,19cyclictest0-21swapper/621:39:436
5368599635,19cyclictest0-21swapper/621:06:016
5368599623,0cyclictest153094-21/usr/sbin/munin22:05:166
5368599570,17cyclictest0-21swapper/621:19:476
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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