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2026-02-17 - 09:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Tue Feb 17, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3483472999816,59cyclictest3662573-21cat00:35:014
3483472998585,0cyclictest3511807-21expr20:00:134
3483472998527,39cyclictest3563459-21/usr/sbin/munin21:35:204
3483472998262,19cyclictest1-21systemd22:35:004
3483472997619,38cyclictest3635290-21aten2.4_rfpower23:45:134
3483472997536,39cyclictest362-21jbd2/sda2-822:49:154
3483472997519,55cyclictest0-21swapper/419:50:094
3483472997233,39cyclictest0-21swapper/420:32:304
3483472997232,39cyclictest0-21swapper/421:24:084
3483472997214,39cyclictest3615823-21kworker/u32:5+events_unbound00:36:354
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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