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2026-02-15 - 17:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 15, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
373902599145143,1cyclictest0-21swapper/208:30:132
3739027997436,19cyclictest3866989-21sh11:00:124
3739027997372,0cyclictest3753203-21munin-run07:35:014
3739027997232,39cyclictest3796756-21latency_hist08:55:014
3739027997230,41cyclictest3776877-21smartctl08:15:214
3739027997133,38cyclictest0-21swapper/408:25:234
3739027996810,39cyclictest236199-21snmpd10:07:004
373902799634,39cyclictest0-21swapper/409:05:144
3739027996225,18cyclictest601ktimers/409:30:504
3739027996124,18cyclictest601ktimers/412:19:384
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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