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2026-02-26 - 00:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Feb 25, 2026 12:46:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3427296995534,2cyclictest3474552-21kworker/u32:0+rpciod09:05:274
3427296995233,19cyclictest0-21swapper/410:48:374
3427295994829,19cyclictest0-21swapper/311:50:153
3427292994810,19cyclictest3440535-21kworker/0:2+ice08:15:150
342729799424,19cyclictest0-21swapper/509:00:175
342729799401,39cyclictest0-21swapper/507:10:155
3427296994018,22cyclictest3461964-21ntpq08:10:204
3427297993812,25cyclictest0-21swapper/507:35:155
342729799380,17cyclictest0-21swapper/510:00:155
3427296993837,1cyclictest877-21mta-sts-daemon11:40:464
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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