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2026-01-27 - 11:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Tue Jan 27, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2642489998987,2cyclictest871-21mta-sts-daemon20:52:591
2642489997535,38cyclictest2813274-21cut00:20:121
2642489997315,39cyclictest2645067-21chrt19:14:431
2642489997133,2cyclictest0-21swapper/123:59:521
264248999679,39cyclictest2762212-21ntpq22:45:191
264249099641,39cyclictest0-21swapper/222:05:162
264249099623,19cyclictest0-21swapper/221:40:152
264248999623,39cyclictest2770701-21ntpq23:00:191
2642489996223,39cyclictest870-21mta-sts-daemon22:15:011
2642489996023,18cyclictest2689890-21telnet20:35:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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