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2026-02-27 - 00:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Thu Feb 26, 2026 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
466358999235,38cyclictest874-21mta-sts-daemon08:05:152
466363998911,19cyclictest0-21swapper/711:35:157
466363998830,39cyclictest1926-21sendmail-mta09:59:597
46635899845,19cyclictest0-21swapper/211:50:152
466363997738,19cyclictest30750irq/60-ahci[0000:00:07.0]11:55:017
466363997618,19cyclictest30750irq/60-ahci[0000:00:07.0]07:39:017
466363997557,18cyclictest101550irq/39-eno2-TxRx-011:41:317
466363997537,38cyclictest101550irq/39-eno2-TxRx-011:01:437
466363997436,38cyclictest101550irq/39-eno2-TxRx-009:41:077
466363997336,37cyclictest0-21swapper/709:30:217
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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