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2026-06-08 - 14:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Mon Jun 08, 2026 00:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262417499166164,1cyclictest0-21swapper/020:30:120
26241819910931,78cyclictest0-21swapper/720:40:177
2624175999212,79cyclictest0-21swapper/120:20:171
2624177998423,39cyclictest2631545-21ntpq19:20:213
2624177997512,40cyclictest1-21systemd20:15:003
2624177997214,39cyclictest2668863-21cut20:30:133
2624177996911,19cyclictest0-21swapper/323:40:313
2624177996628,38cyclictest0-21swapper/319:15:343
2624177996528,18cyclictest0-21swapper/322:20:473
2624177996120,39cyclictest776-21dbus-daemon21:45:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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