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2026-07-01 - 03:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Jul 01, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2705278999618,39cyclictest2811564-21ld22:20:193
2705278998042,19cyclictest511ktimers/319:40:003
2705278997518,38cyclictest2719247-21kworker/u32:2+flush-8:020:30:263
2705278997333,39cyclictest0-21swapper/321:38:183
2705278997233,39cyclictest0-21swapper/319:12:003
2705278997233,39cyclictest0-21swapper/300:24:063
2705278997132,39cyclictest0-21swapper/320:11:303
2705276997133,19cyclictest0-21swapper/220:00:162
2705278996829,39cyclictest0-21swapper/321:33:113
2705279996748,19cyclictest0-21swapper/423:30:174
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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