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2026-07-28 - 22:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Tue Jul 28, 2026 12:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1612855995837,21cyclictest776-21dbus-daemon09:30:033
161285599571,37cyclictest1655246-21kworker/u32:2+events_unbound10:55:233
1612858995638,18cyclictest0-21swapper/608:25:166
1612855995637,18cyclictest1755074-21/usr/sbin/munin11:25:173
1612855995619,36cyclictest0-21swapper/310:48:403
1612855995619,36cyclictest0-21swapper/309:56:363
1612855995618,19cyclictest1626331-21sendmail_mailst07:30:223
1612855995537,0cyclictest1613058-21cat07:10:033
1612855995535,19cyclictest1751896-21cat11:19:593
1612855995519,35cyclictest0-21swapper/312:14:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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