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2026-02-04 - 02:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Tue Feb 03, 2026 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1417077991270,125cyclictest0-21swapper/108:50:121
1417076999234,39cyclictest1484423-21wc09:15:020
1417076998729,38cyclictest870-21mta-sts-daemon12:20:040
1417076997759,0cyclictest85650irq/35-eno1-TxRx-112:10:300
1417076997719,39cyclictest1530996-21munin-run10:40:000
141708199761,74cyclictest0-21swapper/508:50:125
1417080997537,18cyclictest1422876-21kworker/u32:5+events_unbound07:20:184
1417076997532,39cyclictest1537153-21kworker/u32:2+events_unbound11:15:120
1417076997436,19cyclictest1442482-21df07:55:140
1417076997234,38cyclictest101650irq/40-eno2-TxRx-112:00:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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