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2026-08-19 - 12:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Aug 19, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16879769915814,143cyclictest0-21swapper/423:15:154
16879769915720,137cyclictest0-21swapper/423:07:054
16879769915719,137cyclictest0-21swapper/423:45:194
16879769915718,138cyclictest0-21swapper/422:53:534
16879769915717,139cyclictest0-21swapper/423:55:194
16879769915714,142cyclictest0-21swapper/423:36:014
16879769915714,142cyclictest0-21swapper/422:25:194
16879769915714,142cyclictest0-21swapper/422:20:534
16879769915714,142cyclictest0-21swapper/422:20:524
16879769915713,143cyclictest0-21swapper/423:00:274
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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