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2026-02-22 - 23:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 22, 2026 12:46:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4074136996930,19cyclictest0-21swapper/409:50:314
4074136996930,19cyclictest0-21swapper/407:21:354
407413599601,39cyclictest0-21swapper/307:25:183
407413699590,40cyclictest4151920-21awk09:30:124
407413699550,55cyclictest0-21swapper/412:25:194
4074135995536,19cyclictest52-21ksoftirqd/308:36:253
4074135995536,19cyclictest52-21ksoftirqd/308:36:243
4074136995319,34cyclictest0-21swapper/410:01:174
4074136995319,15cyclictest0-21swapper/408:40:294
4074141995215,19cyclictest871ktimers/711:50:177
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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