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2026-07-25 - 09:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sat Jul 25, 2026 00:46:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3988608991150,16cyclictest0-21swapper/019:10:160
3988613997213,19cyclictest0-21swapper/523:15:165
398861599678,19cyclictest0-21swapper/722:14:257
398861599668,20cyclictest0-21swapper/722:21:177
398861599666,59cyclictest0-21swapper/700:22:007
3988615996424,19cyclictest0-21swapper/723:30:097
3988615996324,19cyclictest0-21swapper/719:28:337
3988615996323,20cyclictest3443057-21systemd-journal23:52:367
398861599624,39cyclictest4087114-21unixbench_multi22:05:237
398861599624,39cyclictest4087114-21unixbench_multi22:05:227
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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