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2026-05-14 - 20:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Thu May 14, 2026 12:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2401228991190,117cyclictest0-21swapper/410:30:134
240122499810,79cyclictest0-21swapper/010:30:120
2401228997314,19cyclictest0-21swapper/412:30:134
2401226997111,59cyclictest0-21swapper/210:05:142
2401225996929,39cyclictest0-21swapper/107:23:591
2401225996911,39cyclictest2526993-21meminfo10:55:201
240122599677,39cyclictest0-21swapper/107:30:151
2401225996628,19cyclictest2436857-21latency_hist08:15:011
2401225996426,19cyclictest101750irq/41-eno2-TxRx-210:35:191
2401225995637,19cyclictest874-21mta-sts-daemon12:01:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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