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2026-02-07 - 02:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Fri Feb 06, 2026 12:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
909968997370,2cyclictest0-21swapper/607:25:126
909965995940,1cyclictest928386-21mailstats07:40:213
909969995718,20cyclictest0-21swapper/708:10:167
909965995716,39cyclictest946343-21grep08:15:113
909965995616,39cyclictest954211-21/usr/sbin/munin08:30:173
909965995616,39cyclictest915480-21sed07:20:003
90996299560,56cyclictest0-21swapper/010:55:160
90996299560,56cyclictest0-21swapper/010:55:160
909965995516,39cyclictest876-21mta-sts-daemon08:12:403
90996599550,55cyclictest0-21swapper/311:15:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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