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2026-07-09 - 12:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Thu Jul 09, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316052399820,81cyclictest0-21swapper/523:35:175
316052399820,81cyclictest0-21swapper/523:35:165
3160519996950,19cyclictest0-21swapper/120:40:141
3160518996543,0cyclictest191rcu_preempt19:50:160
3160521995839,19cyclictest0-21swapper/322:35:363
3160521995737,1cyclictest875-21mta-sts-daemon19:16:423
3160521995737,1cyclictest875-21mta-sts-daemon19:16:413
3160520995516,19cyclictest0-21swapper/223:00:152
3160525995213,39cyclictest0-21swapper/723:10:147
3160524995214,19cyclictest0-21swapper/620:30:166
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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