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2026-07-11 - 18:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sat Jul 11, 2026 12:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
383410299131131,0cyclictest0-21swapper/209:10:132
3834107991055,99cyclictest0-21swapper/711:20:167
383410799900,90cyclictest0-21swapper/708:30:167
3834104997214,19cyclictest0-21swapper/411:18:594
3834104997214,19cyclictest0-21swapper/409:47:274
3834104996120,40cyclictest3856638-21cstates07:50:134
3834104996017,39cyclictest776-21dbus-daemon10:10:204
383410499601,39cyclictest0-21swapper/409:11:294
3834104995920,19cyclictest0-21swapper/409:07:324
383410499590,38cyclictest0-21swapper/410:55:094
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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