You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-01 - 18:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Feb 01, 2026 12:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318126899740,55cyclictest3305027-21aten2.4-expect10:55:114
3181268997315,19cyclictest1086-21runrttasks07:58:554
3181269996910,39cyclictest0-21swapper/509:15:165
318126899668,39cyclictest3293155-21sed10:30:234
318126899590,40cyclictest3279985-21/usr/sbin/munin10:10:014
3181268995738,19cyclictest601ktimers/407:17:554
3181268995738,19cyclictest601ktimers/407:17:554
3181268995617,19cyclictest236199-21snmpd12:13:454
318126899560,37cyclictest3225542-21kworker/u32:3+events_unbound08:45:114
3181268995436,18cyclictest0-21swapper/412:39:274
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional