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2026-07-29 - 05:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Wed Jul 29, 2026 00:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43498995634,18cyclictest0-21swapper/420:46:314
43498995633,19cyclictest0-21swapper/421:52:284
43498995633,19cyclictest0-21swapper/400:31:274
43498995553,1cyclictest156609-21systemctl22:35:014
43498995533,20cyclictest160856-21pmu-power22:40:214
43498995533,19cyclictest0-21swapper/423:45:594
43498995533,19cyclictest0-21swapper/423:27:274
43498995533,19cyclictest0-21swapper/423:03:234
43498995533,19cyclictest0-21swapper/422:05:434
43498995533,19cyclictest0-21swapper/421:42:514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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