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2026-03-03 - 14:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Tue Mar 03, 2026 00:46:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3881367996829,20cyclictest3897298-21kworker/0:019:46:066
3881366996526,19cyclictest0-21swapper/523:25:155
388136199580,39cyclictest4008153-21cstates23:00:120
3881361995719,38cyclictest4061602-21irqstats00:35:160
3881361995719,38cyclictest4061602-21irqstats00:35:150
3881361995719,38cyclictest0-21swapper/020:07:080
3881361995417,2cyclictest171ktimers/000:06:230
3881364995311,19cyclictest0-21swapper/322:20:153
3881367995233,19cyclictest3906090-21kworker/6:020:10:086
3881366995214,38cyclictest0-21swapper/521:45:175
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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