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2026-01-25 - 22:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sun Jan 25, 2026 12:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28498199911675,19cyclictest2996779-21irqstats11:35:174
2849819997435,19cyclictest601ktimers/410:55:014
2849819997314,59cyclictest0-21swapper/408:23:054
2849819997171,0cyclictest2983638-21awk11:10:214
2849818997033,18cyclictest2896674-21kworker/3:0+mm_percpu_wq09:15:153
2849819996930,19cyclictest0-21swapper/407:15:244
2849819996829,39cyclictest6050ktimers/408:27:134
2849819996829,39cyclictest0-21swapper/407:42:014
284981999679,39cyclictest3018498-21fschecks_count12:15:134
2849819996728,19cyclictest0-21swapper/412:39:294
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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