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2026-08-01 - 06:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sat Aug 01, 2026 00:46:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31945239911313,99cyclictest0-21swapper/021:10:160
3194527997676,0cyclictest0-21swapper/419:35:174
3194524997013,38cyclictest3194522-21cyclictest19:40:151
319452499640,62cyclictest0-21swapper/121:20:121
3194528995820,38cyclictest3194522-21cyclictest19:50:225
3194525995620,35cyclictest872-21mta-sts-daemon00:22:192
3194529995214,19cyclictest0-21swapper/620:50:166
3194527995213,20cyclictest0-21swapper/420:10:224
3194524995214,19cyclictest0-21swapper/121:10:171
3194525995113,19cyclictest0-21swapper/221:40:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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