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2026-02-08 - 03:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackfslot7.osadl.org (updated Sat Feb 07, 2026 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2164071999636,59cyclictest1086-21runrttasks08:03:134
2164071999090,0cyclictest0-21swapper/407:16:114
2164071997254,0cyclictest0-21swapper/411:53:484
2164071997113,39cyclictest2328508-21vmstat12:05:234
2164071996931,19cyclictest1086-21runrttasks12:24:104
2164071996911,39cyclictest2246466-21munin-run09:40:014
2164071996911,39cyclictest2191691-21grep08:00:024
216407199657,39cyclictest2280667-21meminfo10:40:184
216407199635,39cyclictest236199-21snmpd09:28:354
2164071996224,19cyclictest2260594-21grep10:05:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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