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2026-03-17 - 04:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackfslot7.osadl.org (updated Tue Mar 17, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509748999233,39cyclictest676873-21ntpq00:10:195
509748998729,39cyclictest592066-21grep21:35:235
509748997820,39cyclictest528795-21kworker/5:2+mm_percpu_wq20:21:435
509748997637,20cyclictest606571-21/usr/sbin/munin22:05:015
509748997436,38cyclictest70-21ksoftirqd/523:25:435
509748997436,38cyclictest556008-21kworker/5:1+mm_percpu_wq21:49:475
509748997415,59cyclictest670215-21kworker/u32:2+events_unbound00:03:115
509748997316,38cyclictest580359-21ntpq21:15:195
509748997233,39cyclictest0-21swapper/521:43:495
509748997233,39cyclictest0-21swapper/520:17:415
509748997233,39cyclictest0-21swapper/519:51:055
509748997233,39cyclictest0-21swapper/519:13:215
509748996830,38cyclictest552771-21python320:25:205
509748996730,18cyclictest362-21jbd2/sda2-822:55:175
509748996546,18cyclictest0-21swapper/519:35:135
509748996426,38cyclictest0-21swapper/519:28:325
50974899635,58cyclictest873-21mta-sts-daemon19:49:355
509750996121,1cyclictest88-21ksoftirqd/720:15:187
509748996143,18cyclictest0-21swapper/521:10:195
509748996143,18cyclictest0-21swapper/521:10:195
509746996043,17cyclictest511ktimers/323:45:173
509748995918,39cyclictest638237-21memory23:00:195
50974899591,39cyclictest545207-21kworker/u32:0+events_unbound20:45:475
509748995819,39cyclictest646185-21kworker/5:2-ice23:32:355
509748995819,39cyclictest556008-21kworker/5:1+mm_percpu_wq22:26:475
509748995739,18cyclictest0-21swapper/500:21:115
509748995739,0cyclictest0-21swapper/519:34:355
509748995719,38cyclictest0-21swapper/520:05:355
509748995718,39cyclictest556008-21kworker/5:1+mm_percpu_wq20:32:035
509748995717,39cyclictest600904-21kworker/u32:0+flush-8:022:40:115
509748995638,18cyclictest70-21ksoftirqd/520:35:165
509748995638,18cyclictest622659-21kworker/5:0+mm_percpu_wq23:09:425
509748995619,37cyclictest0-21swapper/520:40:355
509748995619,17cyclictest191rcu_preempt20:52:075
509748995617,39cyclictest677739-21kworker/5:0-mm_percpu_wq00:19:235
509748995537,18cyclictest677739-21kworker/5:0+mm_percpu_wq00:30:475
509748995537,18cyclictest556008-21kworker/5:1+mm_percpu_wq21:26:435
509748995536,19cyclictest655999-21kworker/0:123:44:115
509748995519,36cyclictest0-21swapper/500:25:115
509748995516,39cyclictest528795-21kworker/5:2+mm_percpu_wq20:01:315
509748995515,20cyclictest105-21kcompactd022:51:355
509747995518,18cyclictest601ktimers/421:10:144
509747995518,18cyclictest601ktimers/421:10:144
509748995436,18cyclictest70-21ksoftirqd/522:38:555
509748995436,18cyclictest556008-21kworker/5:1+mm_percpu_wq22:15:075
509748995436,18cyclictest556008-21kworker/5:1+mm_percpu_wq21:34:475
509748995436,18cyclictest556008-21kworker/5:1+mm_percpu_wq21:34:475
509748995435,19cyclictest513701-21awk19:15:175
509748995419,35cyclictest0-21swapper/523:53:455
509748995419,35cyclictest0-21swapper/521:50:455
509748995419,35cyclictest0-21swapper/520:12:135
509748995419,35cyclictest0-21swapper/519:20:055
509748995419,15cyclictest0-21swapper/523:21:535
509748995419,15cyclictest0-21swapper/523:11:295
509748995419,15cyclictest0-21swapper/522:10:455
509748995419,15cyclictest0-21swapper/521:04:335
509748995419,15cyclictest0-21swapper/519:57:375
509748995419,15cyclictest0-21swapper/519:43:235
509748995419,15cyclictest0-21swapper/500:35:335
509748995419,15cyclictest0-21swapper/500:05:415
509748995416,38cyclictest556008-21kworker/5:1+mm_percpu_wq20:55:315
509748995414,39cyclictest574010-21hddtemp_smartct21:05:155
509748995319,15cyclictest0-21swapper/523:37:175
509748995319,15cyclictest0-21swapper/522:24:455
509748995314,39cyclictest0-21swapper/523:58:255
509748995314,39cyclictest0-21swapper/522:09:055
509748995314,39cyclictest0-21swapper/521:58:255
509748995314,39cyclictest0-21swapper/521:23:015
509748995233,19cyclictest0-21swapper/523:17:455
509748995233,19cyclictest0-21swapper/522:46:535
509748995233,19cyclictest0-21swapper/522:31:015
509745995213,39cyclictest0-21swapper/200:00:142
509748995133,18cyclictest0-21swapper/523:48:455
509747995113,19cyclictest0-21swapper/420:45:164
509746995113,19cyclictest0-21swapper/300:25:163
509746995111,39cyclictest0-21swapper/323:30:163
509744995113,19cyclictest0-21swapper/121:15:141
509747995012,19cyclictest0-21swapper/420:10:164
509746995012,19cyclictest0-21swapper/320:40:163
509746995012,19cyclictest0-21swapper/300:00:163
509745995012,38cyclictest0-21swapper/223:25:142
509743995012,19cyclictest0-21swapper/021:10:140
509743995012,19cyclictest0-21swapper/021:10:140
509745994910,19cyclictest0-21swapper/219:55:172
509744994910,39cyclictest0-21swapper/120:25:151
509744994910,20cyclictest0-21swapper/121:45:161
509743994910,39cyclictest171ktimers/019:15:160
509750994810,19cyclictest871ktimers/721:20:167
50974599488,39cyclictest0-21swapper/219:20:162
50974699478,19cyclictest0-21swapper/322:15:163
50974599479,38cyclictest0-21swapper/200:10:152
50974499479,19cyclictest0-21swapper/119:35:161
50974399478,39cyclictest221rcuc/020:20:150
50974599468,19cyclictest0-21swapper/223:55:152
50974599468,19cyclictest0-21swapper/223:15:162
50974599468,19cyclictest0-21swapper/220:50:162
50974499468,19cyclictest0-21swapper/122:55:151
509743994527,18cyclictest0-21swapper/022:55:160
50975099433,39cyclictest0-21swapper/700:30:167
50974799424,19cyclictest0-21swapper/422:05:154
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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