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2026-03-04 - 08:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackfslot7.osadl.org (updated Wed Mar 04, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
943407997436,38cyclictest16-21ksoftirqd/023:55:180
943411996161,0cyclictest0-21swapper/400:10:344
943411996060,0cyclictest1056292-21systemd-run22:35:004
943411996060,0cyclictest0-21swapper/420:08:304
94341299590,40cyclictest0-21swapper/522:20:155
943411995959,0cyclictest0-21swapper/419:46:344
943411995959,0cyclictest0-21swapper/419:11:304
943411995959,0cyclictest0-21swapper/400:00:084
943411995858,0cyclictest0-21swapper/421:53:264
943411995858,0cyclictest0-21swapper/421:44:144
943411995819,19cyclictest0-21swapper/422:28:404
94341199570,38cyclictest954920-21kworker/u32:2+events_unbound20:14:104
943409995756,1cyclictest421ktimers/220:05:162
943412995638,0cyclictest0-21swapper/520:50:145
943411995636,19cyclictest1020747-21latency_hist21:30:024
943411995619,18cyclictest571irq_work/420:38:044
943411995618,19cyclictest1012920-21munin-run21:15:024
943411995618,0cyclictest191rcu_preempt00:36:544
94341199560,54cyclictest917591-21kworker/u32:4+events_unbound19:53:104
943411995537,0cyclictest0-21swapper/423:10:344
943411995536,19cyclictest1021202-21/usr/sbin/munin21:30:144
943411995536,19cyclictest0-21swapper/420:47:104
943411995536,0cyclictest0-21swapper/422:46:424
943411995516,39cyclictest989994-21unixbench-2d20:30:244
943411995516,39cyclictest0-21swapper/420:25:144
94341199550,55cyclictest0-21swapper/422:51:564
94341199550,36cyclictest981699-21kworker/u32:3+events_unbound20:22:344
943411995453,1cyclictest1058977-21apt-get22:40:004
943411995436,0cyclictest0-21swapper/422:20:264
943411995419,35cyclictest0-21swapper/423:38:464
943411995419,15cyclictest0-21swapper/423:31:544
943411995419,15cyclictest0-21swapper/421:38:584
943411995419,15cyclictest0-21swapper/420:58:184
943411995414,39cyclictest0-21swapper/423:50:364
94341199540,35cyclictest954920-21kworker/u32:2+events_unbound19:57:244
943412995315,19cyclictest0-21swapper/500:30:155
943411995335,18cyclictest1068490-21kworker/u32:3+flush-8:023:06:524
943411995335,18cyclictest1020420-21kworker/u32:3+flush-8:022:10:304
943411995315,18cyclictest0-21swapper/423:16:024
943411995315,18cyclictest0-21swapper/423:16:024
943411995314,39cyclictest0-21swapper/423:21:484
943411995314,39cyclictest0-21swapper/423:21:484
943411995314,39cyclictest0-21swapper/423:02:444
943411995314,39cyclictest0-21swapper/421:59:564
943411995314,39cyclictest0-21swapper/421:45:464
943411995314,39cyclictest0-21swapper/420:52:064
943411995314,39cyclictest0-21swapper/420:00:324
943411995314,39cyclictest0-21swapper/419:34:524
943411995314,39cyclictest0-21swapper/419:20:364
943411995314,39cyclictest0-21swapper/400:19:064
943411995314,39cyclictest0-21swapper/400:07:184
943409995314,39cyclictest0-21swapper/221:25:152
943408995315,19cyclictest0-21swapper/100:20:161
943411995234,18cyclictest875-21mta-sts-daemon21:05:144
943411995213,39cyclictest0-21swapper/422:02:204
943411995213,39cyclictest0-21swapper/421:21:584
943411995213,39cyclictest0-21swapper/421:17:204
943410995214,19cyclictest0-21swapper/322:35:143
943411995133,18cyclictest0-21swapper/419:18:484
943411995133,18cyclictest0-21swapper/400:33:104
943411995113,38cyclictest0-21swapper/423:48:584
943409995114,18cyclictest0-21swapper/222:25:142
943411995032,18cyclictest0-21swapper/400:29:324
943411995011,39cyclictest1061012-21ntpq22:40:204
943409995031,19cyclictest0-21swapper/219:35:152
943411994931,18cyclictest0-21swapper/419:36:424
943411994930,19cyclictest0-21swapper/422:55:104
943411994930,19cyclictest0-21swapper/421:04:424
943411994930,19cyclictest0-21swapper/419:41:144
943411994930,19cyclictest0-21swapper/419:27:124
94341199489,39cyclictest0-21swapper/423:57:324
94341199489,39cyclictest0-21swapper/422:19:364
94341199487,19cyclictest1041878-21cat22:05:244
943411994829,19cyclictest0-21swapper/420:42:244
943411994829,19cyclictest0-21swapper/420:17:004
943409994830,18cyclictest0-21swapper/221:55:162
94341199478,39cyclictest0-21swapper/423:26:484
94341199478,39cyclictest0-21swapper/400:21:104
943411994728,19cyclictest0-21swapper/423:42:264
94341299468,38cyclictest0-21swapper/522:55:155
94340899468,19cyclictest0-21swapper/122:55:151
943408994325,18cyclictest0-21swapper/123:00:181
94341399380,19cyclictest0-21swapper/621:55:166
94341299380,38cyclictest0-21swapper/521:35:165
94341299380,19cyclictest0-21swapper/522:30:135
943408993838,0cyclictest0-21swapper/123:15:161
943408993838,0cyclictest0-21swapper/123:15:161
94341299370,37cyclictest0-21swapper/500:35:145
943409993718,19cyclictest0-21swapper/221:40:172
94340999370,18cyclictest0-21swapper/221:30:162
94340999370,18cyclictest0-21swapper/220:25:152
94340999370,18cyclictest0-21swapper/219:15:162
94340899370,37cyclictest0-21swapper/119:25:161
94341399360,17cyclictest0-21swapper/623:10:136
94341399350,15cyclictest0-21swapper/623:45:146
943412993518,17cyclictest0-21swapper/523:20:155
943412993518,17cyclictest0-21swapper/523:20:155
94341299350,35cyclictest0-21swapper/519:25:165
94341099350,16cyclictest0-21swapper/320:30:163
94340999350,16cyclictest0-21swapper/219:55:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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